1 /* 2 * Copyright (c) 2010 Broadcom Corporation 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _HNDSOC_H 18 #define _HNDSOC_H 19 20 /* Include the soci specific files */ 21 #include <sbconfig.h> 22 #include <aidmp.h> 23 24 /* 25 * SOC Interconnect Address Map. 26 * All regions may not exist on all chips. 27 */ 28 #define SI_SDRAM_BASE 0x00000000 /* Physical SDRAM */ 29 #define SI_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */ 30 #define SI_PCI_MEM_SZ (64 * 1024 * 1024) 31 #define SI_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */ 32 #define SI_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */ 33 #define SI_SDRAM_R2 0x80000000 /* Region 2 for sdram (512 MB) */ 34 35 #ifdef SI_ENUM_BASE_VARIABLE 36 #define SI_ENUM_BASE (sii->pub.si_enum_base) 37 #else 38 #define SI_ENUM_BASE 0x18000000 /* Enumeration space base */ 39 #endif /* SI_ENUM_BASE_VARIABLE */ 40 41 #define SI_WRAP_BASE 0x18100000 /* Wrapper space base */ 42 #define SI_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */ 43 #define SI_MAXCORES 16 /* Max cores (this is arbitrary, for software 44 * convenience and could be changed if we 45 * make any larger chips 46 */ 47 48 #define SI_FASTRAM 0x19000000 /* On-chip RAM on chips that also have DDR */ 49 #define SI_FASTRAM_SWAPPED 0x19800000 50 51 #define SI_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */ 52 #define SI_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */ 53 #define SI_ARMCM3_ROM 0x1e000000 /* ARM Cortex-M3 ROM */ 54 #define SI_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */ 55 #define SI_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */ 56 #define SI_ARM7S_ROM 0x20000000 /* ARM7TDMI-S ROM */ 57 #define SI_ARMCM3_SRAM2 0x60000000 /* ARM Cortex-M3 SRAM Region 2 */ 58 #define SI_ARM7S_SRAM2 0x80000000 /* ARM7TDMI-S SRAM Region 2 */ 59 #define SI_ARM_FLASH1 0xffff0000 /* ARM Flash Region 1 */ 60 #define SI_ARM_FLASH1_SZ 0x00010000 /* ARM Size of Flash Region 1 */ 61 62 #define SI_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */ 63 #define SI_PCI_DMA2 0x80000000 /* Client Mode sb2pcitranslation2 (1 GB) */ 64 #define SI_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */ 65 #define SI_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2 66 * (2 ZettaBytes), low 32 bits 67 */ 68 #define SI_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2 69 * (2 ZettaBytes), high 32 bits 70 */ 71 72 /* core codes */ 73 #define NODEV_CORE_ID 0x700 /* Invalid coreid */ 74 #define CC_CORE_ID 0x800 /* chipcommon core */ 75 #define ILINE20_CORE_ID 0x801 /* iline20 core */ 76 #define SRAM_CORE_ID 0x802 /* sram core */ 77 #define SDRAM_CORE_ID 0x803 /* sdram core */ 78 #define PCI_CORE_ID 0x804 /* pci core */ 79 #define MIPS_CORE_ID 0x805 /* mips core */ 80 #define ENET_CORE_ID 0x806 /* enet mac core */ 81 #define CODEC_CORE_ID 0x807 /* v90 codec core */ 82 #define USB_CORE_ID 0x808 /* usb 1.1 host/device core */ 83 #define ADSL_CORE_ID 0x809 /* ADSL core */ 84 #define ILINE100_CORE_ID 0x80a /* iline100 core */ 85 #define IPSEC_CORE_ID 0x80b /* ipsec core */ 86 #define UTOPIA_CORE_ID 0x80c /* utopia core */ 87 #define PCMCIA_CORE_ID 0x80d /* pcmcia core */ 88 #define SOCRAM_CORE_ID 0x80e /* internal memory core */ 89 #define MEMC_CORE_ID 0x80f /* memc sdram core */ 90 #define OFDM_CORE_ID 0x810 /* OFDM phy core */ 91 #define EXTIF_CORE_ID 0x811 /* external interface core */ 92 #define D11_CORE_ID 0x812 /* 802.11 MAC core */ 93 #define APHY_CORE_ID 0x813 /* 802.11a phy core */ 94 #define BPHY_CORE_ID 0x814 /* 802.11b phy core */ 95 #define GPHY_CORE_ID 0x815 /* 802.11g phy core */ 96 #define MIPS33_CORE_ID 0x816 /* mips3302 core */ 97 #define USB11H_CORE_ID 0x817 /* usb 1.1 host core */ 98 #define USB11D_CORE_ID 0x818 /* usb 1.1 device core */ 99 #define USB20H_CORE_ID 0x819 /* usb 2.0 host core */ 100 #define USB20D_CORE_ID 0x81a /* usb 2.0 device core */ 101 #define SDIOH_CORE_ID 0x81b /* sdio host core */ 102 #define ROBO_CORE_ID 0x81c /* roboswitch core */ 103 #define ATA100_CORE_ID 0x81d /* parallel ATA core */ 104 #define SATAXOR_CORE_ID 0x81e /* serial ATA & XOR DMA core */ 105 #define GIGETH_CORE_ID 0x81f /* gigabit ethernet core */ 106 #define PCIE_CORE_ID 0x820 /* pci express core */ 107 #define NPHY_CORE_ID 0x821 /* 802.11n 2x2 phy core */ 108 #define SRAMC_CORE_ID 0x822 /* SRAM controller core */ 109 #define MINIMAC_CORE_ID 0x823 /* MINI MAC/phy core */ 110 #define ARM11_CORE_ID 0x824 /* ARM 1176 core */ 111 #define ARM7S_CORE_ID 0x825 /* ARM7tdmi-s core */ 112 #define LPPHY_CORE_ID 0x826 /* 802.11a/b/g phy core */ 113 #define PMU_CORE_ID 0x827 /* PMU core */ 114 #define SSNPHY_CORE_ID 0x828 /* 802.11n single-stream phy core */ 115 #define SDIOD_CORE_ID 0x829 /* SDIO device core */ 116 #define ARMCM3_CORE_ID 0x82a /* ARM Cortex M3 core */ 117 #define HTPHY_CORE_ID 0x82b /* 802.11n 4x4 phy core */ 118 #define MIPS74K_CORE_ID 0x82c /* mips 74k core */ 119 #define GMAC_CORE_ID 0x82d /* Gigabit MAC core */ 120 #define DMEMC_CORE_ID 0x82e /* DDR1/2 memory controller core */ 121 #define PCIERC_CORE_ID 0x82f /* PCIE Root Complex core */ 122 #define OCP_CORE_ID 0x830 /* OCP2OCP bridge core */ 123 #define SC_CORE_ID 0x831 /* shared common core */ 124 #define AHB_CORE_ID 0x832 /* OCP2AHB bridge core */ 125 #define SPIH_CORE_ID 0x833 /* SPI host core */ 126 #define I2S_CORE_ID 0x834 /* I2S core */ 127 #define DMEMS_CORE_ID 0x835 /* SDR/DDR1 memory controller core */ 128 #define DEF_SHIM_COMP 0x837 /* SHIM component in ubus/6362 */ 129 #define OOB_ROUTER_CORE_ID 0x367 /* OOB router core ID */ 130 #define DEF_AI_COMP 0xfff /* Default component, in ai chips it maps all 131 * unused address ranges 132 */ 133 134 /* There are TWO constants on all HND chips: SI_ENUM_BASE above, 135 * and chipcommon being the first core: 136 */ 137 #define SI_CC_IDX 0 138 139 /* SOC Interconnect types (aka chip types) */ 140 #define SOCI_AI 1 141 142 /* Common core control flags */ 143 #define SICF_BIST_EN 0x8000 144 #define SICF_PME_EN 0x4000 145 #define SICF_CORE_BITS 0x3ffc 146 #define SICF_FGC 0x0002 147 #define SICF_CLOCK_EN 0x0001 148 149 /* Common core status flags */ 150 #define SISF_BIST_DONE 0x8000 151 #define SISF_BIST_ERROR 0x4000 152 #define SISF_GATED_CLK 0x2000 153 #define SISF_DMA64 0x1000 154 #define SISF_CORE_BITS 0x0fff 155 156 /* A register that is common to all cores to 157 * communicate w/PMU regarding clock control. 158 */ 159 #define SI_CLK_CTL_ST 0x1e0 /* clock control and status */ 160 161 /* clk_ctl_st register */ 162 #define CCS_FORCEALP 0x00000001 /* force ALP request */ 163 #define CCS_FORCEHT 0x00000002 /* force HT request */ 164 #define CCS_FORCEILP 0x00000004 /* force ILP request */ 165 #define CCS_ALPAREQ 0x00000008 /* ALP Avail Request */ 166 #define CCS_HTAREQ 0x00000010 /* HT Avail Request */ 167 #define CCS_FORCEHWREQOFF 0x00000020 /* Force HW Clock Request Off */ 168 #define CCS_ERSRC_REQ_MASK 0x00000700 /* external resource requests */ 169 #define CCS_ERSRC_REQ_SHIFT 8 170 #define CCS_ALPAVAIL 0x00010000 /* ALP is available */ 171 #define CCS_HTAVAIL 0x00020000 /* HT is available */ 172 #define CCS_BP_ON_APL 0x00040000 /* RO: Backplane is running on ALP clock */ 173 #define CCS_BP_ON_HT 0x00080000 /* RO: Backplane is running on HT clock */ 174 #define CCS_ERSRC_STS_MASK 0x07000000 /* external resource status */ 175 #define CCS_ERSRC_STS_SHIFT 24 176 177 #define CCS0_HTAVAIL 0x00010000 /* HT avail in chipc and pcmcia on 4328a0 */ 178 #define CCS0_ALPAVAIL 0x00020000 /* ALP avail in chipc and pcmcia on 4328a0 */ 179 180 /* Not really related to SOC Interconnect, but a couple of software 181 * conventions for the use the flash space: 182 */ 183 184 /* Minimum amount of flash we support */ 185 #define FLASH_MIN 0x00020000 /* Minimum flash size */ 186 187 /* A boot/binary may have an embedded block that describes its size */ 188 #define BISZ_OFFSET 0x3e0 /* At this offset into the binary */ 189 #define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */ 190 #define BISZ_MAGIC_IDX 0 /* Word 0: magic */ 191 #define BISZ_TXTST_IDX 1 /* 1: text start */ 192 #define BISZ_TXTEND_IDX 2 /* 2: text end */ 193 #define BISZ_DATAST_IDX 3 /* 3: data start */ 194 #define BISZ_DATAEND_IDX 4 /* 4: data end */ 195 #define BISZ_BSSST_IDX 5 /* 5: bss start */ 196 #define BISZ_BSSEND_IDX 6 /* 6: bss end */ 197 #define BISZ_SIZE 7 /* descriptor size in 32-bit integers */ 198 199 #endif /* _HNDSOC_H */ 200