Searched refs:CCR2 (Results 1 – 6 of 6) sorted by relevance
| /linux-2.6.39/arch/sh/include/cpu-sh2a/cpu/ |
| D | cache.h | 21 #define CCR2 0xfffc1004 macro
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| /linux-2.6.39/drivers/net/wan/ |
| D | dscc4.c | 269 #define CCR2 0x10 macro
627 scc_writel(0x00050000, dpriv, dev, CCR2);
872 scc_writel(0x00050008 & ~RxActivate, dpriv, dev, CCR2); in dscc4_init_registers()
1078 scc_patchl(0, 0x00050000, dpriv, dev, CCR2); in dscc4_open()
1198 scc_patchl(0x00050000, 0, dpriv, dev, CCR2); in dscc4_close()
1680 scc_writel(0x08050008, dpriv, dev, CCR2); in dscc4_tx_irq()
1818 scc_patchl(RxActivate, 0, dpriv, dev, CCR2); in dscc4_rx_irq()
1873 scc_patchl(0, RxActivate, dpriv, dev, CCR2); in dscc4_rx_irq()
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| /linux-2.6.39/arch/arm/mach-omap1/ |
| D | dma.c | 81 [CCR2] = 0x24,
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| /linux-2.6.39/drivers/char/pcmcia/ |
| D | synclink_cs.c | 272 #define CCR2 0x2e macro
2907 val = read_reg(info, (unsigned char) (channel + CCR2)) & 0x3f; in mgslpc_set_rate()
2909 write_reg(info, (unsigned char) (channel + CCR2), val); in mgslpc_set_rate()
2976 write_reg(info, CHB + CCR2, 0x38); in enable_auxclk()
2978 write_reg(info, CHB + CCR2, 0x30); in enable_auxclk()
3011 val = read_reg(info, CHA + CCR2) | (BIT4 + BIT5); in loopback_enable()
3012 write_reg(info, CHA + CCR2, val); in loopback_enable()
3145 write_reg(info, CHA + CCR2, val); in hdlc_mode()
3462 write_reg(info, CHA + CCR2, 0x10); in async_mode()
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| /linux-2.6.39/arch/arm/plat-omap/ |
| D | dma.c | 231 ccr = p->dma_read(CCR2, lch); in omap_set_dma_transfer_params()
235 p->dma_write(ccr, CCR2, lch); in omap_set_dma_transfer_params()
281 w = p->dma_read(CCR2, lch); in omap_set_dma_color_mode()
296 p->dma_write(w, CCR2, lch); in omap_set_dma_color_mode()
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| /linux-2.6.39/arch/arm/plat-omap/include/plat/ |
| D | dma.h | 322 CPC, CCR2, LCH_CTRL, enumerator
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