Searched refs:CACHE_PHYSADDR_MASK (Results 1 – 6 of 6) sorted by relevance
36 if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) { in sh2a__flush_wback_region()61 __raw_writel((v & CACHE_PHYSADDR_MASK), in sh2a__flush_purge_region()84 __raw_writel((v & CACHE_PHYSADDR_MASK), in sh2a__flush_invalidate_region()89 __raw_writel((v & CACHE_PHYSADDR_MASK), in sh2a__flush_invalidate_region()91 __raw_writel((v & CACHE_PHYSADDR_MASK), in sh2a__flush_invalidate_region()119 if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) { in sh2a_flush_icache_range()
32 if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) { in sh2__flush_wback_region()50 __raw_writel((v & CACHE_PHYSADDR_MASK), in sh2__flush_purge_region()81 __raw_writel((v & CACHE_PHYSADDR_MASK), in sh2__flush_invalidate_region()
55 if ((data & CACHE_PHYSADDR_MASK) == in sh3__flush_wback_region()56 (p & CACHE_PHYSADDR_MASK)) { in sh3__flush_wback_region()
39 #define CACHE_PHYSADDR_MASK 0x1ffffc00 macro
29 #define CACHE_PHYSADDR_MASK 0x1ffffc00 macro
41 #define CACHE_PHYSADDR_MASK 0x1ffffc00 macro