Searched refs:BIT_6 (Results 1 – 13 of 13) sorted by relevance
32 #define BIT_6 0x40 macro136 #define ISP_CFG1_F128 BIT_6 /* 128-byte FIFO threshold */974 #define OF_DATA_IN BIT_6 /* Data in to initiator */978 #define OF_NO_DATA (BIT_7 | BIT_6)
483 return BIT_6; in qla1280_data_direction()485 return BIT_5 | BIT_6; in qla1280_data_direction()1179 mr |= BIT_6; in qla1280_set_target_parameters()1947 if (!(status = qla1280_mailbox_command(ha, BIT_7 | BIT_6 | BIT_4 | in qla1280_init_rings()1961 status = qla1280_mailbox_command(ha, BIT_7 | BIT_6 | BIT_5 | in qla1280_init_rings()2230 cfg1 = RD_REG_WORD(®->cfg_1) & ~(BIT_4 | BIT_5 | BIT_6); in qla1280_nvram_config()2297 status |= qla1280_mailbox_command(ha, BIT_7 | BIT_6 | BIT_2 | in qla1280_nvram_config()3987 qla1280_mailbox_command(ha, BIT_6 | BIT_3 | BIT_2 | BIT_1 | BIT_0, in qla1280_get_target_parameters()
17 #define FO1_DISABLE_LED_CTRL BIT_635 #define PDF_ACK0_CAPABLE BIT_6744 #define LCF_EXPL_LOGO BIT_6 /* Perform an explicit LOGO. */959 #define HCCRX_HOST_INT BIT_6 /* Host to RISC interrupt bit. */
64 #define BIT_6 0x40 macro594 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */611 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */743 #define MBX_6 BIT_61257 #define CF_WRITE BIT_61430 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */2513 #define DT_ISP6322 BIT_6
1619 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4; in qla2x00_update_fw_options()1632 (BIT_7 | BIT_6 | BIT_5)) >> 5; in qla2x00_update_fw_options()1637 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4; in qla2x00_update_fw_options()2305 nv->firmware_options[0] |= (BIT_6 | BIT_1); in qla2x00_nvram_config()2313 nv->firmware_options[0] &= ~BIT_6; in qla2x00_nvram_config()2332 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) == in qla2x00_nvram_config()2335 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4); in qla2x00_nvram_config()2365 if ((icb->firmware_options[1] & BIT_6) == 0) { in qla2x00_nvram_config()2390 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4; in qla2x00_nvram_config()4505 (BIT_6 | BIT_5 | BIT_4)) >> 4; in qla24xx_nvram_config()[all …]
745 options |= BIT_6; in qla25xx_create_rsp_que()
1489 mcp->mb[1] = BIT_6; in qla2x00_lip_reset()3780 mcp->mb[1] = mreq->options | BIT_6; // BIT_6 specifies 64 bit addressing in qla2x00_loopback_test()3844 mcp->mb[1] = mreq->options | BIT_6; /* BIT_6 specifies 64bit address */ in qla2x00_echo_test()
337 if (!(ha->fw_attributes & BIT_6)) { in qla25xx_setup_mode()424 (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4; in qla24xx_pci_info_str()
2227 if (rsp->options & ~BIT_6) { in qla25xx_msix_rsp_q()
970 arg1 |= (BIT_4 | BIT_6 | BIT_7); in qlcnic_config_switch_port()977 arg1 &= ~BIT_6; in qlcnic_config_switch_port()1037 esw_cfg->promisc_mode = !!(arg1 & BIT_6); in qlcnic_get_eswitch_port_config()
200 #define BIT_6 0x40 macro
687 if (adapter->capabilities & BIT_6) in qlcnic_initialize_nic()
71 #define BIT_6 0x40 macro