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Searched refs:BIT12 (Results 1 – 18 of 18) sorted by relevance

/linux-2.6.39/drivers/staging/rtl8192e/
Dr8192E_hw.h167 #define RCR_FILTER_MASK (BIT0|BIT1|BIT2|BIT3|BIT5|BIT12|BIT18|BIT19|BIT20|BIT21|BIT22|BIT23)
180 #define RCR_AICV BIT12 // Accept ICV error packet
258 #define IMR_RXFOVW BIT12 // Receive FIFO Overflow
285 #define TPPoll_StopVO BIT12 // Stop VO queue
418 #define RRSR_MCS0 BIT12
Dr8192E.h65 #define BIT12 0x00001000 macro
122 #define COMP_RATE BIT12 // For Rate Adaptive mechanism, 2006.07.02, by rcnjko. #define COMP_EVEN…
/linux-2.6.39/arch/arm/mach-integrator/include/mach/
Dbits.h38 #define BIT12 0x00001000 macro
/linux-2.6.39/drivers/staging/vt6655/
D80211hdr.h50 #define BIT12 0x00001000 macro
171 #define WLAN_GET_FC_PWRMGT(n) ((((unsigned short)(n) << 8) & (BIT12)) >> 12)
206 #define WLAN_GET_FC_PWRMGT(n) ((((unsigned short)(n)) & (BIT12)) >> 12)
/linux-2.6.39/drivers/staging/vt6656/
D80211hdr.h48 #define BIT12 0x00001000 macro
168 #define WLAN_GET_FC_PWRMGT(n) ((((WORD)(n) << 8) & (BIT12)) >> 12)
202 #define WLAN_GET_FC_PWRMGT(n) ((((WORD)(n)) & (BIT12)) >> 12)
/linux-2.6.39/drivers/staging/rtl8192u/
Dr8192U_hw.h155 #define RCR_AICV BIT12 // Accept ICV error packet
319 #define RRSR_MCS0 BIT12
Dr8192U.h64 #define BIT12 0x00001000 macro
111 #define COMP_RATE BIT12 // For Rate Adaptive mechanism, 2006.07.02, by rcnjko.
/linux-2.6.39/drivers/scsi/
Dtmscsim.h179 #define BIT12 0x00001000 macro
218 #define SRB_ABORT_SENT BIT12
Ddc395x.h63 #define BIT12 0x00001000 macro
/linux-2.6.39/include/linux/
Dsynclink.h30 #define BIT12 0x1000 macro
/linux-2.6.39/drivers/tty/
Dsynclink.c565 #define MISCSTATUS_TXC BIT12
586 #define SICR_TXC_INACTIVE BIT12
587 #define SICR_TXC (BIT13+BIT12)
1855 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12)); in shutdown()
4693 (unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12)); in usc_set_sdlc_mode()
4727 RegValue |= BIT12; in usc_set_sdlc_mode()
4769 RegValue |= ( BIT12 | BIT10 | BIT9 ); in usc_set_sdlc_mode()
4844 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8); in usc_set_sdlc_mode()
5175 case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 + BIT12; break; in usc_set_sdlc_mode()
6050 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12)); in usc_set_async_mode()
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Dsynclink_gt.c416 #define IRQ_TXIDLE BIT12
4311 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break; in sync_mode()
4312 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; in sync_mode()
4313 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; in sync_mode()
4314 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; in sync_mode()
4384 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break; in sync_mode()
4385 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; in sync_mode()
4386 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; in sync_mode()
4387 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; in sync_mode()
/linux-2.6.39/drivers/staging/rtl8192u/ieee80211/
Drtl819x_Qos.h16 #define BIT12 0x00001000 macro
/linux-2.6.39/drivers/staging/rtl8192e/ieee80211/
Drtl819x_Qos.h16 #define BIT12 0x00001000 macro
/linux-2.6.39/drivers/staging/wlags49_h2/
Dhcfdef.h101 #define BIT12 0x1000
/linux-2.6.39/drivers/staging/gma500/
Dpsb_drv.c365 #define FB_SKU_MASK (BIT12|BIT13|BIT14)
/linux-2.6.39/drivers/scsi/lpfc/
Dlpfc_hw4.h612 #define LPFC_SLI4_INTR12 BIT12
/linux-2.6.39/drivers/char/pcmcia/
Dsynclink_cs.c295 #define IRQ_UNDERRUN BIT12 // transmit data underrun