Searched refs:BFIN_IRQ (Results 1 – 5 of 5) sorted by relevance
41 #define BFIN_IRQ(x) ((x) + 7) macro43 #define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */44 #define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */45 #define IRQ_PPI_ERROR BFIN_IRQ(2) /* PPI Error */46 #define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Status */47 #define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Status */48 #define IRQ_SPI0_ERROR BFIN_IRQ(5) /* SPI0 Status */49 #define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART0 Status */50 #define IRQ_RTC BFIN_IRQ(7) /* RTC */51 #define IRQ_PPI BFIN_IRQ(8) /* DMA Channel 0 (PPI) */[all …]
41 #define BFIN_IRQ(x) ((x) + 7) macro43 #define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */44 #define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */45 #define IRQ_DMAR0_BLK BFIN_IRQ(2) /* DMAR0 Block Interrupt */46 #define IRQ_DMAR1_BLK BFIN_IRQ(3) /* DMAR1 Block Interrupt */47 #define IRQ_DMAR0_OVR BFIN_IRQ(4) /* DMAR0 Overflow Error */48 #define IRQ_DMAR1_OVR BFIN_IRQ(5) /* DMAR1 Overflow Error */49 #define IRQ_PPI_ERROR BFIN_IRQ(6) /* PPI Error */50 #define IRQ_MAC_ERROR BFIN_IRQ(7) /* MAC Status */51 #define IRQ_SPORT0_ERROR BFIN_IRQ(8) /* SPORT0 Status */[all …]
41 #define BFIN_IRQ(x) ((x) + 7) macro43 #define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */44 #define IRQ_DMAC0_ERROR BFIN_IRQ(1) /* DMAC0 Status Interrupt */45 #define IRQ_EPPI0_ERROR BFIN_IRQ(2) /* EPPI0 Error Interrupt */46 #define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Error Interrupt */47 #define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Error Interrupt */48 #define IRQ_SPI0_ERROR BFIN_IRQ(5) /* SPI0 Status(Error) Interrupt */49 #define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART0 Status(Error) Interrupt */50 #define IRQ_RTC BFIN_IRQ(7) /* RTC Interrupt */51 #define IRQ_EPPI0 BFIN_IRQ(8) /* EPPI0 Interrupt (DMA12) */[all …]
39 #define IRQ_UART2_RX BFIN_IRQ(37) /* UART2 RX USE EPP1 (DMA13) Interrupt */41 #define IRQ_UART2_TX BFIN_IRQ(38) /* UART2 RX USE EPP1 (DMA14) Interrupt */44 #define IRQ_UART2_RX BFIN_IRQ(33) /* UART2 RX (DMA18) Interrupt */46 #define IRQ_UART2_TX BFIN_IRQ(34) /* UART2 TX (DMA19) Interrupt */51 #define IRQ_UART3_RX BFIN_IRQ(64) /* UART3 RX USE PIXC IN0 (DMA15) Interrupt */53 #define IRQ_UART3_TX BFIN_IRQ(65) /* UART3 TX USE PIXC IN1 (DMA16) Interrupt */56 #define IRQ_UART3_RX BFIN_IRQ(35) /* UART3 RX (DMA20) Interrupt */58 #define IRQ_UART3_TX BFIN_IRQ(36) /* UART3 TX (DMA21) Interrupt */