1 /* 2 * Copyright (c) 2010 Broadcom Corporation 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _BCMDEVS_H 18 #define _BCMDEVS_H 19 20 /* PCI vendor IDs */ 21 #define VENDOR_BROADCOM 0x14e4 22 23 /* DONGLE VID/PIDs */ 24 #define BCM_DNGL_VID 0x0a5c 25 #define BCM_DNGL_BDC_PID 0x0bdc 26 27 #define BCM4325_D11DUAL_ID 0x431b 28 #define BCM4325_D11G_ID 0x431c 29 #define BCM4325_D11A_ID 0x431d 30 #define BCM4329_D11N_ID 0x432e /* 4329 802.11n dualband device */ 31 #define BCM4329_D11N2G_ID 0x432f /* 4329 802.11n 2.4G device */ 32 #define BCM4329_D11N5G_ID 0x4330 /* 4329 802.11n 5G device */ 33 #define BCM4329_D11NDUAL_ID 0x432e 34 35 #define BCM4319_D11N_ID 0x4337 /* 4319 802.11n dualband device */ 36 #define BCM4319_D11N2G_ID 0x4338 /* 4319 802.11n 2.4G device */ 37 #define BCM4319_D11N5G_ID 0x4339 /* 4319 802.11n 5G device */ 38 39 #define BCM43224_D11N_ID 0x4353 /* 43224 802.11n dualband device */ 40 #define BCM43225_D11N2G_ID 0x4357 /* 43225 802.11n 2.4GHz device */ 41 42 #define BCM43236_D11N_ID 0x4346 /* 43236 802.11n dualband device */ 43 #define BCM43236_D11N2G_ID 0x4347 /* 43236 802.11n 2.4GHz device */ 44 #define BCM43236_D11N5G_ID 0x4348 /* 43236 802.11n 5GHz device */ 45 46 #define BCM43421_D11N_ID 0xA99D /* 43421 802.11n dualband device */ 47 #define BCM4313_D11N2G_ID 0x4727 /* 4313 802.11n 2.4G device */ 48 #define BCM4330_D11N_ID 0x4360 /* 4330 802.11n dualband device */ 49 #define BCM4330_D11N2G_ID 0x4361 /* 4330 802.11n 2.4G device */ 50 #define BCM4330_D11N5G_ID 0x4362 /* 4330 802.11n 5G device */ 51 #define BCM4336_D11N_ID 0x4343 /* 4336 802.11n 2.4GHz device */ 52 #define BCM6362_D11N_ID 0x435f /* 6362 802.11n dualband device */ 53 #define BCM4331_D11N_ID 0x4331 /* 4331 802.11n dualband id */ 54 #define BCM4331_D11N2G_ID 0x4332 /* 4331 802.11n 2.4Ghz band id */ 55 #define BCM4331_D11N5G_ID 0x4333 /* 4331 802.11n 5Ghz band id */ 56 57 /* Chip IDs */ 58 #define BCM4313_CHIP_ID 0x4313 /* 4313 chip id */ 59 #define BCM4319_CHIP_ID 0x4319 /* 4319 chip id */ 60 61 #define BCM43224_CHIP_ID 43224 /* 43224 chipcommon chipid */ 62 #define BCM43225_CHIP_ID 43225 /* 43225 chipcommon chipid */ 63 #define BCM43228_CHIP_ID 43228 /* 43228 chipcommon chipid */ 64 #define BCM43421_CHIP_ID 43421 /* 43421 chipcommon chipid */ 65 #define BCM43235_CHIP_ID 43235 /* 43235 chipcommon chipid */ 66 #define BCM43236_CHIP_ID 43236 /* 43236 chipcommon chipid */ 67 #define BCM43238_CHIP_ID 43238 /* 43238 chipcommon chipid */ 68 #define BCM4329_CHIP_ID 0x4329 /* 4329 chipcommon chipid */ 69 #define BCM4325_CHIP_ID 0x4325 /* 4325 chipcommon chipid */ 70 #define BCM4331_CHIP_ID 0x4331 /* 4331 chipcommon chipid */ 71 #define BCM4336_CHIP_ID 0x4336 /* 4336 chipcommon chipid */ 72 #define BCM4330_CHIP_ID 0x4330 /* 4330 chipcommon chipid */ 73 #define BCM6362_CHIP_ID 0x6362 /* 6362 chipcommon chipid */ 74 75 /* these are router chips */ 76 #define BCM4716_CHIP_ID 0x4716 /* 4716 chipcommon chipid */ 77 #define BCM47162_CHIP_ID 47162 /* 47162 chipcommon chipid */ 78 #define BCM4748_CHIP_ID 0x4748 /* 4716 chipcommon chipid (OTP, RBBU) */ 79 #define BCM5356_CHIP_ID 0x5356 /* 5356 chipcommon chipid */ 80 #define BCM5357_CHIP_ID 0x5357 /* 5357 chipcommon chipid */ 81 82 /* Package IDs */ 83 #define BCM4329_289PIN_PKG_ID 0 /* 4329 289-pin package id */ 84 #define BCM4329_182PIN_PKG_ID 1 /* 4329N 182-pin package id */ 85 #define BCM4716_PKG_ID 8 /* 4716 package id */ 86 #define BCM4717_PKG_ID 9 /* 4717 package id */ 87 #define BCM4718_PKG_ID 10 /* 4718 package id */ 88 #define BCM5356_PKG_NONMODE 1 /* 5356 package without nmode suppport */ 89 #define BCM5358U_PKG_ID 8 /* 5358U package id */ 90 #define BCM5358_PKG_ID 9 /* 5358 package id */ 91 #define BCM47186_PKG_ID 10 /* 47186 package id */ 92 #define BCM5357_PKG_ID 11 /* 5357 package id */ 93 #define BCM5356U_PKG_ID 12 /* 5356U package id */ 94 #define HDLSIM5350_PKG_ID 1 /* HDL simulator package id for a 5350 */ 95 #define HDLSIM_PKG_ID 14 /* HDL simulator package id */ 96 #define HWSIM_PKG_ID 15 /* Hardware simulator package id */ 97 #define BCM43224_FAB_CSM 0x8 /* the chip is manufactured by CSM */ 98 #define BCM43224_FAB_SMIC 0xa /* the chip is manufactured by SMIC */ 99 #define BCM4336_WLBGA_PKG_ID 0x8 100 101 /* boardflags */ 102 #define BFL_RESERVED1 0x00000001 103 #define BFL_PACTRL 0x00000002 /* Board has gpio 9 controlling the PA */ 104 #define BFL_AIRLINEMODE 0x00000004 /* Board implements gpio 13 radio disable indication */ 105 #define BFL_ADCDIV 0x00000008 /* Board has the rssi ADC divider */ 106 #define BFL_ENETROBO 0x00000010 /* Board has robo switch or core */ 107 #define BFL_NOPLLDOWN 0x00000020 /* Not ok to power down the chip pll and oscillator */ 108 #define BFL_CCKHIPWR 0x00000040 /* Can do high-power CCK transmission */ 109 #define BFL_ENETADM 0x00000080 /* Board has ADMtek switch */ 110 #define BFL_ENETVLAN 0x00000100 /* Board has VLAN capability */ 111 #define BFL_NOPCI 0x00000400 /* Board leaves PCI floating */ 112 #define BFL_FEM 0x00000800 /* Board supports the Front End Module */ 113 #define BFL_EXTLNA 0x00001000 /* Board has an external LNA in 2.4GHz band */ 114 #define BFL_HGPA 0x00002000 /* Board has a high gain PA */ 115 #define BFL_RESERVED2 0x00004000 116 #define BFL_ALTIQ 0x00008000 /* Alternate I/Q settings */ 117 #define BFL_NOPA 0x00010000 /* Board has no PA */ 118 #define BFL_RSSIINV 0x00020000 /* Board's RSSI uses positive slope(not TSSI) */ 119 #define BFL_PAREF 0x00040000 /* Board uses the PARef LDO */ 120 #define BFL_3TSWITCH 0x00080000 /* Board uses a triple throw switch shared with BT */ 121 #define BFL_PHASESHIFT 0x00100000 /* Board can support phase shifter */ 122 #define BFL_BUCKBOOST 0x00200000 /* Power topology uses BUCKBOOST */ 123 #define BFL_FEM_BT 0x00400000 /* Board has FEM and switch to share antenna w/ BT */ 124 #define BFL_NOCBUCK 0x00800000 /* Power topology doesn't use CBUCK */ 125 #define BFL_CCKFAVOREVM 0x01000000 /* Favor CCK EVM over spectral mask */ 126 #define BFL_PALDO 0x02000000 /* Power topology uses PALDO */ 127 #define BFL_LNLDO2_2P5 0x04000000 /* Select 2.5V as LNLDO2 output voltage */ 128 #define BFL_FASTPWR 0x08000000 129 #define BFL_UCPWRCTL_MININDX 0x08000000 /* Enforce min power index to avoid FEM damage */ 130 #define BFL_EXTLNA_5GHz 0x10000000 /* Board has an external LNA in 5GHz band */ 131 #define BFL_TRSW_1by2 0x20000000 /* Board has 2 TRSW's in 1by2 designs */ 132 #define BFL_LO_TRSW_R_5GHz 0x40000000 /* In 5G do not throw TRSW to T for clipLO gain */ 133 #define BFL_ELNA_GAINDEF 0x80000000 /* Backoff InitGain based on elna_2g/5g field 134 * when this flag is set 135 */ 136 137 /* boardflags2 */ 138 #define BFL2_RXBB_INT_REG_DIS 0x00000001 /* Board has an external rxbb regulator */ 139 #define BFL2_APLL_WAR 0x00000002 /* Flag to implement alternative A-band PLL settings */ 140 #define BFL2_TXPWRCTRL_EN 0x00000004 /* Board permits enabling TX Power Control */ 141 #define BFL2_2X4_DIV 0x00000008 /* Board supports the 2X4 diversity switch */ 142 #define BFL2_5G_PWRGAIN 0x00000010 /* Board supports 5G band power gain */ 143 #define BFL2_PCIEWAR_OVR 0x00000020 /* Board overrides ASPM and Clkreq settings */ 144 #define BFL2_CAESERS_BRD 0x00000040 /* Board is Caesers brd (unused by sw) */ 145 #define BFL2_LEGACY 0x00000080 146 #define BFL2_SKWRKFEM_BRD 0x00000100 /* 4321mcm93 board uses Skyworks FEM */ 147 #define BFL2_SPUR_WAR 0x00000200 /* Board has a WAR for clock-harmonic spurs */ 148 #define BFL2_GPLL_WAR 0x00000400 /* Flag to narrow G-band PLL loop b/w */ 149 #define BFL2_TRISTATE_LED 0x00000800 /* Tri-state the LED */ 150 #define BFL2_SINGLEANT_CCK 0x00001000 /* Tx CCK pkts on Ant 0 only */ 151 #define BFL2_2G_SPUR_WAR 0x00002000 /* WAR to reduce and avoid clock-harmonic spurs in 2G */ 152 #define BFL2_BPHY_ALL_TXCORES 0x00004000 /* Transmit bphy frames using all tx cores */ 153 #define BFL2_FCC_BANDEDGE_WAR 0x00008000 /* using 40Mhz LPF for 20Mhz bandedge channels */ 154 #define BFL2_GPLL_WAR2 0x00010000 /* Flag to widen G-band PLL loop b/w */ 155 #define BFL2_IPALVLSHIFT_3P3 0x00020000 156 #define BFL2_INTERNDET_TXIQCAL 0x00040000 /* Use internal envelope detector for TX IQCAL */ 157 #define BFL2_XTALBUFOUTEN 0x00080000 /* Keep the buffered Xtal output from radio "ON" 158 * Most drivers will turn it off without this flag 159 * to save power. 160 */ 161 162 /* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */ 163 #define BOARD_GPIO_RESERVED1 0x010 164 #define BOARD_GPIO_RESERVED2 0x020 165 #define BOARD_GPIO_RESERVED3 0x080 166 #define BOARD_GPIO_RESERVED4 0x100 167 #define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */ 168 #define BOARD_GPIO_12 0x1000 /* gpio 12 */ 169 #define BOARD_GPIO_13 0x2000 /* gpio 13 */ 170 #define BOARD_GPIO_RESERVED5 0x0800 171 #define BOARD_GPIO_RESERVED6 0x2000 172 #define BOARD_GPIO_RESERVED7 0x4000 173 #define BOARD_GPIO_RESERVED8 0x8000 174 175 #define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */ 176 #define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */ 177 #define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal power-up */ 178 #define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL power-down */ 179 180 /* power control defines */ 181 #define PLL_DELAY 150 /* us pll on delay */ 182 #define FREF_DELAY 200 /* us fref change delay */ 183 #define MIN_SLOW_CLK 32 /* us Slow clock period */ 184 #define XTAL_ON_DELAY 1000 /* us crystal power-on delay */ 185 186 /* # of GPIO pins */ 187 #define GPIO_NUMPINS 16 188 189 /* Reference board types */ 190 #define SPI_BOARD 0x0402 191 192 #endif /* _BCMDEVS_H */ 193