1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #ifndef ATH9K_H
18 #define ATH9K_H
19
20 #include <linux/etherdevice.h>
21 #include <linux/device.h>
22 #include <linux/leds.h>
23 #include <linux/completion.h>
24
25 #include "debug.h"
26 #include "common.h"
27
28 /*
29 * Header for the ath9k.ko driver core *only* -- hw code nor any other driver
30 * should rely on this file or its contents.
31 */
32
33 struct ath_node;
34
35 /* Macro to expand scalars to 64-bit objects */
36
37 #define ito64(x) (sizeof(x) == 1) ? \
38 (((unsigned long long int)(x)) & (0xff)) : \
39 (sizeof(x) == 2) ? \
40 (((unsigned long long int)(x)) & 0xffff) : \
41 ((sizeof(x) == 4) ? \
42 (((unsigned long long int)(x)) & 0xffffffff) : \
43 (unsigned long long int)(x))
44
45 /* increment with wrap-around */
46 #define INCR(_l, _sz) do { \
47 (_l)++; \
48 (_l) &= ((_sz) - 1); \
49 } while (0)
50
51 /* decrement with wrap-around */
52 #define DECR(_l, _sz) do { \
53 (_l)--; \
54 (_l) &= ((_sz) - 1); \
55 } while (0)
56
57 #define A_MAX(a, b) ((a) > (b) ? (a) : (b))
58
59 #define TSF_TO_TU(_h,_l) \
60 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
61
62 #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i))
63
64 struct ath_config {
65 u32 ath_aggr_prot;
66 u16 txpowlimit;
67 u8 cabqReadytime;
68 };
69
70 /*************************/
71 /* Descriptor Management */
72 /*************************/
73
74 #define ATH_TXBUF_RESET(_bf) do { \
75 (_bf)->bf_stale = false; \
76 (_bf)->bf_lastbf = NULL; \
77 (_bf)->bf_next = NULL; \
78 memset(&((_bf)->bf_state), 0, \
79 sizeof(struct ath_buf_state)); \
80 } while (0)
81
82 #define ATH_RXBUF_RESET(_bf) do { \
83 (_bf)->bf_stale = false; \
84 } while (0)
85
86 /**
87 * enum buffer_type - Buffer type flags
88 *
89 * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
90 * @BUF_AGGR: Indicates whether the buffer can be aggregated
91 * (used in aggregation scheduling)
92 * @BUF_XRETRY: To denote excessive retries of the buffer
93 */
94 enum buffer_type {
95 BUF_AMPDU = BIT(0),
96 BUF_AGGR = BIT(1),
97 BUF_XRETRY = BIT(2),
98 };
99
100 #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
101 #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
102 #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
103
104 #define ATH_TXSTATUS_RING_SIZE 64
105
106 struct ath_descdma {
107 void *dd_desc;
108 dma_addr_t dd_desc_paddr;
109 u32 dd_desc_len;
110 struct ath_buf *dd_bufptr;
111 };
112
113 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
114 struct list_head *head, const char *name,
115 int nbuf, int ndesc, bool is_tx);
116 void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
117 struct list_head *head);
118
119 /***********/
120 /* RX / TX */
121 /***********/
122
123 #define ATH_MAX_ANTENNA 3
124 #define ATH_RXBUF 512
125 #define ATH_TXBUF 512
126 #define ATH_TXBUF_RESERVE 5
127 #define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE)
128 #define ATH_TXMAXTRY 13
129 #define ATH_MGT_TXMAXTRY 4
130
131 #define TID_TO_WME_AC(_tid) \
132 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
133 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
134 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
135 WME_AC_VO)
136
137 #define ATH_AGGR_DELIM_SZ 4
138 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
139 /* number of delimiters for encryption padding */
140 #define ATH_AGGR_ENCRYPTDELIM 10
141 /* minimum h/w qdepth to be sustained to maximize aggregation */
142 #define ATH_AGGR_MIN_QDEPTH 2
143 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
144
145 #define IEEE80211_SEQ_SEQ_SHIFT 4
146 #define IEEE80211_SEQ_MAX 4096
147 #define IEEE80211_WEP_IVLEN 3
148 #define IEEE80211_WEP_KIDLEN 1
149 #define IEEE80211_WEP_CRCLEN 4
150 #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \
151 (IEEE80211_WEP_IVLEN + \
152 IEEE80211_WEP_KIDLEN + \
153 IEEE80211_WEP_CRCLEN))
154
155 /* return whether a bit at index _n in bitmap _bm is set
156 * _sz is the size of the bitmap */
157 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
158 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
159
160 /* return block-ack bitmap index given sequence and starting sequence */
161 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
162
163 /* returns delimiter padding required given the packet length */
164 #define ATH_AGGR_GET_NDELIM(_len) \
165 (((_len) >= ATH_AGGR_MINPLEN) ? 0 : \
166 DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ))
167
168 #define BAW_WITHIN(_start, _bawsz, _seqno) \
169 ((((_seqno) - (_start)) & 4095) < (_bawsz))
170
171 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)])
172
173 #define ATH_TX_COMPLETE_POLL_INT 1000
174
175 enum ATH_AGGR_STATUS {
176 ATH_AGGR_DONE,
177 ATH_AGGR_BAW_CLOSED,
178 ATH_AGGR_LIMITED,
179 };
180
181 #define ATH_TXFIFO_DEPTH 8
182 struct ath_txq {
183 int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */
184 u32 axq_qnum; /* ath9k hardware queue number */
185 u32 *axq_link;
186 struct list_head axq_q;
187 spinlock_t axq_lock;
188 u32 axq_depth;
189 u32 axq_ampdu_depth;
190 bool stopped;
191 bool axq_tx_inprogress;
192 struct list_head axq_acq;
193 struct list_head txq_fifo[ATH_TXFIFO_DEPTH];
194 struct list_head txq_fifo_pending;
195 u8 txq_headidx;
196 u8 txq_tailidx;
197 int pending_frames;
198 };
199
200 struct ath_atx_ac {
201 struct ath_txq *txq;
202 int sched;
203 struct list_head list;
204 struct list_head tid_q;
205 };
206
207 struct ath_frame_info {
208 int framelen;
209 u32 keyix;
210 enum ath9k_key_type keytype;
211 u8 retries;
212 u16 seqno;
213 };
214
215 struct ath_buf_state {
216 u8 bf_type;
217 u8 bfs_paprd;
218 unsigned long bfs_paprd_timestamp;
219 enum ath9k_internal_frame_type bfs_ftype;
220 };
221
222 struct ath_buf {
223 struct list_head list;
224 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
225 an aggregate) */
226 struct ath_buf *bf_next; /* next subframe in the aggregate */
227 struct sk_buff *bf_mpdu; /* enclosing frame structure */
228 void *bf_desc; /* virtual addr of desc */
229 dma_addr_t bf_daddr; /* physical addr of desc */
230 dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */
231 bool bf_stale;
232 u16 bf_flags;
233 struct ath_buf_state bf_state;
234 };
235
236 struct ath_atx_tid {
237 struct list_head list;
238 struct list_head buf_q;
239 struct ath_node *an;
240 struct ath_atx_ac *ac;
241 unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)];
242 u16 seq_start;
243 u16 seq_next;
244 u16 baw_size;
245 int tidno;
246 int baw_head; /* first un-acked tx buffer */
247 int baw_tail; /* next unused tx buffer slot */
248 int sched;
249 int paused;
250 u8 state;
251 };
252
253 struct ath_node {
254 #ifdef CONFIG_ATH9K_DEBUGFS
255 struct list_head list; /* for sc->nodes */
256 struct ieee80211_sta *sta; /* station struct we're part of */
257 #endif
258 struct ath_atx_tid tid[WME_NUM_TID];
259 struct ath_atx_ac ac[WME_NUM_AC];
260 u16 maxampdu;
261 u8 mpdudensity;
262 };
263
264 #define AGGR_CLEANUP BIT(1)
265 #define AGGR_ADDBA_COMPLETE BIT(2)
266 #define AGGR_ADDBA_PROGRESS BIT(3)
267
268 struct ath_tx_control {
269 struct ath_txq *txq;
270 struct ath_node *an;
271 int if_id;
272 enum ath9k_internal_frame_type frame_type;
273 u8 paprd;
274 };
275
276 #define ATH_TX_ERROR 0x01
277 #define ATH_TX_XRETRY 0x02
278 #define ATH_TX_BAR 0x04
279
280 /**
281 * @txq_map: Index is mac80211 queue number. This is
282 * not necessarily the same as the hardware queue number
283 * (axq_qnum).
284 */
285 struct ath_tx {
286 u16 seq_no;
287 u32 txqsetup;
288 spinlock_t txbuflock;
289 struct list_head txbuf;
290 struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
291 struct ath_descdma txdma;
292 struct ath_txq *txq_map[WME_NUM_AC];
293 };
294
295 struct ath_rx_edma {
296 struct sk_buff_head rx_fifo;
297 struct sk_buff_head rx_buffers;
298 u32 rx_fifo_hwsize;
299 };
300
301 struct ath_rx {
302 u8 defant;
303 u8 rxotherant;
304 u32 *rxlink;
305 unsigned int rxfilter;
306 spinlock_t rxbuflock;
307 struct list_head rxbuf;
308 struct ath_descdma rxdma;
309 struct ath_buf *rx_bufptr;
310 struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX];
311
312 struct sk_buff *frag;
313 };
314
315 int ath_startrecv(struct ath_softc *sc);
316 bool ath_stoprecv(struct ath_softc *sc);
317 void ath_flushrecv(struct ath_softc *sc);
318 u32 ath_calcrxfilter(struct ath_softc *sc);
319 int ath_rx_init(struct ath_softc *sc, int nbufs);
320 void ath_rx_cleanup(struct ath_softc *sc);
321 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp);
322 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
323 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
324 bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
325 void ath_draintxq(struct ath_softc *sc,
326 struct ath_txq *txq, bool retry_tx);
327 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
328 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
329 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
330 int ath_tx_init(struct ath_softc *sc, int nbufs);
331 void ath_tx_cleanup(struct ath_softc *sc);
332 int ath_txq_update(struct ath_softc *sc, int qnum,
333 struct ath9k_tx_queue_info *q);
334 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
335 struct ath_tx_control *txctl);
336 void ath_tx_tasklet(struct ath_softc *sc);
337 void ath_tx_edma_tasklet(struct ath_softc *sc);
338 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
339 u16 tid, u16 *ssn);
340 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
341 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
342
343 /********/
344 /* VIFs */
345 /********/
346
347 struct ath_vif {
348 int av_bslot;
349 bool is_bslot_active;
350 __le64 tsf_adjust; /* TSF adjustment for staggered beacons */
351 enum nl80211_iftype av_opmode;
352 struct ath_buf *av_bcbuf;
353 u8 bssid[ETH_ALEN]; /* current BSSID from config_interface */
354 };
355
356 /*******************/
357 /* Beacon Handling */
358 /*******************/
359
360 /*
361 * Regardless of the number of beacons we stagger, (i.e. regardless of the
362 * number of BSSIDs) if a given beacon does not go out even after waiting this
363 * number of beacon intervals, the game's up.
364 */
365 #define BSTUCK_THRESH (9 * ATH_BCBUF)
366 #define ATH_BCBUF 4
367 #define ATH_DEFAULT_BINTVAL 100 /* TU */
368 #define ATH_DEFAULT_BMISS_LIMIT 10
369 #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
370
371 struct ath_beacon_config {
372 int beacon_interval;
373 u16 listen_interval;
374 u16 dtim_period;
375 u16 bmiss_timeout;
376 u8 dtim_count;
377 };
378
379 struct ath_beacon {
380 enum {
381 OK, /* no change needed */
382 UPDATE, /* update pending */
383 COMMIT /* beacon sent, commit change */
384 } updateslot; /* slot time update fsm */
385
386 u32 beaconq;
387 u32 bmisscnt;
388 u32 ast_be_xmit;
389 u64 bc_tstamp;
390 struct ieee80211_vif *bslot[ATH_BCBUF];
391 int slottime;
392 int slotupdate;
393 struct ath9k_tx_queue_info beacon_qi;
394 struct ath_descdma bdma;
395 struct ath_txq *cabq;
396 struct list_head bbuf;
397 };
398
399 void ath_beacon_tasklet(unsigned long data);
400 void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif);
401 int ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_vif *vif);
402 void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp);
403 int ath_beaconq_config(struct ath_softc *sc);
404 void ath9k_set_beaconing_status(struct ath_softc *sc, bool status);
405
406 /*******/
407 /* ANI */
408 /*******/
409
410 #define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */
411 #define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */
412 #define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */
413 #define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */
414 #define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */
415 #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */
416 #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */
417
418 #define ATH_PAPRD_TIMEOUT 100 /* msecs */
419
420 void ath_hw_check(struct work_struct *work);
421 void ath_paprd_calibrate(struct work_struct *work);
422 void ath_ani_calibrate(unsigned long data);
423
424 /**********/
425 /* BTCOEX */
426 /**********/
427
428 struct ath_btcoex {
429 bool hw_timer_enabled;
430 spinlock_t btcoex_lock;
431 struct timer_list period_timer; /* Timer for BT period */
432 u32 bt_priority_cnt;
433 unsigned long bt_priority_time;
434 int bt_stomp_type; /* Types of BT stomping */
435 u32 btcoex_no_stomp; /* in usec */
436 u32 btcoex_period; /* in usec */
437 u32 btscan_no_stomp; /* in usec */
438 struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */
439 };
440
441 int ath_init_btcoex_timer(struct ath_softc *sc);
442 void ath9k_btcoex_timer_resume(struct ath_softc *sc);
443 void ath9k_btcoex_timer_pause(struct ath_softc *sc);
444
445 /********************/
446 /* LED Control */
447 /********************/
448
449 #define ATH_LED_PIN_DEF 1
450 #define ATH_LED_PIN_9287 8
451 #define ATH_LED_PIN_9485 6
452
453 #ifdef CONFIG_MAC80211_LEDS
454 void ath_init_leds(struct ath_softc *sc);
455 void ath_deinit_leds(struct ath_softc *sc);
456 #else
ath_init_leds(struct ath_softc * sc)457 static inline void ath_init_leds(struct ath_softc *sc)
458 {
459 }
460
ath_deinit_leds(struct ath_softc * sc)461 static inline void ath_deinit_leds(struct ath_softc *sc)
462 {
463 }
464 #endif
465
466
467 /* Antenna diversity/combining */
468 #define ATH_ANT_RX_CURRENT_SHIFT 4
469 #define ATH_ANT_RX_MAIN_SHIFT 2
470 #define ATH_ANT_RX_MASK 0x3
471
472 #define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50
473 #define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100
474 #define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200
475 #define ATH_ANT_DIV_COMB_INIT_COUNT 95
476 #define ATH_ANT_DIV_COMB_MAX_COUNT 100
477 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30
478 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20
479
480 #define ATH_ANT_DIV_COMB_LNA1_LNA2_DELTA -3
481 #define ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA -1
482 #define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4
483 #define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2
484 #define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2
485
486 enum ath9k_ant_div_comb_lna_conf {
487 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2,
488 ATH_ANT_DIV_COMB_LNA2,
489 ATH_ANT_DIV_COMB_LNA1,
490 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2,
491 };
492
493 struct ath_ant_comb {
494 u16 count;
495 u16 total_pkt_count;
496 bool scan;
497 bool scan_not_start;
498 int main_total_rssi;
499 int alt_total_rssi;
500 int alt_recv_cnt;
501 int main_recv_cnt;
502 int rssi_lna1;
503 int rssi_lna2;
504 int rssi_add;
505 int rssi_sub;
506 int rssi_first;
507 int rssi_second;
508 int rssi_third;
509 bool alt_good;
510 int quick_scan_cnt;
511 int main_conf;
512 enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf;
513 enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf;
514 int first_bias;
515 int second_bias;
516 bool first_ratio;
517 bool second_ratio;
518 unsigned long scan_start_time;
519 };
520
521 /********************/
522 /* Main driver core */
523 /********************/
524
525 /*
526 * Default cache line size, in bytes.
527 * Used when PCI device not fully initialized by bootrom/BIOS
528 */
529 #define DEFAULT_CACHELINE 32
530 #define ATH_REGCLASSIDS_MAX 10
531 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
532 #define ATH_MAX_SW_RETRIES 10
533 #define ATH_CHAN_MAX 255
534
535 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */
536 #define ATH_RATE_DUMMY_MARKER 0
537
538 #define SC_OP_INVALID BIT(0)
539 #define SC_OP_BEACONS BIT(1)
540 #define SC_OP_RXAGGR BIT(2)
541 #define SC_OP_TXAGGR BIT(3)
542 #define SC_OP_OFFCHANNEL BIT(4)
543 #define SC_OP_PREAMBLE_SHORT BIT(5)
544 #define SC_OP_PROTECT_ENABLE BIT(6)
545 #define SC_OP_RXFLUSH BIT(7)
546 #define SC_OP_LED_ASSOCIATED BIT(8)
547 #define SC_OP_LED_ON BIT(9)
548 #define SC_OP_TSF_RESET BIT(11)
549 #define SC_OP_BT_PRIORITY_DETECTED BIT(12)
550 #define SC_OP_BT_SCAN BIT(13)
551 #define SC_OP_ANI_RUN BIT(14)
552 #define SC_OP_ENABLE_APM BIT(15)
553
554 /* Powersave flags */
555 #define PS_WAIT_FOR_BEACON BIT(0)
556 #define PS_WAIT_FOR_CAB BIT(1)
557 #define PS_WAIT_FOR_PSPOLL_DATA BIT(2)
558 #define PS_WAIT_FOR_TX_ACK BIT(3)
559 #define PS_BEACON_SYNC BIT(4)
560
561 struct ath_rate_table;
562
563 struct ath9k_vif_iter_data {
564 const u8 *hw_macaddr; /* phy's hardware address, set
565 * before starting iteration for
566 * valid bssid mask.
567 */
568 u8 mask[ETH_ALEN]; /* bssid mask */
569 int naps; /* number of AP vifs */
570 int nmeshes; /* number of mesh vifs */
571 int nstations; /* number of station vifs */
572 int nwds; /* number of nwd vifs */
573 int nadhocs; /* number of adhoc vifs */
574 int nothers; /* number of vifs not specified above. */
575 };
576
577 struct ath_softc {
578 struct ieee80211_hw *hw;
579 struct device *dev;
580
581 int chan_idx;
582 int chan_is_ht;
583 struct survey_info *cur_survey;
584 struct survey_info survey[ATH9K_NUM_CHANNELS];
585
586 struct tasklet_struct intr_tq;
587 struct tasklet_struct bcon_tasklet;
588 struct ath_hw *sc_ah;
589 void __iomem *mem;
590 int irq;
591 spinlock_t sc_serial_rw;
592 spinlock_t sc_pm_lock;
593 spinlock_t sc_pcu_lock;
594 struct mutex mutex;
595 struct work_struct paprd_work;
596 struct work_struct hw_check_work;
597 struct completion paprd_complete;
598
599 unsigned int hw_busy_count;
600
601 u32 intrstatus;
602 u32 sc_flags; /* SC_OP_* */
603 u16 ps_flags; /* PS_* */
604 u16 curtxpow;
605 bool ps_enabled;
606 bool ps_idle;
607 short nbcnvifs;
608 short nvifs;
609 unsigned long ps_usecount;
610
611 struct ath_config config;
612 struct ath_rx rx;
613 struct ath_tx tx;
614 struct ath_beacon beacon;
615 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
616
617 #ifdef CONFIG_MAC80211_LEDS
618 bool led_registered;
619 char led_name[32];
620 struct led_classdev led_cdev;
621 #endif
622
623 struct ath9k_hw_cal_data caldata;
624 int last_rssi;
625
626 #ifdef CONFIG_ATH9K_DEBUGFS
627 struct ath9k_debug debug;
628 spinlock_t nodes_lock;
629 struct list_head nodes; /* basically, stations */
630 unsigned int tx_complete_poll_work_seen;
631 #endif
632 struct ath_beacon_config cur_beacon_conf;
633 struct delayed_work tx_complete_work;
634 struct delayed_work hw_pll_work;
635 struct ath_btcoex btcoex;
636
637 struct ath_descdma txsdma;
638
639 struct ath_ant_comb ant_comb;
640 };
641
642 void ath9k_tasklet(unsigned long data);
643 int ath_reset(struct ath_softc *sc, bool retry_tx);
644 int ath_cabq_update(struct ath_softc *);
645
ath_read_cachesize(struct ath_common * common,int * csz)646 static inline void ath_read_cachesize(struct ath_common *common, int *csz)
647 {
648 common->bus_ops->read_cachesize(common, csz);
649 }
650
651 extern struct ieee80211_ops ath9k_ops;
652 extern int ath9k_modparam_nohwcrypt;
653 extern int led_blink;
654 extern bool is_ath9k_unloaded;
655
656 irqreturn_t ath_isr(int irq, void *dev);
657 void ath9k_init_crypto(struct ath_softc *sc);
658 int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
659 const struct ath_bus_ops *bus_ops);
660 void ath9k_deinit_device(struct ath_softc *sc);
661 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw);
662 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
663 struct ath9k_channel *hchan);
664
665 void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw);
666 void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw);
667 bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode);
668 bool ath9k_uses_beacons(int type);
669
670 #ifdef CONFIG_PCI
671 int ath_pci_init(void);
672 void ath_pci_exit(void);
673 #else
ath_pci_init(void)674 static inline int ath_pci_init(void) { return 0; };
ath_pci_exit(void)675 static inline void ath_pci_exit(void) {};
676 #endif
677
678 #ifdef CONFIG_ATHEROS_AR71XX
679 int ath_ahb_init(void);
680 void ath_ahb_exit(void);
681 #else
ath_ahb_init(void)682 static inline int ath_ahb_init(void) { return 0; };
ath_ahb_exit(void)683 static inline void ath_ahb_exit(void) {};
684 #endif
685
686 void ath9k_ps_wakeup(struct ath_softc *sc);
687 void ath9k_ps_restore(struct ath_softc *sc);
688
689 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate);
690
691 void ath9k_set_bssid_mask(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
692
693 void ath_start_rfkill_poll(struct ath_softc *sc);
694 extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);
695 void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
696 struct ieee80211_vif *vif,
697 struct ath9k_vif_iter_data *iter_data);
698
699
700 #endif /* ATH9K_H */
701