1 /* 2 * arch/arm/mach-at91/include/mach/at91sam9260.h 3 * 4 * (C) 2006 Andrew Victor 5 * 6 * Common definitions. 7 * Based on AT91SAM9260 datasheet revision A (Preliminary). 8 * 9 * Includes also definitions for AT91SAM9XE and AT91SAM9G families 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #ifndef AT91SAM9260_H 18 #define AT91SAM9260_H 19 20 /* 21 * Peripheral identifiers/interrupts. 22 */ 23 #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ 24 #define AT91_ID_SYS 1 /* System Peripherals */ 25 #define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */ 26 #define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */ 27 #define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */ 28 #define AT91SAM9260_ID_ADC 5 /* Analog-to-Digital Converter */ 29 #define AT91SAM9260_ID_US0 6 /* USART 0 */ 30 #define AT91SAM9260_ID_US1 7 /* USART 1 */ 31 #define AT91SAM9260_ID_US2 8 /* USART 2 */ 32 #define AT91SAM9260_ID_MCI 9 /* Multimedia Card Interface */ 33 #define AT91SAM9260_ID_UDP 10 /* USB Device Port */ 34 #define AT91SAM9260_ID_TWI 11 /* Two-Wire Interface */ 35 #define AT91SAM9260_ID_SPI0 12 /* Serial Peripheral Interface 0 */ 36 #define AT91SAM9260_ID_SPI1 13 /* Serial Peripheral Interface 1 */ 37 #define AT91SAM9260_ID_SSC 14 /* Serial Synchronous Controller */ 38 #define AT91SAM9260_ID_TC0 17 /* Timer Counter 0 */ 39 #define AT91SAM9260_ID_TC1 18 /* Timer Counter 1 */ 40 #define AT91SAM9260_ID_TC2 19 /* Timer Counter 2 */ 41 #define AT91SAM9260_ID_UHP 20 /* USB Host port */ 42 #define AT91SAM9260_ID_EMAC 21 /* Ethernet */ 43 #define AT91SAM9260_ID_ISI 22 /* Image Sensor Interface */ 44 #define AT91SAM9260_ID_US3 23 /* USART 3 */ 45 #define AT91SAM9260_ID_US4 24 /* USART 4 */ 46 #define AT91SAM9260_ID_US5 25 /* USART 5 */ 47 #define AT91SAM9260_ID_TC3 26 /* Timer Counter 3 */ 48 #define AT91SAM9260_ID_TC4 27 /* Timer Counter 4 */ 49 #define AT91SAM9260_ID_TC5 28 /* Timer Counter 5 */ 50 #define AT91SAM9260_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ 51 #define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ 52 #define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ 53 54 55 /* 56 * User Peripheral physical base addresses. 57 */ 58 #define AT91SAM9260_BASE_TCB0 0xfffa0000 59 #define AT91SAM9260_BASE_TC0 0xfffa0000 60 #define AT91SAM9260_BASE_TC1 0xfffa0040 61 #define AT91SAM9260_BASE_TC2 0xfffa0080 62 #define AT91SAM9260_BASE_UDP 0xfffa4000 63 #define AT91SAM9260_BASE_MCI 0xfffa8000 64 #define AT91SAM9260_BASE_TWI 0xfffac000 65 #define AT91SAM9260_BASE_US0 0xfffb0000 66 #define AT91SAM9260_BASE_US1 0xfffb4000 67 #define AT91SAM9260_BASE_US2 0xfffb8000 68 #define AT91SAM9260_BASE_SSC 0xfffbc000 69 #define AT91SAM9260_BASE_ISI 0xfffc0000 70 #define AT91SAM9260_BASE_EMAC 0xfffc4000 71 #define AT91SAM9260_BASE_SPI0 0xfffc8000 72 #define AT91SAM9260_BASE_SPI1 0xfffcc000 73 #define AT91SAM9260_BASE_US3 0xfffd0000 74 #define AT91SAM9260_BASE_US4 0xfffd4000 75 #define AT91SAM9260_BASE_US5 0xfffd8000 76 #define AT91SAM9260_BASE_TCB1 0xfffdc000 77 #define AT91SAM9260_BASE_TC3 0xfffdc000 78 #define AT91SAM9260_BASE_TC4 0xfffdc040 79 #define AT91SAM9260_BASE_TC5 0xfffdc080 80 #define AT91SAM9260_BASE_ADC 0xfffe0000 81 #define AT91_BASE_SYS 0xffffe800 82 83 /* 84 * System Peripherals (offset from AT91_BASE_SYS) 85 */ 86 #define AT91_ECC (0xffffe800 - AT91_BASE_SYS) 87 #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) 88 #define AT91_SMC (0xffffec00 - AT91_BASE_SYS) 89 #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) 90 #define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) 91 #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) 92 #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) 93 #define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) 94 #define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) 95 #define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) 96 #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 97 #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) 98 #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) 99 #define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) 100 #define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) 101 #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) 102 #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) 103 104 #define AT91_USART0 AT91SAM9260_BASE_US0 105 #define AT91_USART1 AT91SAM9260_BASE_US1 106 #define AT91_USART2 AT91SAM9260_BASE_US2 107 #define AT91_USART3 AT91SAM9260_BASE_US3 108 #define AT91_USART4 AT91SAM9260_BASE_US4 109 #define AT91_USART5 AT91SAM9260_BASE_US5 110 111 112 /* 113 * Internal Memory. 114 */ 115 #define AT91SAM9260_ROM_BASE 0x00100000 /* Internal ROM base address */ 116 #define AT91SAM9260_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ 117 118 #define AT91SAM9260_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */ 119 #define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */ 120 #define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */ 121 #define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */ 122 123 #define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */ 124 125 #define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */ 126 #define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */ 127 128 #define AT91SAM9G20_ROM_BASE 0x00100000 /* Internal ROM base address */ 129 #define AT91SAM9G20_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ 130 131 #define AT91SAM9G20_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */ 132 #define AT91SAM9G20_SRAM0_SIZE SZ_16K /* Internal SRAM 0 size (16Kb) */ 133 #define AT91SAM9G20_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */ 134 #define AT91SAM9G20_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */ 135 136 #define AT91SAM9G20_UHP_BASE 0x00500000 /* USB Host controller */ 137 138 #endif 139