Searched refs:AR_RTC_9160_PLL_DIV (Results 1 – 3 of 3) sorted by relevance
465 pll |= SM(0x28, AR_RTC_9160_PLL_DIV); in ar9002_hw_compute_pll_control()467 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV); in ar9002_hw_compute_pll_control()
1005 pll |= SM(0x50, AR_RTC_9160_PLL_DIV); in ar9160_hw_compute_pll_control()1007 pll |= SM(0x58, AR_RTC_9160_PLL_DIV); in ar9160_hw_compute_pll_control()
1110 #define AR_RTC_9160_PLL_DIV 0x000003ff macro