1 /* 2 * ItLpRegSave.h 3 * Copyright (C) 2001 Mike Corrigan IBM Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 20 //===================================================================================== 21 // 22 // This control block contains the data that is shared between PLIC 23 // and the OS 24 // 25 // 26 27 #ifndef _ITLPREGSAVE_H 28 #define _ITLPREGSAVE_H 29 30 struct ItLpRegSave 31 { 32 u32 xDesc; // Eye catcher "LpRS" ebcdic 000-003 33 u16 xSize; // Size of this class 004-005 34 u8 xInUse; // Area is live 006-007 35 u8 xRsvd1[9]; // Reserved 007-00F 36 37 u8 xFixedRegSave[352]; // Fixed Register Save Area 010-16F 38 u32 xCTRL; // Control Register 170-173 39 u32 xDEC; // Decrementer 174-177 40 u32 xFPSCR; // FP Status and Control Reg 178-17B 41 u32 xPVR; // Processor Version Number 17C-17F 42 43 u64 xMMCR0; // Monitor Mode Control Reg 0 180-187 44 u32 xPMC1; // Perf Monitor Counter 1 188-18B 45 u32 xPMC2; // Perf Monitor Counter 2 18C-18F 46 u32 xPMC3; // Perf Monitor Counter 3 190-193 47 u32 xPMC4; // Perf Monitor Counter 4 194-197 48 u32 xPIR; // Processor ID Reg 198-19B 49 50 u32 xMMCR1; // Monitor Mode Control Reg 1 19C-19F 51 u32 xMMCRA; // Monitor Mode Control Reg A 1A0-1A3 52 u32 xPMC5; // Perf Monitor Counter 5 1A4-1A7 53 u32 xPMC6; // Perf Monitor Counter 6 1A8-1AB 54 u32 xPMC7; // Perf Monitor Counter 7 1AC-1AF 55 u32 xPMC8; // Perf Monitor Counter 8 1B0-1B3 56 u32 xTSC; // Thread Switch Control 1B4-1B7 57 u32 xTST; // Thread Switch Timeout 1B8-1BB 58 u32 xRsvd; // Reserved 1BC-1BF 59 60 u64 xACCR; // Address Compare Control Reg 1C0-1C7 61 u64 xIMR; // Instruction Match Register 1C8-1CF 62 u64 xSDR1; // Storage Description Reg 1 1D0-1D7 63 u64 xSPRG0; // Special Purpose Reg General0 1D8-1DF 64 u64 xSPRG1; // Special Purpose Reg General1 1E0-1E7 65 u64 xSPRG2; // Special Purpose Reg General2 1E8-1EF 66 u64 xSPRG3; // Special Purpose Reg General3 1F0-1F7 67 u64 xTB; // Time Base Register 1F8-1FF 68 69 u64 xFPR[32]; // Floating Point Registers 200-2FF 70 71 u64 xMSR; // Machine State Register 300-307 72 u64 xNIA; // Next Instruction Address 308-30F 73 74 u64 xDABR; // Data Address Breakpoint Reg 310-317 75 u64 xIABR; // Inst Address Breakpoint Reg 318-31F 76 77 u64 xHID0; // HW Implementation Dependent0 320-327 78 79 u64 xHID4; // HW Implementation Dependent4 328-32F 80 u64 xSCOMd; // SCON Data Reg (SPRG4) 330-337 81 u64 xSCOMc; // SCON Command Reg (SPRG5) 338-33F 82 u64 xSDAR; // Sample Data Address Register 340-347 83 u64 xSIAR; // Sample Inst Address Register 348-34F 84 85 u8 xRsvd3[176]; // Reserved 350-3FF 86 }; 87 #endif // _ITLPREGSAVE_H 88