1 /* 2 * ItLpNaca.h 3 * Copyright (C) 2001 Mike Corrigan IBM Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 20 //============================================================================= 21 // 22 // This control block contains the data that is shared between the 23 // hypervisor (PLIC) and the OS. 24 // 25 //============================================================================= 26 27 28 #ifndef _ITLPNACA_H 29 #define _ITLPNACA_H 30 31 struct ItLpNaca 32 { 33 //============================================================================= 34 // CACHE_LINE_1 0x0000 - 0x007F Contains read-only data 35 //============================================================================= 36 u32 xDesc; // Eye catcher x00-x03 37 u16 xSize; // Size of this class x04-x05 38 u16 xIntHdlrOffset; // Offset to IntHdlr array x06-x07 39 u8 xMaxIntHdlrEntries; // Number of entries in array x08-x08 40 u8 xPrimaryLpIndex; // LP Index of Primary x09-x09 41 u8 xServiceLpIndex; // LP Ind of Service Focal Pointx0A-x0A 42 u8 xLpIndex; // LP Index x0B-x0B 43 u16 xMaxLpQueues; // Number of allocated queues x0C-x0D 44 u16 xLpQueueOffset; // Offset to start of LP queues x0E-x0F 45 u8 xPirEnvironMode:8; // Piranha or hardware x10-x10 46 u8 xPirConsoleMode:8; // Piranha console indicator x11-x11 47 u8 xPirDasdMode:8; // Piranha dasd indicator x12-x12 48 u8 xRsvd1_0[5]; // Reserved for Piranha related x13-x17 49 u8 xLparInstalled:1; // Is LPAR installed on system x18-x1F 50 u8 xSysPartitioned:1; // Is the system partitioned ... 51 u8 xHwSyncedTBs:1; // Hardware synced TBs ... 52 u8 xIntProcUtilHmt:1; // Utilize HMT for interrupts ... 53 u8 xRsvd1_1:4; // Reserved ... 54 u8 xSpVpdFormat:8; // VPD areas are in CSP format ... 55 u8 xIntProcRatio:8; // Ratio of int procs to procs ... 56 u8 xRsvd1_2[5]; // Reserved ... 57 u16 xRsvd1_3; // Reserved x20-x21 58 u16 xPlicVrmIndex; // VRM index of PLIC x22-x23 59 u16 xMinSupportedSlicVrmInd;// Min supported OS VRM index x24-x25 60 u16 xMinCompatableSlicVrmInd;// Min compatable OS VRM index x26-x27 61 u64 xLoadAreaAddr; // ER address of load area x28-x2F 62 u32 xLoadAreaChunks; // Chunks for the load area x30-x33 63 u32 xPaseSysCallCRMask; // Mask used to test CR before x34-x37 64 // doing an ASR switch on PASE 65 // system call. 66 u64 xSlicSegmentTablePtr; // Pointer to Slic seg table. x38-x3f 67 u8 xRsvd1_4[64]; // x40-x7F 68 69 //============================================================================= 70 // CACHE_LINE_2 0x0080 - 0x00FF Contains local read-write data 71 //============================================================================= 72 u8 xRsvd2_0[128]; // Reserved x00-x7F 73 74 //============================================================================= 75 // CACHE_LINE_3-6 0x0100 - 0x02FF Contains LP Queue indicators 76 // NB: Padding required to keep xInterrruptHdlr at x300 which is required 77 // for v4r4 PLIC. 78 //============================================================================= 79 u8 xOldLpQueue[128]; // LP Queue needed for v4r4 100-17F 80 u8 xRsvd3_0[384]; // Reserved 180-2FF 81 //============================================================================= 82 // CACHE_LINE_7-8 0x0300 - 0x03FF Contains the address of the OS interrupt 83 // handlers 84 //============================================================================= 85 u64 xInterruptHdlr[32]; // Interrupt handlers 300-x3FF 86 }; 87 88 //============================================================================= 89 90 #endif // _ITLPNACA_H 91