1 /*
2 Written 1998-2000 by Donald Becker.
3
4 This software may be used and distributed according to the terms of
5 the GNU General Public License (GPL), incorporated herein by reference.
6 Drivers based on or derived from this code fall under the GPL and must
7 retain the authorship, copyright and license notice. This file is not
8 a complete program and may only be used when the entire operating
9 system is licensed under the GPL.
10
11 The author may be reached as becker@scyld.com, or C/O
12 Scyld Computing Corporation
13 410 Severn Ave., Suite 210
14 Annapolis MD 21403
15
16 Support information and updates available at
17 http://www.scyld.com/network/pci-skeleton.html
18
19 Linux kernel updates:
20
21 Version 2.51, Nov 17, 2001 (jgarzik):
22 - Add ethtool support
23 - Replace some MII-related magic numbers with constants
24
25 */
26
27 #define DRV_NAME "fealnx"
28 #define DRV_VERSION "2.51"
29 #define DRV_RELDATE "Nov-17-2001"
30
31 static int debug; /* 1-> print debug message */
32 static int max_interrupt_work = 20;
33
34 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). */
35 static int multicast_filter_limit = 32;
36
37 /* Set the copy breakpoint for the copy-only-tiny-frames scheme. */
38 /* Setting to > 1518 effectively disables this feature. */
39 static int rx_copybreak;
40
41 /* Used to pass the media type, etc. */
42 /* Both 'options[]' and 'full_duplex[]' should exist for driver */
43 /* interoperability. */
44 /* The media type is usually passed in 'options[]'. */
45 #define MAX_UNITS 8 /* More are supported, limit only on options */
46 static int options[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
47 static int full_duplex[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
48
49 /* Operational parameters that are set at compile time. */
50 /* Keep the ring sizes a power of two for compile efficiency. */
51 /* The compiler will convert <unsigned>'%'<2^N> into a bit mask. */
52 /* Making the Tx ring too large decreases the effectiveness of channel */
53 /* bonding and packet priority. */
54 /* There are no ill effects from too-large receive rings. */
55 // 88-12-9 modify,
56 // #define TX_RING_SIZE 16
57 // #define RX_RING_SIZE 32
58 #define TX_RING_SIZE 6
59 #define RX_RING_SIZE 12
60 #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct fealnx_desc)
61 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct fealnx_desc)
62
63 /* Operational parameters that usually are not changed. */
64 /* Time in jiffies before concluding the transmitter is hung. */
65 #define TX_TIMEOUT (2*HZ)
66
67 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */
68
69
70 /* Include files, designed to support most kernel versions 2.0.0 and later. */
71 #include <linux/module.h>
72 #include <linux/kernel.h>
73 #include <linux/sched.h>
74 #include <linux/string.h>
75 #include <linux/timer.h>
76 #include <linux/errno.h>
77 #include <linux/ioport.h>
78 #include <linux/slab.h>
79 #include <linux/interrupt.h>
80 #include <linux/pci.h>
81 #include <linux/netdevice.h>
82 #include <linux/etherdevice.h>
83 #include <linux/skbuff.h>
84 #include <linux/init.h>
85 #include <linux/mii.h>
86 #include <linux/ethtool.h>
87 #include <linux/crc32.h>
88 #include <linux/delay.h>
89
90 #include <asm/processor.h> /* Processor type for cache alignment. */
91 #include <asm/bitops.h>
92 #include <asm/io.h>
93 #include <asm/uaccess.h>
94
95 /* These identify the driver base version and may not be removed. */
96 static char version[] __devinitdata =
97 KERN_INFO DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE "\n";
98
99
100 /* This driver was written to use PCI memory space, however some x86 systems
101 work only with I/O space accesses. */
102 #ifndef __alpha__
103 #define USE_IO_OPS
104 #endif
105
106 #ifdef USE_IO_OPS
107 #undef readb
108 #undef readw
109 #undef readl
110 #undef writeb
111 #undef writew
112 #undef writel
113 #define readb inb
114 #define readw inw
115 #define readl inl
116 #define writeb outb
117 #define writew outw
118 #define writel outl
119 #endif
120
121 /* Kernel compatibility defines, some common to David Hinds' PCMCIA package. */
122 /* This is only in the support-all-kernels source code. */
123
124 #define RUN_AT(x) (jiffies + (x))
125
126 MODULE_AUTHOR("Myson or whoever");
127 MODULE_DESCRIPTION("Myson MTD-8xx 100/10M Ethernet PCI Adapter Driver");
128 MODULE_LICENSE("GPL");
129 MODULE_PARM(max_interrupt_work, "i");
130 //MODULE_PARM(min_pci_latency, "i");
131 MODULE_PARM(debug, "i");
132 MODULE_PARM(rx_copybreak, "i");
133 MODULE_PARM(multicast_filter_limit, "i");
134 MODULE_PARM(options, "1-" __MODULE_STRING(MAX_UNITS) "i");
135 MODULE_PARM(full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i");
136 MODULE_PARM_DESC(max_interrupt_work, "fealnx maximum events handled per interrupt");
137 MODULE_PARM_DESC(debug, "fealnx enable debugging (0-1)");
138 MODULE_PARM_DESC(rx_copybreak, "fealnx copy breakpoint for copy-only-tiny-frames");
139 MODULE_PARM_DESC(multicast_filter_limit, "fealnx maximum number of filtered multicast addresses");
140 MODULE_PARM_DESC(options, "fealnx: Bits 0-3: media type, bit 17: full duplex");
141 MODULE_PARM_DESC(full_duplex, "fealnx full duplex setting(s) (1)");
142
143 #define MIN_REGION_SIZE 136
144
145 enum pci_flags_bit {
146 PCI_USES_IO = 1,
147 PCI_USES_MEM = 2,
148 PCI_USES_MASTER = 4,
149 PCI_ADDR0 = 0x10 << 0,
150 PCI_ADDR1 = 0x10 << 1,
151 PCI_ADDR2 = 0x10 << 2,
152 PCI_ADDR3 = 0x10 << 3,
153 };
154
155 /* A chip capabilities table, matching the entries in pci_tbl[] above. */
156 enum chip_capability_flags {
157 HAS_MII_XCVR,
158 HAS_CHIP_XCVR,
159 };
160
161 /* 89/6/13 add, */
162 /* for different PHY */
163 enum phy_type_flags {
164 MysonPHY = 1,
165 AhdocPHY = 2,
166 SeeqPHY = 3,
167 MarvellPHY = 4,
168 Myson981 = 5,
169 LevelOnePHY = 6,
170 OtherPHY = 10,
171 };
172
173 struct chip_info {
174 char *chip_name;
175 int io_size;
176 int flags;
177 };
178
179 static struct chip_info skel_netdrv_tbl[] = {
180 {"100/10M Ethernet PCI Adapter", 136, HAS_MII_XCVR},
181 {"100/10M Ethernet PCI Adapter", 136, HAS_CHIP_XCVR},
182 {"1000/100/10M Ethernet PCI Adapter", 136, HAS_MII_XCVR},
183 };
184
185 /* Offsets to the Command and Status Registers. */
186 enum fealnx_offsets {
187 PAR0 = 0x0, /* physical address 0-3 */
188 PAR1 = 0x04, /* physical address 4-5 */
189 MAR0 = 0x08, /* multicast address 0-3 */
190 MAR1 = 0x0C, /* multicast address 4-7 */
191 FAR0 = 0x10, /* flow-control address 0-3 */
192 FAR1 = 0x14, /* flow-control address 4-5 */
193 TCRRCR = 0x18, /* receive & transmit configuration */
194 BCR = 0x1C, /* bus command */
195 TXPDR = 0x20, /* transmit polling demand */
196 RXPDR = 0x24, /* receive polling demand */
197 RXCWP = 0x28, /* receive current word pointer */
198 TXLBA = 0x2C, /* transmit list base address */
199 RXLBA = 0x30, /* receive list base address */
200 ISR = 0x34, /* interrupt status */
201 IMR = 0x38, /* interrupt mask */
202 FTH = 0x3C, /* flow control high/low threshold */
203 MANAGEMENT = 0x40, /* bootrom/eeprom and mii management */
204 TALLY = 0x44, /* tally counters for crc and mpa */
205 TSR = 0x48, /* tally counter for transmit status */
206 BMCRSR = 0x4c, /* basic mode control and status */
207 PHYIDENTIFIER = 0x50, /* phy identifier */
208 ANARANLPAR = 0x54, /* auto-negotiation advertisement and link
209 partner ability */
210 ANEROCR = 0x58, /* auto-negotiation expansion and pci conf. */
211 BPREMRPSR = 0x5c, /* bypass & receive error mask and phy status */
212 };
213
214 /* Bits in the interrupt status/enable registers. */
215 /* The bits in the Intr Status/Enable registers, mostly interrupt sources. */
216 enum intr_status_bits {
217 RFCON = 0x00020000, /* receive flow control xon packet */
218 RFCOFF = 0x00010000, /* receive flow control xoff packet */
219 LSCStatus = 0x00008000, /* link status change */
220 ANCStatus = 0x00004000, /* autonegotiation completed */
221 FBE = 0x00002000, /* fatal bus error */
222 FBEMask = 0x00001800, /* mask bit12-11 */
223 ParityErr = 0x00000000, /* parity error */
224 TargetErr = 0x00001000, /* target abort */
225 MasterErr = 0x00000800, /* master error */
226 TUNF = 0x00000400, /* transmit underflow */
227 ROVF = 0x00000200, /* receive overflow */
228 ETI = 0x00000100, /* transmit early int */
229 ERI = 0x00000080, /* receive early int */
230 CNTOVF = 0x00000040, /* counter overflow */
231 RBU = 0x00000020, /* receive buffer unavailable */
232 TBU = 0x00000010, /* transmit buffer unavilable */
233 TI = 0x00000008, /* transmit interrupt */
234 RI = 0x00000004, /* receive interrupt */
235 RxErr = 0x00000002, /* receive error */
236 };
237
238 /* Bits in the NetworkConfig register, W for writing, R for reading */
239 /* FIXME: some names are invented by me. Marked with (name?) */
240 /* If you have docs and know bit names, please fix 'em */
241 enum rx_mode_bits {
242 CR_W_ENH = 0x02000000, /* enhanced mode (name?) */
243 CR_W_FD = 0x00100000, /* full duplex */
244 CR_W_PS10 = 0x00080000, /* 10 mbit */
245 CR_W_TXEN = 0x00040000, /* tx enable (name?) */
246 CR_W_PS1000 = 0x00010000, /* 1000 mbit */
247 /* CR_W_RXBURSTMASK= 0x00000e00, Im unsure about this */
248 CR_W_RXMODEMASK = 0x000000e0,
249 CR_W_PROM = 0x00000080, /* promiscuous mode */
250 CR_W_AB = 0x00000040, /* accept broadcast */
251 CR_W_AM = 0x00000020, /* accept mutlicast */
252 CR_W_ARP = 0x00000008, /* receive runt pkt */
253 CR_W_ALP = 0x00000004, /* receive long pkt */
254 CR_W_SEP = 0x00000002, /* receive error pkt */
255 CR_W_RXEN = 0x00000001, /* rx enable (unicast?) (name?) */
256
257 CR_R_TXSTOP = 0x04000000, /* tx stopped (name?) */
258 CR_R_FD = 0x00100000, /* full duplex detected */
259 CR_R_PS10 = 0x00080000, /* 10 mbit detected */
260 CR_R_RXSTOP = 0x00008000, /* rx stopped (name?) */
261 };
262
263 /* The Tulip Rx and Tx buffer descriptors. */
264 struct fealnx_desc {
265 s32 status;
266 s32 control;
267 u32 buffer;
268 u32 next_desc;
269 struct fealnx_desc *next_desc_logical;
270 struct sk_buff *skbuff;
271 u32 reserved1;
272 u32 reserved2;
273 };
274
275 /* Bits in network_desc.status */
276 enum rx_desc_status_bits {
277 RXOWN = 0x80000000, /* own bit */
278 FLNGMASK = 0x0fff0000, /* frame length */
279 FLNGShift = 16,
280 MARSTATUS = 0x00004000, /* multicast address received */
281 BARSTATUS = 0x00002000, /* broadcast address received */
282 PHYSTATUS = 0x00001000, /* physical address received */
283 RXFSD = 0x00000800, /* first descriptor */
284 RXLSD = 0x00000400, /* last descriptor */
285 ErrorSummary = 0x80, /* error summary */
286 RUNT = 0x40, /* runt packet received */
287 LONG = 0x20, /* long packet received */
288 FAE = 0x10, /* frame align error */
289 CRC = 0x08, /* crc error */
290 RXER = 0x04, /* receive error */
291 };
292
293 enum rx_desc_control_bits {
294 RXIC = 0x00800000, /* interrupt control */
295 RBSShift = 0,
296 };
297
298 enum tx_desc_status_bits {
299 TXOWN = 0x80000000, /* own bit */
300 JABTO = 0x00004000, /* jabber timeout */
301 CSL = 0x00002000, /* carrier sense lost */
302 LC = 0x00001000, /* late collision */
303 EC = 0x00000800, /* excessive collision */
304 UDF = 0x00000400, /* fifo underflow */
305 DFR = 0x00000200, /* deferred */
306 HF = 0x00000100, /* heartbeat fail */
307 NCRMask = 0x000000ff, /* collision retry count */
308 NCRShift = 0,
309 };
310
311 enum tx_desc_control_bits {
312 TXIC = 0x80000000, /* interrupt control */
313 ETIControl = 0x40000000, /* early transmit interrupt */
314 TXLD = 0x20000000, /* last descriptor */
315 TXFD = 0x10000000, /* first descriptor */
316 CRCEnable = 0x08000000, /* crc control */
317 PADEnable = 0x04000000, /* padding control */
318 RetryTxLC = 0x02000000, /* retry late collision */
319 PKTSMask = 0x3ff800, /* packet size bit21-11 */
320 PKTSShift = 11,
321 TBSMask = 0x000007ff, /* transmit buffer bit 10-0 */
322 TBSShift = 0,
323 };
324
325 /* BootROM/EEPROM/MII Management Register */
326 #define MASK_MIIR_MII_READ 0x00000000
327 #define MASK_MIIR_MII_WRITE 0x00000008
328 #define MASK_MIIR_MII_MDO 0x00000004
329 #define MASK_MIIR_MII_MDI 0x00000002
330 #define MASK_MIIR_MII_MDC 0x00000001
331
332 /* ST+OP+PHYAD+REGAD+TA */
333 #define OP_READ 0x6000 /* ST:01+OP:10+PHYAD+REGAD+TA:Z0 */
334 #define OP_WRITE 0x5002 /* ST:01+OP:01+PHYAD+REGAD+TA:10 */
335
336 /* ------------------------------------------------------------------------- */
337 /* Constants for Myson PHY */
338 /* ------------------------------------------------------------------------- */
339 #define MysonPHYID 0xd0000302
340 /* 89-7-27 add, (begin) */
341 #define MysonPHYID0 0x0302
342 #define StatusRegister 18
343 #define SPEED100 0x0400 // bit10
344 #define FULLMODE 0x0800 // bit11
345 /* 89-7-27 add, (end) */
346
347 /* ------------------------------------------------------------------------- */
348 /* Constants for Seeq 80225 PHY */
349 /* ------------------------------------------------------------------------- */
350 #define SeeqPHYID0 0x0016
351
352 #define MIIRegister18 18
353 #define SPD_DET_100 0x80
354 #define DPLX_DET_FULL 0x40
355
356 /* ------------------------------------------------------------------------- */
357 /* Constants for Ahdoc 101 PHY */
358 /* ------------------------------------------------------------------------- */
359 #define AhdocPHYID0 0x0022
360
361 #define DiagnosticReg 18
362 #define DPLX_FULL 0x0800
363 #define Speed_100 0x0400
364
365 /* 89/6/13 add, */
366 /* -------------------------------------------------------------------------- */
367 /* Constants */
368 /* -------------------------------------------------------------------------- */
369 #define MarvellPHYID0 0x0141
370 #define LevelOnePHYID0 0x0013
371
372 #define MII1000BaseTControlReg 9
373 #define MII1000BaseTStatusReg 10
374 #define SpecificReg 17
375
376 /* for 1000BaseT Control Register */
377 #define PHYAbletoPerform1000FullDuplex 0x0200
378 #define PHYAbletoPerform1000HalfDuplex 0x0100
379 #define PHY1000AbilityMask 0x300
380
381 // for phy specific status register, marvell phy.
382 #define SpeedMask 0x0c000
383 #define Speed_1000M 0x08000
384 #define Speed_100M 0x4000
385 #define Speed_10M 0
386 #define Full_Duplex 0x2000
387
388 // 89/12/29 add, for phy specific status register, levelone phy, (begin)
389 #define LXT1000_100M 0x08000
390 #define LXT1000_1000M 0x0c000
391 #define LXT1000_Full 0x200
392 // 89/12/29 add, for phy specific status register, levelone phy, (end)
393
394 /* for 3-in-1 case, BMCRSR register */
395 #define LinkIsUp2 0x00040000
396
397 /* for PHY */
398 #define LinkIsUp 0x0004
399
400
401 struct netdev_private {
402 /* Descriptor rings first for alignment. */
403 struct fealnx_desc *rx_ring;
404 struct fealnx_desc *tx_ring;
405
406 dma_addr_t rx_ring_dma;
407 dma_addr_t tx_ring_dma;
408
409 spinlock_t lock;
410
411 struct net_device_stats stats;
412
413 /* Media monitoring timer. */
414 struct timer_list timer;
415
416 /* Reset timer */
417 struct timer_list reset_timer;
418 int reset_timer_armed;
419 unsigned long crvalue_sv;
420 unsigned long imrvalue_sv;
421
422 /* Frequently used values: keep some adjacent for cache effect. */
423 int flags;
424 struct pci_dev *pci_dev;
425 unsigned long crvalue;
426 unsigned long bcrvalue;
427 unsigned long imrvalue;
428 struct fealnx_desc *cur_rx;
429 struct fealnx_desc *lack_rxbuf;
430 int really_rx_count;
431 struct fealnx_desc *cur_tx;
432 struct fealnx_desc *cur_tx_copy;
433 int really_tx_count;
434 int free_tx_count;
435 unsigned int rx_buf_sz; /* Based on MTU+slack. */
436
437 /* These values are keep track of the transceiver/media in use. */
438 unsigned int linkok;
439 unsigned int line_speed;
440 unsigned int duplexmode;
441 unsigned int default_port:4; /* Last dev->if_port value. */
442 unsigned int PHYType;
443
444 /* MII transceiver section. */
445 int mii_cnt; /* MII device addresses. */
446 unsigned char phys[2]; /* MII device addresses. */
447 struct mii_if_info mii;
448 };
449
450
451 static int mdio_read(struct net_device *dev, int phy_id, int location);
452 static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
453 static int netdev_open(struct net_device *dev);
454 static void getlinktype(struct net_device *dev);
455 static void getlinkstatus(struct net_device *dev);
456 static void netdev_timer(unsigned long data);
457 static void reset_timer(unsigned long data);
458 static void tx_timeout(struct net_device *dev);
459 static void init_ring(struct net_device *dev);
460 static int start_tx(struct sk_buff *skb, struct net_device *dev);
461 static irqreturn_t intr_handler(int irq, void *dev_instance, struct pt_regs *regs);
462 static int netdev_rx(struct net_device *dev);
463 static void set_rx_mode(struct net_device *dev);
464 static void __set_rx_mode(struct net_device *dev);
465 static struct net_device_stats *get_stats(struct net_device *dev);
466 static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
467 static struct ethtool_ops netdev_ethtool_ops;
468 static int netdev_close(struct net_device *dev);
469 static void reset_rx_descriptors(struct net_device *dev);
470 static void reset_tx_descriptors(struct net_device *dev);
471
stop_nic_rx(long ioaddr,long crvalue)472 static void stop_nic_rx(long ioaddr, long crvalue)
473 {
474 int delay = 0x1000;
475 writel(crvalue & ~(CR_W_RXEN), ioaddr + TCRRCR);
476 while (--delay) {
477 if ( (readl(ioaddr + TCRRCR) & CR_R_RXSTOP) == CR_R_RXSTOP)
478 break;
479 }
480 }
481
482
stop_nic_rxtx(long ioaddr,long crvalue)483 static void stop_nic_rxtx(long ioaddr, long crvalue)
484 {
485 int delay = 0x1000;
486 writel(crvalue & ~(CR_W_RXEN+CR_W_TXEN), ioaddr + TCRRCR);
487 while (--delay) {
488 if ( (readl(ioaddr + TCRRCR) & (CR_R_RXSTOP+CR_R_TXSTOP))
489 == (CR_R_RXSTOP+CR_R_TXSTOP) )
490 break;
491 }
492 }
493
494
fealnx_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)495 static int __devinit fealnx_init_one(struct pci_dev *pdev,
496 const struct pci_device_id *ent)
497 {
498 struct netdev_private *np;
499 int i, option, err, irq;
500 static int card_idx = -1;
501 char boardname[12];
502 long ioaddr;
503 unsigned int chip_id = ent->driver_data;
504 struct net_device *dev;
505 void *ring_space;
506 dma_addr_t ring_dma;
507
508 /* when built into the kernel, we only print version if device is found */
509 #ifndef MODULE
510 static int printed_version;
511 if (!printed_version++)
512 printk(version);
513 #endif
514
515 card_idx++;
516 sprintf(boardname, "fealnx%d", card_idx);
517
518 option = card_idx < MAX_UNITS ? options[card_idx] : 0;
519
520 i = pci_enable_device(pdev);
521 if (i) return i;
522 pci_set_master(pdev);
523
524 #ifdef USE_IO_OPS
525 ioaddr = pci_resource_len(pdev, 0);
526 #else
527 ioaddr = pci_resource_len(pdev, 1);
528 #endif
529 if (ioaddr < MIN_REGION_SIZE) {
530 printk(KERN_ERR "%s: region size %ld too small, aborting\n",
531 boardname, ioaddr);
532 return -ENODEV;
533 }
534
535 i = pci_request_regions(pdev, boardname);
536 if (i) return i;
537
538 irq = pdev->irq;
539
540 #ifdef USE_IO_OPS
541 ioaddr = pci_resource_start(pdev, 0);
542 #else
543 ioaddr = (long) ioremap(pci_resource_start(pdev, 1),
544 pci_resource_len(pdev, 1));
545 if (!ioaddr) {
546 err = -ENOMEM;
547 goto err_out_res;
548 }
549 #endif
550
551 dev = alloc_etherdev(sizeof(struct netdev_private));
552 if (!dev) {
553 err = -ENOMEM;
554 goto err_out_unmap;
555 }
556 SET_MODULE_OWNER(dev);
557
558 /* read ethernet id */
559 for (i = 0; i < 6; ++i)
560 dev->dev_addr[i] = readb(ioaddr + PAR0 + i);
561
562 /* Reset the chip to erase previous misconfiguration. */
563 writel(0x00000001, ioaddr + BCR);
564
565 dev->base_addr = ioaddr;
566 dev->irq = irq;
567
568 /* Make certain the descriptor lists are aligned. */
569 np = dev->priv;
570 spin_lock_init(&np->lock);
571 np->pci_dev = pdev;
572 np->flags = skel_netdrv_tbl[chip_id].flags;
573 pci_set_drvdata(pdev, dev);
574 np->mii.dev = dev;
575 np->mii.mdio_read = mdio_read;
576 np->mii.mdio_write = mdio_write;
577 np->mii.phy_id_mask = 0x1f;
578 np->mii.reg_num_mask = 0x1f;
579
580 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
581 if (!ring_space) {
582 err = -ENOMEM;
583 goto err_out_free_dev;
584 }
585 np->rx_ring = (struct fealnx_desc *)ring_space;
586 np->rx_ring_dma = ring_dma;
587
588 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
589 if (!ring_space) {
590 err = -ENOMEM;
591 goto err_out_free_rx;
592 }
593 np->tx_ring = (struct fealnx_desc *)ring_space;
594 np->tx_ring_dma = ring_dma;
595
596 /* find the connected MII xcvrs */
597 if (np->flags == HAS_MII_XCVR) {
598 int phy, phy_idx = 0;
599
600 for (phy = 1; phy < 32 && phy_idx < 4; phy++) {
601 int mii_status = mdio_read(dev, phy, 1);
602
603 if (mii_status != 0xffff && mii_status != 0x0000) {
604 np->phys[phy_idx++] = phy;
605 printk(KERN_INFO
606 "%s: MII PHY found at address %d, status "
607 "0x%4.4x.\n", dev->name, phy, mii_status);
608 /* get phy type */
609 {
610 unsigned int data;
611
612 data = mdio_read(dev, np->phys[0], 2);
613 if (data == SeeqPHYID0)
614 np->PHYType = SeeqPHY;
615 else if (data == AhdocPHYID0)
616 np->PHYType = AhdocPHY;
617 else if (data == MarvellPHYID0)
618 np->PHYType = MarvellPHY;
619 else if (data == MysonPHYID0)
620 np->PHYType = Myson981;
621 else if (data == LevelOnePHYID0)
622 np->PHYType = LevelOnePHY;
623 else
624 np->PHYType = OtherPHY;
625 }
626 }
627 }
628
629 np->mii_cnt = phy_idx;
630 if (phy_idx == 0) {
631 printk(KERN_WARNING "%s: MII PHY not found -- this device may "
632 "not operate correctly.\n", dev->name);
633 }
634 } else {
635 np->phys[0] = 32;
636 /* 89/6/23 add, (begin) */
637 /* get phy type */
638 if (readl(ioaddr + PHYIDENTIFIER) == MysonPHYID)
639 np->PHYType = MysonPHY;
640 else
641 np->PHYType = OtherPHY;
642 }
643 np->mii.phy_id = np->phys[0];
644
645 if (dev->mem_start)
646 option = dev->mem_start;
647
648 /* The lower four bits are the media type. */
649 if (option > 0) {
650 if (option & 0x200)
651 np->mii.full_duplex = 1;
652 np->default_port = option & 15;
653 }
654
655 if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0)
656 np->mii.full_duplex = full_duplex[card_idx];
657
658 if (np->mii.full_duplex) {
659 printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);
660 /* 89/6/13 add, (begin) */
661 // if (np->PHYType==MarvellPHY)
662 if ((np->PHYType == MarvellPHY) || (np->PHYType == LevelOnePHY)) {
663 unsigned int data;
664
665 data = mdio_read(dev, np->phys[0], 9);
666 data = (data & 0xfcff) | 0x0200;
667 mdio_write(dev, np->phys[0], 9, data);
668 }
669 /* 89/6/13 add, (end) */
670 if (np->flags == HAS_MII_XCVR)
671 mdio_write(dev, np->phys[0], MII_ADVERTISE, ADVERTISE_FULL);
672 else
673 writel(ADVERTISE_FULL, ioaddr + ANARANLPAR);
674 np->mii.force_media = 1;
675 }
676
677 /* The chip-specific entries in the device structure. */
678 dev->open = &netdev_open;
679 dev->hard_start_xmit = &start_tx;
680 dev->stop = &netdev_close;
681 dev->get_stats = &get_stats;
682 dev->set_multicast_list = &set_rx_mode;
683 dev->do_ioctl = &mii_ioctl;
684 dev->ethtool_ops = &netdev_ethtool_ops;
685 dev->tx_timeout = &tx_timeout;
686 dev->watchdog_timeo = TX_TIMEOUT;
687
688 err = register_netdev(dev);
689 if (err)
690 goto err_out_free_tx;
691
692 printk(KERN_INFO "%s: %s at 0x%lx, ",
693 dev->name, skel_netdrv_tbl[chip_id].chip_name, ioaddr);
694 for (i = 0; i < 5; i++)
695 printk("%2.2x:", dev->dev_addr[i]);
696 printk("%2.2x, IRQ %d.\n", dev->dev_addr[i], irq);
697
698 return 0;
699
700 err_out_free_tx:
701 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
702 err_out_free_rx:
703 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
704 err_out_free_dev:
705 kfree(dev);
706 err_out_unmap:
707 #ifndef USE_IO_OPS
708 iounmap((void *)ioaddr);
709 err_out_res:
710 #endif
711 pci_release_regions(pdev);
712 return err;
713 }
714
715
fealnx_remove_one(struct pci_dev * pdev)716 static void __devexit fealnx_remove_one(struct pci_dev *pdev)
717 {
718 struct net_device *dev = pci_get_drvdata(pdev);
719
720 if (dev) {
721 struct netdev_private *np = dev->priv;
722
723 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring,
724 np->tx_ring_dma);
725 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring,
726 np->rx_ring_dma);
727 unregister_netdev(dev);
728 #ifndef USE_IO_OPS
729 iounmap((void *)dev->base_addr);
730 #endif
731 kfree(dev);
732 pci_release_regions(pdev);
733 pci_set_drvdata(pdev, NULL);
734 } else
735 printk(KERN_ERR "fealnx: remove for unknown device\n");
736 }
737
738
m80x_send_cmd_to_phy(long miiport,int opcode,int phyad,int regad)739 static ulong m80x_send_cmd_to_phy(long miiport, int opcode, int phyad, int regad)
740 {
741 ulong miir;
742 int i;
743 unsigned int mask, data;
744
745 /* enable MII output */
746 miir = (ulong) readl(miiport);
747 miir &= 0xfffffff0;
748
749 miir |= MASK_MIIR_MII_WRITE + MASK_MIIR_MII_MDO;
750
751 /* send 32 1's preamble */
752 for (i = 0; i < 32; i++) {
753 /* low MDC; MDO is already high (miir) */
754 miir &= ~MASK_MIIR_MII_MDC;
755 writel(miir, miiport);
756
757 /* high MDC */
758 miir |= MASK_MIIR_MII_MDC;
759 writel(miir, miiport);
760 }
761
762 /* calculate ST+OP+PHYAD+REGAD+TA */
763 data = opcode | (phyad << 7) | (regad << 2);
764
765 /* sent out */
766 mask = 0x8000;
767 while (mask) {
768 /* low MDC, prepare MDO */
769 miir &= ~(MASK_MIIR_MII_MDC + MASK_MIIR_MII_MDO);
770 if (mask & data)
771 miir |= MASK_MIIR_MII_MDO;
772
773 writel(miir, miiport);
774 /* high MDC */
775 miir |= MASK_MIIR_MII_MDC;
776 writel(miir, miiport);
777 udelay(30);
778
779 /* next */
780 mask >>= 1;
781 if (mask == 0x2 && opcode == OP_READ)
782 miir &= ~MASK_MIIR_MII_WRITE;
783 }
784 return miir;
785 }
786
787
mdio_read(struct net_device * dev,int phyad,int regad)788 static int mdio_read(struct net_device *dev, int phyad, int regad)
789 {
790 long miiport = dev->base_addr + MANAGEMENT;
791 ulong miir;
792 unsigned int mask, data;
793
794 miir = m80x_send_cmd_to_phy(miiport, OP_READ, phyad, regad);
795
796 /* read data */
797 mask = 0x8000;
798 data = 0;
799 while (mask) {
800 /* low MDC */
801 miir &= ~MASK_MIIR_MII_MDC;
802 writel(miir, miiport);
803
804 /* read MDI */
805 miir = readl(miiport);
806 if (miir & MASK_MIIR_MII_MDI)
807 data |= mask;
808
809 /* high MDC, and wait */
810 miir |= MASK_MIIR_MII_MDC;
811 writel(miir, miiport);
812 udelay(30);
813
814 /* next */
815 mask >>= 1;
816 }
817
818 /* low MDC */
819 miir &= ~MASK_MIIR_MII_MDC;
820 writel(miir, miiport);
821
822 return data & 0xffff;
823 }
824
825
mdio_write(struct net_device * dev,int phyad,int regad,int data)826 static void mdio_write(struct net_device *dev, int phyad, int regad, int data)
827 {
828 long miiport = dev->base_addr + MANAGEMENT;
829 ulong miir;
830 unsigned int mask;
831
832 miir = m80x_send_cmd_to_phy(miiport, OP_WRITE, phyad, regad);
833
834 /* write data */
835 mask = 0x8000;
836 while (mask) {
837 /* low MDC, prepare MDO */
838 miir &= ~(MASK_MIIR_MII_MDC + MASK_MIIR_MII_MDO);
839 if (mask & data)
840 miir |= MASK_MIIR_MII_MDO;
841 writel(miir, miiport);
842
843 /* high MDC */
844 miir |= MASK_MIIR_MII_MDC;
845 writel(miir, miiport);
846
847 /* next */
848 mask >>= 1;
849 }
850
851 /* low MDC */
852 miir &= ~MASK_MIIR_MII_MDC;
853 writel(miir, miiport);
854 }
855
856
netdev_open(struct net_device * dev)857 static int netdev_open(struct net_device *dev)
858 {
859 struct netdev_private *np = dev->priv;
860 long ioaddr = dev->base_addr;
861
862 writel(0x00000001, ioaddr + BCR); /* Reset */
863
864 if (request_irq(dev->irq, &intr_handler, SA_SHIRQ, dev->name, dev))
865 return -EAGAIN;
866
867 init_ring(dev);
868
869 writel(np->rx_ring_dma, ioaddr + RXLBA);
870 writel(np->tx_ring_dma, ioaddr + TXLBA);
871
872 /* Initialize other registers. */
873 /* Configure the PCI bus bursts and FIFO thresholds.
874 486: Set 8 longword burst.
875 586: no burst limit.
876 Burst length 5:3
877 0 0 0 1
878 0 0 1 4
879 0 1 0 8
880 0 1 1 16
881 1 0 0 32
882 1 0 1 64
883 1 1 0 128
884 1 1 1 256
885 Wait the specified 50 PCI cycles after a reset by initializing
886 Tx and Rx queues and the address filter list.
887 FIXME (Ueimor): optimistic for alpha + posted writes ? */
888 #if defined(__powerpc__) || defined(__sparc__)
889 // 89/9/1 modify,
890 // np->bcrvalue=0x04 | 0x0x38; /* big-endian, 256 burst length */
891 np->bcrvalue = 0x04 | 0x10; /* big-endian, tx 8 burst length */
892 np->crvalue = 0xe00; /* rx 128 burst length */
893 #elif defined(__alpha__) || defined(__x86_64__)
894 // 89/9/1 modify,
895 // np->bcrvalue=0x38; /* little-endian, 256 burst length */
896 np->bcrvalue = 0x10; /* little-endian, 8 burst length */
897 np->crvalue = 0xe00; /* rx 128 burst length */
898 #elif defined(__i386__)
899 #if defined(MODULE)
900 // 89/9/1 modify,
901 // np->bcrvalue=0x38; /* little-endian, 256 burst length */
902 np->bcrvalue = 0x10; /* little-endian, 8 burst length */
903 np->crvalue = 0xe00; /* rx 128 burst length */
904 #else
905 /* When not a module we can work around broken '486 PCI boards. */
906 #define x86 boot_cpu_data.x86
907 // 89/9/1 modify,
908 // np->bcrvalue=(x86 <= 4 ? 0x10 : 0x38);
909 np->bcrvalue = 0x10;
910 np->crvalue = (x86 <= 4 ? 0xa00 : 0xe00);
911 if (x86 <= 4)
912 printk(KERN_INFO "%s: This is a 386/486 PCI system, setting burst "
913 "length to %x.\n", dev->name, (x86 <= 4 ? 0x10 : 0x38));
914 #endif
915 #else
916 // 89/9/1 modify,
917 // np->bcrvalue=0x38;
918 np->bcrvalue = 0x10;
919 np->crvalue = 0xe00; /* rx 128 burst length */
920 #warning Processor architecture undefined!
921 #endif
922 // 89/12/29 add,
923 // 90/1/16 modify,
924 // np->imrvalue=FBE|TUNF|CNTOVF|RBU|TI|RI;
925 np->imrvalue = TUNF | CNTOVF | RBU | TI | RI;
926 if (np->pci_dev->device == 0x891) {
927 np->bcrvalue |= 0x200; /* set PROG bit */
928 np->crvalue |= CR_W_ENH; /* set enhanced bit */
929 np->imrvalue |= ETI;
930 }
931 writel(np->bcrvalue, ioaddr + BCR);
932
933 if (dev->if_port == 0)
934 dev->if_port = np->default_port;
935
936 writel(0, ioaddr + RXPDR);
937 // 89/9/1 modify,
938 // np->crvalue = 0x00e40001; /* tx store and forward, tx/rx enable */
939 np->crvalue |= 0x00e40001; /* tx store and forward, tx/rx enable */
940 np->mii.full_duplex = np->mii.force_media;
941 getlinkstatus(dev);
942 if (np->linkok)
943 getlinktype(dev);
944 __set_rx_mode(dev);
945
946 netif_start_queue(dev);
947
948 /* Clear and Enable interrupts by setting the interrupt mask. */
949 writel(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR);
950 writel(np->imrvalue, ioaddr + IMR);
951
952 if (debug)
953 printk(KERN_DEBUG "%s: Done netdev_open().\n", dev->name);
954
955 /* Set the timer to check for link beat. */
956 init_timer(&np->timer);
957 np->timer.expires = RUN_AT(3 * HZ);
958 np->timer.data = (unsigned long) dev;
959 np->timer.function = &netdev_timer;
960
961 /* timer handler */
962 add_timer(&np->timer);
963
964 init_timer(&np->reset_timer);
965 np->reset_timer.data = (unsigned long) dev;
966 np->reset_timer.function = &reset_timer;
967 np->reset_timer_armed = 0;
968
969 return 0;
970 }
971
972
getlinkstatus(struct net_device * dev)973 static void getlinkstatus(struct net_device *dev)
974 /* function: Routine will read MII Status Register to get link status. */
975 /* input : dev... pointer to the adapter block. */
976 /* output : none. */
977 {
978 struct netdev_private *np = dev->priv;
979 unsigned int i, DelayTime = 0x1000;
980
981 np->linkok = 0;
982
983 if (np->PHYType == MysonPHY) {
984 for (i = 0; i < DelayTime; ++i) {
985 if (readl(dev->base_addr + BMCRSR) & LinkIsUp2) {
986 np->linkok = 1;
987 return;
988 }
989 udelay(100);
990 }
991 } else {
992 for (i = 0; i < DelayTime; ++i) {
993 if (mdio_read(dev, np->phys[0], MII_BMSR) & BMSR_LSTATUS) {
994 np->linkok = 1;
995 return;
996 }
997 udelay(100);
998 }
999 }
1000 }
1001
1002
getlinktype(struct net_device * dev)1003 static void getlinktype(struct net_device *dev)
1004 {
1005 struct netdev_private *np = dev->priv;
1006
1007 if (np->PHYType == MysonPHY) { /* 3-in-1 case */
1008 if (readl(dev->base_addr + TCRRCR) & CR_R_FD)
1009 np->duplexmode = 2; /* full duplex */
1010 else
1011 np->duplexmode = 1; /* half duplex */
1012 if (readl(dev->base_addr + TCRRCR) & CR_R_PS10)
1013 np->line_speed = 1; /* 10M */
1014 else
1015 np->line_speed = 2; /* 100M */
1016 } else {
1017 if (np->PHYType == SeeqPHY) { /* this PHY is SEEQ 80225 */
1018 unsigned int data;
1019
1020 data = mdio_read(dev, np->phys[0], MIIRegister18);
1021 if (data & SPD_DET_100)
1022 np->line_speed = 2; /* 100M */
1023 else
1024 np->line_speed = 1; /* 10M */
1025 if (data & DPLX_DET_FULL)
1026 np->duplexmode = 2; /* full duplex mode */
1027 else
1028 np->duplexmode = 1; /* half duplex mode */
1029 } else if (np->PHYType == AhdocPHY) {
1030 unsigned int data;
1031
1032 data = mdio_read(dev, np->phys[0], DiagnosticReg);
1033 if (data & Speed_100)
1034 np->line_speed = 2; /* 100M */
1035 else
1036 np->line_speed = 1; /* 10M */
1037 if (data & DPLX_FULL)
1038 np->duplexmode = 2; /* full duplex mode */
1039 else
1040 np->duplexmode = 1; /* half duplex mode */
1041 }
1042 /* 89/6/13 add, (begin) */
1043 else if (np->PHYType == MarvellPHY) {
1044 unsigned int data;
1045
1046 data = mdio_read(dev, np->phys[0], SpecificReg);
1047 if (data & Full_Duplex)
1048 np->duplexmode = 2; /* full duplex mode */
1049 else
1050 np->duplexmode = 1; /* half duplex mode */
1051 data &= SpeedMask;
1052 if (data == Speed_1000M)
1053 np->line_speed = 3; /* 1000M */
1054 else if (data == Speed_100M)
1055 np->line_speed = 2; /* 100M */
1056 else
1057 np->line_speed = 1; /* 10M */
1058 }
1059 /* 89/6/13 add, (end) */
1060 /* 89/7/27 add, (begin) */
1061 else if (np->PHYType == Myson981) {
1062 unsigned int data;
1063
1064 data = mdio_read(dev, np->phys[0], StatusRegister);
1065
1066 if (data & SPEED100)
1067 np->line_speed = 2;
1068 else
1069 np->line_speed = 1;
1070
1071 if (data & FULLMODE)
1072 np->duplexmode = 2;
1073 else
1074 np->duplexmode = 1;
1075 }
1076 /* 89/7/27 add, (end) */
1077 /* 89/12/29 add */
1078 else if (np->PHYType == LevelOnePHY) {
1079 unsigned int data;
1080
1081 data = mdio_read(dev, np->phys[0], SpecificReg);
1082 if (data & LXT1000_Full)
1083 np->duplexmode = 2; /* full duplex mode */
1084 else
1085 np->duplexmode = 1; /* half duplex mode */
1086 data &= SpeedMask;
1087 if (data == LXT1000_1000M)
1088 np->line_speed = 3; /* 1000M */
1089 else if (data == LXT1000_100M)
1090 np->line_speed = 2; /* 100M */
1091 else
1092 np->line_speed = 1; /* 10M */
1093 }
1094 np->crvalue &= (~CR_W_PS10) & (~CR_W_FD) & (~CR_W_PS1000);
1095 if (np->line_speed == 1)
1096 np->crvalue |= CR_W_PS10;
1097 else if (np->line_speed == 3)
1098 np->crvalue |= CR_W_PS1000;
1099 if (np->duplexmode == 2)
1100 np->crvalue |= CR_W_FD;
1101 }
1102 }
1103
1104
1105 /* Take lock before calling this */
allocate_rx_buffers(struct net_device * dev)1106 static void allocate_rx_buffers(struct net_device *dev)
1107 {
1108 struct netdev_private *np = dev->priv;
1109
1110 /* allocate skb for rx buffers */
1111 while (np->really_rx_count != RX_RING_SIZE) {
1112 struct sk_buff *skb;
1113
1114 skb = dev_alloc_skb(np->rx_buf_sz);
1115 if (skb == NULL)
1116 break; /* Better luck next round. */
1117
1118 while (np->lack_rxbuf->skbuff)
1119 np->lack_rxbuf = np->lack_rxbuf->next_desc_logical;
1120
1121 skb->dev = dev; /* Mark as being used by this device. */
1122 np->lack_rxbuf->skbuff = skb;
1123 np->lack_rxbuf->buffer = pci_map_single(np->pci_dev, skb->tail,
1124 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1125 np->lack_rxbuf->status = RXOWN;
1126 ++np->really_rx_count;
1127 }
1128 }
1129
1130
netdev_timer(unsigned long data)1131 static void netdev_timer(unsigned long data)
1132 {
1133 struct net_device *dev = (struct net_device *) data;
1134 struct netdev_private *np = dev->priv;
1135 long ioaddr = dev->base_addr;
1136 int old_crvalue = np->crvalue;
1137 unsigned int old_linkok = np->linkok;
1138 unsigned long flags;
1139
1140 if (debug)
1141 printk(KERN_DEBUG "%s: Media selection timer tick, status %8.8x "
1142 "config %8.8x.\n", dev->name, readl(ioaddr + ISR),
1143 readl(ioaddr + TCRRCR));
1144
1145 spin_lock_irqsave(&np->lock, flags);
1146
1147 if (np->flags == HAS_MII_XCVR) {
1148 getlinkstatus(dev);
1149 if ((old_linkok == 0) && (np->linkok == 1)) { /* we need to detect the media type again */
1150 getlinktype(dev);
1151 if (np->crvalue != old_crvalue) {
1152 stop_nic_rxtx(ioaddr, np->crvalue);
1153 writel(np->crvalue, ioaddr + TCRRCR);
1154 }
1155 }
1156 }
1157
1158 allocate_rx_buffers(dev);
1159
1160 spin_unlock_irqrestore(&np->lock, flags);
1161
1162 np->timer.expires = RUN_AT(10 * HZ);
1163 add_timer(&np->timer);
1164 }
1165
1166
1167 /* Take lock before calling */
1168 /* Reset chip and disable rx, tx and interrupts */
reset_and_disable_rxtx(struct net_device * dev)1169 static void reset_and_disable_rxtx(struct net_device *dev)
1170 {
1171 long ioaddr = dev->base_addr;
1172 int delay=51;
1173
1174 /* Reset the chip's Tx and Rx processes. */
1175 stop_nic_rxtx(ioaddr, 0);
1176
1177 /* Disable interrupts by clearing the interrupt mask. */
1178 writel(0, ioaddr + IMR);
1179
1180 /* Reset the chip to erase previous misconfiguration. */
1181 writel(0x00000001, ioaddr + BCR);
1182
1183 /* Ueimor: wait for 50 PCI cycles (and flush posted writes btw).
1184 We surely wait too long (address+data phase). Who cares? */
1185 while (--delay) {
1186 readl(ioaddr + BCR);
1187 rmb();
1188 }
1189 }
1190
1191
1192 /* Take lock before calling */
1193 /* Restore chip after reset */
enable_rxtx(struct net_device * dev)1194 static void enable_rxtx(struct net_device *dev)
1195 {
1196 struct netdev_private *np = dev->priv;
1197 long ioaddr = dev->base_addr;
1198
1199 reset_rx_descriptors(dev);
1200
1201 writel(np->tx_ring_dma + ((char*)np->cur_tx - (char*)np->tx_ring),
1202 ioaddr + TXLBA);
1203 writel(np->rx_ring_dma + ((char*)np->cur_rx - (char*)np->rx_ring),
1204 ioaddr + RXLBA);
1205
1206 writel(np->bcrvalue, ioaddr + BCR);
1207
1208 writel(0, ioaddr + RXPDR);
1209 __set_rx_mode(dev); /* changes np->crvalue, writes it into TCRRCR */
1210
1211 /* Clear and Enable interrupts by setting the interrupt mask. */
1212 writel(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR);
1213 writel(np->imrvalue, ioaddr + IMR);
1214
1215 writel(0, ioaddr + TXPDR);
1216 }
1217
1218
reset_timer(unsigned long data)1219 static void reset_timer(unsigned long data)
1220 {
1221 struct net_device *dev = (struct net_device *) data;
1222 struct netdev_private *np = dev->priv;
1223 unsigned long flags;
1224
1225 printk(KERN_WARNING "%s: resetting tx and rx machinery\n", dev->name);
1226
1227 spin_lock_irqsave(&np->lock, flags);
1228 np->crvalue = np->crvalue_sv;
1229 np->imrvalue = np->imrvalue_sv;
1230
1231 reset_and_disable_rxtx(dev);
1232 /* works for me without this:
1233 reset_tx_descriptors(dev); */
1234 enable_rxtx(dev);
1235 netif_start_queue(dev); /* FIXME: or netif_wake_queue(dev); ? */
1236
1237 np->reset_timer_armed = 0;
1238
1239 spin_unlock_irqrestore(&np->lock, flags);
1240 }
1241
1242
tx_timeout(struct net_device * dev)1243 static void tx_timeout(struct net_device *dev)
1244 {
1245 struct netdev_private *np = dev->priv;
1246 long ioaddr = dev->base_addr;
1247 unsigned long flags;
1248 int i;
1249
1250 printk(KERN_WARNING "%s: Transmit timed out, status %8.8x,"
1251 " resetting...\n", dev->name, readl(ioaddr + ISR));
1252
1253 {
1254 printk(KERN_DEBUG " Rx ring %p: ", np->rx_ring);
1255 for (i = 0; i < RX_RING_SIZE; i++)
1256 printk(" %8.8x", (unsigned int) np->rx_ring[i].status);
1257 printk("\n" KERN_DEBUG " Tx ring %p: ", np->tx_ring);
1258 for (i = 0; i < TX_RING_SIZE; i++)
1259 printk(" %4.4x", np->tx_ring[i].status);
1260 printk("\n");
1261 }
1262
1263 spin_lock_irqsave(&np->lock, flags);
1264
1265 reset_and_disable_rxtx(dev);
1266 reset_tx_descriptors(dev);
1267 enable_rxtx(dev);
1268
1269 spin_unlock_irqrestore(&np->lock, flags);
1270
1271 dev->trans_start = jiffies;
1272 np->stats.tx_errors++;
1273 netif_wake_queue(dev); /* or .._start_.. ?? */
1274 }
1275
1276
1277 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
init_ring(struct net_device * dev)1278 static void init_ring(struct net_device *dev)
1279 {
1280 struct netdev_private *np = dev->priv;
1281 int i;
1282
1283 /* initialize rx variables */
1284 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
1285 np->cur_rx = &np->rx_ring[0];
1286 np->lack_rxbuf = np->rx_ring;
1287 np->really_rx_count = 0;
1288
1289 /* initial rx descriptors. */
1290 for (i = 0; i < RX_RING_SIZE; i++) {
1291 np->rx_ring[i].status = 0;
1292 np->rx_ring[i].control = np->rx_buf_sz << RBSShift;
1293 np->rx_ring[i].next_desc = np->rx_ring_dma +
1294 (i + 1)*sizeof(struct fealnx_desc);
1295 np->rx_ring[i].next_desc_logical = &np->rx_ring[i + 1];
1296 np->rx_ring[i].skbuff = NULL;
1297 }
1298
1299 /* for the last rx descriptor */
1300 np->rx_ring[i - 1].next_desc = np->rx_ring_dma;
1301 np->rx_ring[i - 1].next_desc_logical = np->rx_ring;
1302
1303 /* allocate skb for rx buffers */
1304 for (i = 0; i < RX_RING_SIZE; i++) {
1305 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz);
1306
1307 if (skb == NULL) {
1308 np->lack_rxbuf = &np->rx_ring[i];
1309 break;
1310 }
1311
1312 ++np->really_rx_count;
1313 np->rx_ring[i].skbuff = skb;
1314 skb->dev = dev; /* Mark as being used by this device. */
1315 np->rx_ring[i].buffer = pci_map_single(np->pci_dev, skb->tail,
1316 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1317 np->rx_ring[i].status = RXOWN;
1318 np->rx_ring[i].control |= RXIC;
1319 }
1320
1321 /* initialize tx variables */
1322 np->cur_tx = &np->tx_ring[0];
1323 np->cur_tx_copy = &np->tx_ring[0];
1324 np->really_tx_count = 0;
1325 np->free_tx_count = TX_RING_SIZE;
1326
1327 for (i = 0; i < TX_RING_SIZE; i++) {
1328 np->tx_ring[i].status = 0;
1329 /* do we need np->tx_ring[i].control = XXX; ?? */
1330 np->tx_ring[i].next_desc = np->tx_ring_dma +
1331 (i + 1)*sizeof(struct fealnx_desc);
1332 np->tx_ring[i].next_desc_logical = &np->tx_ring[i + 1];
1333 np->tx_ring[i].skbuff = NULL;
1334 }
1335
1336 /* for the last tx descriptor */
1337 np->tx_ring[i - 1].next_desc = np->tx_ring_dma;
1338 np->tx_ring[i - 1].next_desc_logical = &np->tx_ring[0];
1339 }
1340
1341
start_tx(struct sk_buff * skb,struct net_device * dev)1342 static int start_tx(struct sk_buff *skb, struct net_device *dev)
1343 {
1344 struct netdev_private *np = dev->priv;
1345
1346 np->cur_tx_copy->skbuff = skb;
1347
1348 #define one_buffer
1349 #define BPT 1022
1350 #if defined(one_buffer)
1351 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1352 skb->len, PCI_DMA_TODEVICE);
1353 np->cur_tx_copy->control = TXIC | TXLD | TXFD | CRCEnable | PADEnable;
1354 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1355 np->cur_tx_copy->control |= (skb->len << TBSShift); /* buffer size */
1356 // 89/12/29 add,
1357 if (np->pci_dev->device == 0x891)
1358 np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1359 np->cur_tx_copy->status = TXOWN;
1360 np->cur_tx_copy = np->cur_tx_copy->next_desc_logical;
1361 --np->free_tx_count;
1362 #elif defined(two_buffer)
1363 if (skb->len > BPT) {
1364 struct fealnx_desc *next;
1365
1366 /* for the first descriptor */
1367 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1368 BPT, PCI_DMA_TODEVICE);
1369 np->cur_tx_copy->control = TXIC | TXFD | CRCEnable | PADEnable;
1370 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1371 np->cur_tx_copy->control |= (BPT << TBSShift); /* buffer size */
1372
1373 /* for the last descriptor */
1374 next = np->cur_tx_copy->next_desc_logical;
1375 next->skbuff = skb;
1376 next->control = TXIC | TXLD | CRCEnable | PADEnable;
1377 next->control |= (skb->len << PKTSShift); /* pkt size */
1378 next->control |= ((skb->len - BPT) << TBSShift); /* buf size */
1379 // 89/12/29 add,
1380 if (np->pci_dev->device == 0x891)
1381 np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1382 next->buffer = pci_map_single(ep->pci_dev, skb->data + BPT,
1383 skb->len - BPT, PCI_DMA_TODEVICE);
1384
1385 next->status = TXOWN;
1386 np->cur_tx_copy->status = TXOWN;
1387
1388 np->cur_tx_copy = next->next_desc_logical;
1389 np->free_tx_count -= 2;
1390 } else {
1391 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1392 skb->len, PCI_DMA_TODEVICE);
1393 np->cur_tx_copy->control = TXIC | TXLD | TXFD | CRCEnable | PADEnable;
1394 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1395 np->cur_tx_copy->control |= (skb->len << TBSShift); /* buffer size */
1396 // 89/12/29 add,
1397 if (np->pci_dev->device == 0x891)
1398 np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1399 np->cur_tx_copy->status = TXOWN;
1400 np->cur_tx_copy = np->cur_tx_copy->next_desc_logical;
1401 --np->free_tx_count;
1402 }
1403 #endif
1404
1405 if (np->free_tx_count < 2)
1406 netif_stop_queue(dev);
1407 ++np->really_tx_count;
1408 writel(0, dev->base_addr + TXPDR);
1409 dev->trans_start = jiffies;
1410
1411 return 0;
1412 }
1413
1414
1415 /* Take lock before calling */
1416 /* Chip probably hosed tx ring. Clean up. */
reset_tx_descriptors(struct net_device * dev)1417 static void reset_tx_descriptors(struct net_device *dev)
1418 {
1419 struct netdev_private *np = dev->priv;
1420 struct fealnx_desc *cur;
1421 int i;
1422
1423 /* initialize tx variables */
1424 np->cur_tx = &np->tx_ring[0];
1425 np->cur_tx_copy = &np->tx_ring[0];
1426 np->really_tx_count = 0;
1427 np->free_tx_count = TX_RING_SIZE;
1428
1429 for (i = 0; i < TX_RING_SIZE; i++) {
1430 cur = &np->tx_ring[i];
1431 if (cur->skbuff) {
1432 pci_unmap_single(np->pci_dev, cur->buffer,
1433 cur->skbuff->len, PCI_DMA_TODEVICE);
1434 dev_kfree_skb(cur->skbuff);
1435 /* or dev_kfree_skb_irq(cur->skbuff); ? */
1436 cur->skbuff = NULL;
1437 }
1438 cur->status = 0;
1439 cur->control = 0; /* needed? */
1440 /* probably not needed. We do it for purely paranoid reasons */
1441 cur->next_desc = np->tx_ring_dma +
1442 (i + 1)*sizeof(struct fealnx_desc);
1443 cur->next_desc_logical = &np->tx_ring[i + 1];
1444 }
1445 /* for the last tx descriptor */
1446 np->tx_ring[TX_RING_SIZE - 1].next_desc = np->tx_ring_dma;
1447 np->tx_ring[TX_RING_SIZE - 1].next_desc_logical = &np->tx_ring[0];
1448 }
1449
1450
1451 /* Take lock and stop rx before calling this */
reset_rx_descriptors(struct net_device * dev)1452 static void reset_rx_descriptors(struct net_device *dev)
1453 {
1454 struct netdev_private *np = dev->priv;
1455 struct fealnx_desc *cur = np->cur_rx;
1456 int i;
1457
1458 allocate_rx_buffers(dev);
1459
1460 for (i = 0; i < RX_RING_SIZE; i++) {
1461 if (cur->skbuff)
1462 cur->status = RXOWN;
1463 cur = cur->next_desc_logical;
1464 }
1465
1466 writel(np->rx_ring_dma + ((char*)np->cur_rx - (char*)np->rx_ring),
1467 dev->base_addr + RXLBA);
1468 }
1469
1470
1471 /* The interrupt handler does all of the Rx thread work and cleans up
1472 after the Tx thread. */
intr_handler(int irq,void * dev_instance,struct pt_regs * rgs)1473 static irqreturn_t intr_handler(int irq, void *dev_instance, struct pt_regs *rgs)
1474 {
1475 struct net_device *dev = (struct net_device *) dev_instance;
1476 struct netdev_private *np = dev->priv;
1477 long ioaddr = dev->base_addr;
1478 long boguscnt = max_interrupt_work;
1479 unsigned int num_tx = 0;
1480 int handled = 0;
1481
1482 spin_lock(&np->lock);
1483
1484 writel(0, ioaddr + IMR);
1485
1486 do {
1487 u32 intr_status = readl(ioaddr + ISR);
1488
1489 /* Acknowledge all of the current interrupt sources ASAP. */
1490 writel(intr_status, ioaddr + ISR);
1491
1492 if (debug)
1493 printk(KERN_DEBUG "%s: Interrupt, status %4.4x.\n", dev->name,
1494 intr_status);
1495
1496 if (!(intr_status & np->imrvalue))
1497 break;
1498
1499 handled = 1;
1500
1501 // 90/1/16 delete,
1502 //
1503 // if (intr_status & FBE)
1504 // { /* fatal error */
1505 // stop_nic_tx(ioaddr, 0);
1506 // stop_nic_rx(ioaddr, 0);
1507 // break;
1508 // };
1509
1510 if (intr_status & TUNF)
1511 writel(0, ioaddr + TXPDR);
1512
1513 if (intr_status & CNTOVF) {
1514 /* missed pkts */
1515 np->stats.rx_missed_errors += readl(ioaddr + TALLY) & 0x7fff;
1516
1517 /* crc error */
1518 np->stats.rx_crc_errors +=
1519 (readl(ioaddr + TALLY) & 0x7fff0000) >> 16;
1520 }
1521
1522 if (intr_status & (RI | RBU)) {
1523 if (intr_status & RI)
1524 netdev_rx(dev);
1525 else {
1526 stop_nic_rx(ioaddr, np->crvalue);
1527 reset_rx_descriptors(dev);
1528 writel(np->crvalue, ioaddr + TCRRCR);
1529 }
1530 }
1531
1532 while (np->really_tx_count) {
1533 long tx_status = np->cur_tx->status;
1534 long tx_control = np->cur_tx->control;
1535
1536 if (!(tx_control & TXLD)) { /* this pkt is combined by two tx descriptors */
1537 struct fealnx_desc *next;
1538
1539 next = np->cur_tx->next_desc_logical;
1540 tx_status = next->status;
1541 tx_control = next->control;
1542 }
1543
1544 if (tx_status & TXOWN)
1545 break;
1546
1547 if (!(np->crvalue & CR_W_ENH)) {
1548 if (tx_status & (CSL | LC | EC | UDF | HF)) {
1549 np->stats.tx_errors++;
1550 if (tx_status & EC)
1551 np->stats.tx_aborted_errors++;
1552 if (tx_status & CSL)
1553 np->stats.tx_carrier_errors++;
1554 if (tx_status & LC)
1555 np->stats.tx_window_errors++;
1556 if (tx_status & UDF)
1557 np->stats.tx_fifo_errors++;
1558 if ((tx_status & HF) && np->mii.full_duplex == 0)
1559 np->stats.tx_heartbeat_errors++;
1560
1561 } else {
1562 np->stats.tx_bytes +=
1563 ((tx_control & PKTSMask) >> PKTSShift);
1564
1565 np->stats.collisions +=
1566 ((tx_status & NCRMask) >> NCRShift);
1567 np->stats.tx_packets++;
1568 }
1569 } else {
1570 np->stats.tx_bytes +=
1571 ((tx_control & PKTSMask) >> PKTSShift);
1572 np->stats.tx_packets++;
1573 }
1574
1575 /* Free the original skb. */
1576 pci_unmap_single(np->pci_dev, np->cur_tx->buffer,
1577 np->cur_tx->skbuff->len, PCI_DMA_TODEVICE);
1578 dev_kfree_skb_irq(np->cur_tx->skbuff);
1579 np->cur_tx->skbuff = NULL;
1580 --np->really_tx_count;
1581 if (np->cur_tx->control & TXLD) {
1582 np->cur_tx = np->cur_tx->next_desc_logical;
1583 ++np->free_tx_count;
1584 } else {
1585 np->cur_tx = np->cur_tx->next_desc_logical;
1586 np->cur_tx = np->cur_tx->next_desc_logical;
1587 np->free_tx_count += 2;
1588 }
1589 num_tx++;
1590 } /* end of for loop */
1591
1592 if (num_tx && np->free_tx_count >= 2)
1593 netif_wake_queue(dev);
1594
1595 /* read transmit status for enhanced mode only */
1596 if (np->crvalue & CR_W_ENH) {
1597 long data;
1598
1599 data = readl(ioaddr + TSR);
1600 np->stats.tx_errors += (data & 0xff000000) >> 24;
1601 np->stats.tx_aborted_errors += (data & 0xff000000) >> 24;
1602 np->stats.tx_window_errors += (data & 0x00ff0000) >> 16;
1603 np->stats.collisions += (data & 0x0000ffff);
1604 }
1605
1606 if (--boguscnt < 0) {
1607 printk(KERN_WARNING "%s: Too much work at interrupt, "
1608 "status=0x%4.4x.\n", dev->name, intr_status);
1609 if (!np->reset_timer_armed) {
1610 np->reset_timer_armed = 1;
1611 np->reset_timer.expires = RUN_AT(HZ/2);
1612 add_timer(&np->reset_timer);
1613 stop_nic_rxtx(ioaddr, 0);
1614 netif_stop_queue(dev);
1615 /* or netif_tx_disable(dev); ?? */
1616 /* Prevent other paths from enabling tx,rx,intrs */
1617 np->crvalue_sv = np->crvalue;
1618 np->imrvalue_sv = np->imrvalue;
1619 np->crvalue &= ~(CR_W_TXEN | CR_W_RXEN); /* or simply = 0? */
1620 np->imrvalue = 0;
1621 }
1622
1623 break;
1624 }
1625 } while (1);
1626
1627 /* read the tally counters */
1628 /* missed pkts */
1629 np->stats.rx_missed_errors += readl(ioaddr + TALLY) & 0x7fff;
1630
1631 /* crc error */
1632 np->stats.rx_crc_errors += (readl(ioaddr + TALLY) & 0x7fff0000) >> 16;
1633
1634 if (debug)
1635 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1636 dev->name, readl(ioaddr + ISR));
1637
1638 writel(np->imrvalue, ioaddr + IMR);
1639
1640 spin_unlock(&np->lock);
1641
1642 return IRQ_RETVAL(handled);
1643 }
1644
1645
1646 /* This routine is logically part of the interrupt handler, but separated
1647 for clarity and better register allocation. */
netdev_rx(struct net_device * dev)1648 static int netdev_rx(struct net_device *dev)
1649 {
1650 struct netdev_private *np = dev->priv;
1651 long ioaddr = dev->base_addr;
1652
1653 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1654 while (!(np->cur_rx->status & RXOWN) && np->cur_rx->skbuff) {
1655 s32 rx_status = np->cur_rx->status;
1656
1657 if (np->really_rx_count == 0)
1658 break;
1659
1660 if (debug)
1661 printk(KERN_DEBUG " netdev_rx() status was %8.8x.\n", rx_status);
1662
1663 if ((!((rx_status & RXFSD) && (rx_status & RXLSD)))
1664 || (rx_status & ErrorSummary)) {
1665 if (rx_status & ErrorSummary) { /* there was a fatal error */
1666 if (debug)
1667 printk(KERN_DEBUG
1668 "%s: Receive error, Rx status %8.8x.\n",
1669 dev->name, rx_status);
1670
1671 np->stats.rx_errors++; /* end of a packet. */
1672 if (rx_status & (LONG | RUNT))
1673 np->stats.rx_length_errors++;
1674 if (rx_status & RXER)
1675 np->stats.rx_frame_errors++;
1676 if (rx_status & CRC)
1677 np->stats.rx_crc_errors++;
1678 } else {
1679 int need_to_reset = 0;
1680 int desno = 0;
1681
1682 if (rx_status & RXFSD) { /* this pkt is too long, over one rx buffer */
1683 struct fealnx_desc *cur;
1684
1685 /* check this packet is received completely? */
1686 cur = np->cur_rx;
1687 while (desno <= np->really_rx_count) {
1688 ++desno;
1689 if ((!(cur->status & RXOWN))
1690 && (cur->status & RXLSD))
1691 break;
1692 /* goto next rx descriptor */
1693 cur = cur->next_desc_logical;
1694 }
1695 if (desno > np->really_rx_count)
1696 need_to_reset = 1;
1697 } else /* RXLSD did not find, something error */
1698 need_to_reset = 1;
1699
1700 if (need_to_reset == 0) {
1701 int i;
1702
1703 np->stats.rx_length_errors++;
1704
1705 /* free all rx descriptors related this long pkt */
1706 for (i = 0; i < desno; ++i) {
1707 if (!np->cur_rx->skbuff) {
1708 printk(KERN_DEBUG
1709 "%s: I'm scared\n", dev->name);
1710 break;
1711 }
1712 np->cur_rx->status = RXOWN;
1713 np->cur_rx = np->cur_rx->next_desc_logical;
1714 }
1715 continue;
1716 } else { /* rx error, need to reset this chip */
1717 stop_nic_rx(ioaddr, np->crvalue);
1718 reset_rx_descriptors(dev);
1719 writel(np->crvalue, ioaddr + TCRRCR);
1720 }
1721 break; /* exit the while loop */
1722 }
1723 } else { /* this received pkt is ok */
1724
1725 struct sk_buff *skb;
1726 /* Omit the four octet CRC from the length. */
1727 short pkt_len = ((rx_status & FLNGMASK) >> FLNGShift) - 4;
1728
1729 #ifndef final_version
1730 if (debug)
1731 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d"
1732 " status %x.\n", pkt_len, rx_status);
1733 #endif
1734 pci_dma_sync_single(np->pci_dev, np->cur_rx->buffer,
1735 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1736 pci_unmap_single(np->pci_dev, np->cur_rx->buffer,
1737 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1738
1739 /* Check if the packet is long enough to accept without copying
1740 to a minimally-sized skbuff. */
1741 if (pkt_len < rx_copybreak &&
1742 (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1743 skb->dev = dev;
1744 skb_reserve(skb, 2); /* 16 byte align the IP header */
1745 /* Call copy + cksum if available. */
1746
1747 #if ! defined(__alpha__)
1748 eth_copy_and_sum(skb,
1749 np->cur_rx->skbuff->tail, pkt_len, 0);
1750 skb_put(skb, pkt_len);
1751 #else
1752 memcpy(skb_put(skb, pkt_len),
1753 np->cur_rx->skbuff->tail, pkt_len);
1754 #endif
1755 } else {
1756 skb_put(skb = np->cur_rx->skbuff, pkt_len);
1757 np->cur_rx->skbuff = NULL;
1758 --np->really_rx_count;
1759 }
1760 skb->protocol = eth_type_trans(skb, dev);
1761 netif_rx(skb);
1762 dev->last_rx = jiffies;
1763 np->stats.rx_packets++;
1764 np->stats.rx_bytes += pkt_len;
1765 }
1766
1767 np->cur_rx = np->cur_rx->next_desc_logical;
1768 } /* end of while loop */
1769
1770 /* allocate skb for rx buffers */
1771 allocate_rx_buffers(dev);
1772
1773 return 0;
1774 }
1775
1776
get_stats(struct net_device * dev)1777 static struct net_device_stats *get_stats(struct net_device *dev)
1778 {
1779 long ioaddr = dev->base_addr;
1780 struct netdev_private *np = dev->priv;
1781
1782 /* The chip only need report frame silently dropped. */
1783 if (netif_running(dev)) {
1784 np->stats.rx_missed_errors += readl(ioaddr + TALLY) & 0x7fff;
1785 np->stats.rx_crc_errors += (readl(ioaddr + TALLY) & 0x7fff0000) >> 16;
1786 }
1787
1788 return &np->stats;
1789 }
1790
1791
1792 /* for dev->set_multicast_list */
set_rx_mode(struct net_device * dev)1793 static void set_rx_mode(struct net_device *dev)
1794 {
1795 spinlock_t *lp = &((struct netdev_private *)dev->priv)->lock;
1796 unsigned long flags;
1797 spin_lock_irqsave(lp, flags);
1798 __set_rx_mode(dev);
1799 spin_unlock_irqrestore(lp, flags);
1800 }
1801
1802
1803 /* Take lock before calling */
__set_rx_mode(struct net_device * dev)1804 static void __set_rx_mode(struct net_device *dev)
1805 {
1806 struct netdev_private *np = dev->priv;
1807 long ioaddr = dev->base_addr;
1808 u32 mc_filter[2]; /* Multicast hash filter */
1809 u32 rx_mode;
1810
1811 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1812 /* Unconditionally log net taps. */
1813 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
1814 memset(mc_filter, 0xff, sizeof(mc_filter));
1815 rx_mode = CR_W_PROM | CR_W_AB | CR_W_AM;
1816 } else if ((dev->mc_count > multicast_filter_limit)
1817 || (dev->flags & IFF_ALLMULTI)) {
1818 /* Too many to match, or accept all multicasts. */
1819 memset(mc_filter, 0xff, sizeof(mc_filter));
1820 rx_mode = CR_W_AB | CR_W_AM;
1821 } else {
1822 struct dev_mc_list *mclist;
1823 int i;
1824
1825 memset(mc_filter, 0, sizeof(mc_filter));
1826 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1827 i++, mclist = mclist->next) {
1828 unsigned int bit;
1829 bit = (ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26) ^ 0x3F;
1830 mc_filter[bit >> 5] |= (1 << bit);
1831 }
1832 rx_mode = CR_W_AB | CR_W_AM;
1833 }
1834
1835 stop_nic_rxtx(ioaddr, np->crvalue);
1836
1837 writel(mc_filter[0], ioaddr + MAR0);
1838 writel(mc_filter[1], ioaddr + MAR1);
1839 np->crvalue &= ~CR_W_RXMODEMASK;
1840 np->crvalue |= rx_mode;
1841 writel(np->crvalue, ioaddr + TCRRCR);
1842 }
1843
netdev_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)1844 static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1845 {
1846 struct netdev_private *np = dev->priv;
1847
1848 strcpy(info->driver, DRV_NAME);
1849 strcpy(info->version, DRV_VERSION);
1850 strcpy(info->bus_info, pci_name(np->pci_dev));
1851 }
1852
netdev_get_settings(struct net_device * dev,struct ethtool_cmd * cmd)1853 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1854 {
1855 struct netdev_private *np = dev->priv;
1856 int rc;
1857
1858 spin_lock_irq(&np->lock);
1859 rc = mii_ethtool_gset(&np->mii, cmd);
1860 spin_unlock_irq(&np->lock);
1861
1862 return rc;
1863 }
1864
netdev_set_settings(struct net_device * dev,struct ethtool_cmd * cmd)1865 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1866 {
1867 struct netdev_private *np = dev->priv;
1868 int rc;
1869
1870 spin_lock_irq(&np->lock);
1871 rc = mii_ethtool_sset(&np->mii, cmd);
1872 spin_unlock_irq(&np->lock);
1873
1874 return rc;
1875 }
1876
netdev_nway_reset(struct net_device * dev)1877 static int netdev_nway_reset(struct net_device *dev)
1878 {
1879 struct netdev_private *np = dev->priv;
1880 return mii_nway_restart(&np->mii);
1881 }
1882
netdev_get_link(struct net_device * dev)1883 static u32 netdev_get_link(struct net_device *dev)
1884 {
1885 struct netdev_private *np = dev->priv;
1886 return mii_link_ok(&np->mii);
1887 }
1888
netdev_get_msglevel(struct net_device * dev)1889 static u32 netdev_get_msglevel(struct net_device *dev)
1890 {
1891 return debug;
1892 }
1893
netdev_set_msglevel(struct net_device * dev,u32 value)1894 static void netdev_set_msglevel(struct net_device *dev, u32 value)
1895 {
1896 debug = value;
1897 }
1898
1899 static struct ethtool_ops netdev_ethtool_ops = {
1900 .get_drvinfo = netdev_get_drvinfo,
1901 .get_settings = netdev_get_settings,
1902 .set_settings = netdev_set_settings,
1903 .nway_reset = netdev_nway_reset,
1904 .get_link = netdev_get_link,
1905 .get_msglevel = netdev_get_msglevel,
1906 .set_msglevel = netdev_set_msglevel,
1907 .get_sg = ethtool_op_get_sg,
1908 .get_tx_csum = ethtool_op_get_tx_csum,
1909 };
1910
mii_ioctl(struct net_device * dev,struct ifreq * rq,int cmd)1911 static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1912 {
1913 struct netdev_private *np = dev->priv;
1914 struct mii_ioctl_data *data = (struct mii_ioctl_data *) & rq->ifr_data;
1915 int rc;
1916
1917 if (!netif_running(dev))
1918 return -EINVAL;
1919
1920 spin_lock_irq(&np->lock);
1921 rc = generic_mii_ioctl(&np->mii, data, cmd, NULL);
1922 spin_unlock_irq(&np->lock);
1923
1924 return rc;
1925 }
1926
1927
netdev_close(struct net_device * dev)1928 static int netdev_close(struct net_device *dev)
1929 {
1930 long ioaddr = dev->base_addr;
1931 struct netdev_private *np = dev->priv;
1932 int i;
1933
1934 netif_stop_queue(dev);
1935
1936 /* Disable interrupts by clearing the interrupt mask. */
1937 writel(0x0000, ioaddr + IMR);
1938
1939 /* Stop the chip's Tx and Rx processes. */
1940 stop_nic_rxtx(ioaddr, 0);
1941
1942 del_timer_sync(&np->timer);
1943 del_timer_sync(&np->reset_timer);
1944
1945 free_irq(dev->irq, dev);
1946
1947 /* Free all the skbuffs in the Rx queue. */
1948 for (i = 0; i < RX_RING_SIZE; i++) {
1949 struct sk_buff *skb = np->rx_ring[i].skbuff;
1950
1951 np->rx_ring[i].status = 0;
1952 if (skb) {
1953 pci_unmap_single(np->pci_dev, np->rx_ring[i].buffer,
1954 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1955 dev_kfree_skb(skb);
1956 np->rx_ring[i].skbuff = NULL;
1957 }
1958 }
1959
1960 for (i = 0; i < TX_RING_SIZE; i++) {
1961 struct sk_buff *skb = np->tx_ring[i].skbuff;
1962
1963 if (skb) {
1964 pci_unmap_single(np->pci_dev, np->tx_ring[i].buffer,
1965 skb->len, PCI_DMA_TODEVICE);
1966 dev_kfree_skb(skb);
1967 np->tx_ring[i].skbuff = NULL;
1968 }
1969 }
1970
1971 return 0;
1972 }
1973
1974 static struct pci_device_id fealnx_pci_tbl[] = {
1975 {0x1516, 0x0800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1976 {0x1516, 0x0803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1977 {0x1516, 0x0891, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1978 {} /* terminate list */
1979 };
1980 MODULE_DEVICE_TABLE(pci, fealnx_pci_tbl);
1981
1982
1983 static struct pci_driver fealnx_driver = {
1984 .name = "fealnx",
1985 .id_table = fealnx_pci_tbl,
1986 .probe = fealnx_init_one,
1987 .remove = __devexit_p(fealnx_remove_one),
1988 };
1989
fealnx_init(void)1990 static int __init fealnx_init(void)
1991 {
1992 /* when a module, this is printed whether or not devices are found in probe */
1993 #ifdef MODULE
1994 printk(version);
1995 #endif
1996
1997 return pci_module_init(&fealnx_driver);
1998 }
1999
fealnx_exit(void)2000 static void __exit fealnx_exit(void)
2001 {
2002 pci_unregister_driver(&fealnx_driver);
2003 }
2004
2005 module_init(fealnx_init);
2006 module_exit(fealnx_exit);
2007