1 /*
2 * linux/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
3 *
4 * Toshiba RBTX4927 specific interrupt handlers
5 *
6 * Author: MontaVista Software, Inc.
7 * source@mvista.com
8 *
9 * Copyright 2001-2002 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
22 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
24 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
25 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 */
31
32
33 /*
34 IRQ Device
35 00 RBTX4927-ISA/00
36 01 RBTX4927-ISA/01 PS2/Keyboard
37 02 RBTX4927-ISA/02 Cascade RBTX4927-ISA (irqs 8-15)
38 03 RBTX4927-ISA/03
39 04 RBTX4927-ISA/04
40 05 RBTX4927-ISA/05
41 06 RBTX4927-ISA/06
42 07 RBTX4927-ISA/07
43 08 RBTX4927-ISA/08
44 09 RBTX4927-ISA/09
45 10 RBTX4927-ISA/10
46 11 RBTX4927-ISA/11
47 12 RBTX4927-ISA/12 PS2/Mouse (not supported at this time)
48 13 RBTX4927-ISA/13
49 14 RBTX4927-ISA/14 IDE
50 15 RBTX4927-ISA/15
51
52 16 TX4927-CP0/00 Software 0
53 17 TX4927-CP0/01 Software 1
54 18 TX4927-CP0/02 Cascade TX4927-CP0
55 19 TX4927-CP0/03 Multiplexed -- do not use
56 20 TX4927-CP0/04 Multiplexed -- do not use
57 21 TX4927-CP0/05 Multiplexed -- do not use
58 22 TX4927-CP0/06 Multiplexed -- do not use
59 23 TX4927-CP0/07 CPU TIMER
60
61 24 TX4927-PIC/00
62 25 TX4927-PIC/01
63 26 TX4927-PIC/02
64 27 TX4927-PIC/03 Cascade RBTX4927-IOC
65 28 TX4927-PIC/04
66 29 TX4927-PIC/05 RBTX4927 RTL-8019AS ethernet
67 30 TX4927-PIC/06
68 31 TX4927-PIC/07
69 32 TX4927-PIC/08 TX4927 SerialIO Channel 0
70 33 TX4927-PIC/09 TX4927 SerialIO Channel 1
71 34 TX4927-PIC/10
72 35 TX4927-PIC/11
73 36 TX4927-PIC/12
74 37 TX4927-PIC/13
75 38 TX4927-PIC/14
76 39 TX4927-PIC/15
77 40 TX4927-PIC/16 TX4927 PCI PCI-C
78 41 TX4927-PIC/17
79 42 TX4927-PIC/18
80 43 TX4927-PIC/19
81 44 TX4927-PIC/20
82 45 TX4927-PIC/21
83 46 TX4927-PIC/22 TX4927 PCI PCI-ERR
84 47 TX4927-PIC/23 TX4927 PCI PCI-PMA (not used)
85 48 TX4927-PIC/24
86 49 TX4927-PIC/25
87 50 TX4927-PIC/26
88 51 TX4927-PIC/27
89 52 TX4927-PIC/28
90 53 TX4927-PIC/29
91 54 TX4927-PIC/30
92 55 TX4927-PIC/31
93
94 56 RBTX4927-IOC/00 FPCIB0 PCI-D PJ4/A PJ5/B SB/C PJ6/D PJ7/A (SouthBridge/NotUsed) [RTL-8139=PJ4]
95 57 RBTX4927-IOC/01 FPCIB0 PCI-C PJ4/D PJ5/A SB/B PJ6/C PJ7/D (SouthBridge/NotUsed) [RTL-8139=PJ5]
96 58 RBTX4927-IOC/02 FPCIB0 PCI-B PJ4/C PJ5/D SB/A PJ6/B PJ7/C (SouthBridge/IDE/pin=1,INTR) [RTL-8139=NotSupported]
97 59 RBTX4927-IOC/03 FPCIB0 PCI-A PJ4/B PJ5/C SB/D PJ6/A PJ7/B (SouthBridge/USB/pin=4) [RTL-8139=PJ6]
98 60 RBTX4927-IOC/04
99 61 RBTX4927-IOC/05
100 62 RBTX4927-IOC/06
101 63 RBTX4927-IOC/07
102
103 NOTES:
104 SouthBridge/INTR is mapped to SouthBridge/A=PCI-B/#58
105 SouthBridge/ISA/pin=0 no pci irq used by this device
106 SouthBridge/IDE/pin=1 no pci irq used by this device, using INTR via ISA IRQ14
107 SouthBridge/USB/pin=4 using pci irq SouthBridge/D=PCI-A=#59
108 SouthBridge/PMC/pin=0 no pci irq used by this device
109 SuperIO/PS2/Keyboard, using INTR via ISA IRQ1
110 SuperIO/PS2/Mouse, using INTR via ISA IRQ12 (mouse not currently supported)
111 JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthBridge, JP4, JP5, JP6
112 */
113
114 #include <linux/config.h>
115 #include <linux/init.h>
116 #include <linux/kernel.h>
117 #include <linux/types.h>
118 #include <linux/mm.h>
119 #include <linux/swap.h>
120 #include <linux/ioport.h>
121 #include <linux/sched.h>
122 #include <linux/interrupt.h>
123 #include <linux/pci.h>
124 #include <linux/timex.h>
125 #include <asm/page.h>
126 #include <asm/io.h>
127 #include <asm/irq.h>
128 #include <asm/pci.h>
129 #include <asm/processor.h>
130 #include <asm/ptrace.h>
131 #include <asm/reboot.h>
132 #include <asm/time.h>
133 #include <asm/wbflush.h>
134 #include <linux/version.h>
135 #include <linux/bootmem.h>
136 #include <linux/blk.h>
137 #ifdef CONFIG_TOSHIBA_FPCIB0
138 #include <asm/smsc_fdc37m81x.h>
139 #endif
140 #include <asm/tx4927/toshiba_rbtx4927.h>
141
142
143 #undef TOSHIBA_RBTX4927_IRQ_DEBUG
144
145 #ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
146 #define TOSHIBA_RBTX4927_IRQ_NONE 0x00000000
147
148 #define TOSHIBA_RBTX4927_IRQ_INFO ( 1 << 0 )
149 #define TOSHIBA_RBTX4927_IRQ_WARN ( 1 << 1 )
150 #define TOSHIBA_RBTX4927_IRQ_EROR ( 1 << 2 )
151
152 #define TOSHIBA_RBTX4927_IRQ_IOC_INIT ( 1 << 10 )
153 #define TOSHIBA_RBTX4927_IRQ_IOC_STARTUP ( 1 << 11 )
154 #define TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN ( 1 << 12 )
155 #define TOSHIBA_RBTX4927_IRQ_IOC_ENABLE ( 1 << 13 )
156 #define TOSHIBA_RBTX4927_IRQ_IOC_DISABLE ( 1 << 14 )
157 #define TOSHIBA_RBTX4927_IRQ_IOC_MASK ( 1 << 15 )
158 #define TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ ( 1 << 16 )
159
160 #define TOSHIBA_RBTX4927_IRQ_ISA_INIT ( 1 << 20 )
161 #define TOSHIBA_RBTX4927_IRQ_ISA_STARTUP ( 1 << 21 )
162 #define TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN ( 1 << 22 )
163 #define TOSHIBA_RBTX4927_IRQ_ISA_ENABLE ( 1 << 23 )
164 #define TOSHIBA_RBTX4927_IRQ_ISA_DISABLE ( 1 << 24 )
165 #define TOSHIBA_RBTX4927_IRQ_ISA_MASK ( 1 << 25 )
166 #define TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ ( 1 << 26 )
167
168 #define TOSHIBA_RBTX4927_SETUP_ALL 0xffffffff
169 #endif
170
171
172 #ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
173 static const u32 toshiba_rbtx4927_irq_debug_flag =
174 (TOSHIBA_RBTX4927_IRQ_NONE | TOSHIBA_RBTX4927_IRQ_INFO |
175 TOSHIBA_RBTX4927_IRQ_WARN | TOSHIBA_RBTX4927_IRQ_EROR
176 // | TOSHIBA_RBTX4927_IRQ_IOC_INIT
177 // | TOSHIBA_RBTX4927_IRQ_IOC_STARTUP
178 // | TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN
179 // | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE
180 // | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE
181 // | TOSHIBA_RBTX4927_IRQ_IOC_MASK
182 // | TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ
183 // | TOSHIBA_RBTX4927_IRQ_ISA_INIT
184 // | TOSHIBA_RBTX4927_IRQ_ISA_STARTUP
185 // | TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN
186 // | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE
187 // | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE
188 // | TOSHIBA_RBTX4927_IRQ_ISA_MASK
189 // | TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ
190 );
191 #endif
192
193
194 #ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
195 #define TOSHIBA_RBTX4927_IRQ_DPRINTK(flag,str...) \
196 if ( (toshiba_rbtx4927_irq_debug_flag) & (flag) ) \
197 { \
198 char tmp[100]; \
199 sprintf( tmp, str ); \
200 printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \
201 }
202 #else
203 #define TOSHIBA_RBTX4927_IRQ_DPRINTK(flag,str...)
204 #endif
205
206
207
208
209 #define TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG 0
210 #define TOSHIBA_RBTX4927_IRQ_IOC_RAW_END 7
211
212 #define TOSHIBA_RBTX4927_IRQ_IOC_BEG ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG) /* 56 */
213 #define TOSHIBA_RBTX4927_IRQ_IOC_END ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_END) /* 63 */
214
215
216 #define TOSHIBA_RBTX4927_IRQ_ISA_BEG MI8259_IRQ_ISA_BEG
217 #define TOSHIBA_RBTX4927_IRQ_ISA_END MI8259_IRQ_ISA_END
218 #define TOSHIBA_RBTX4927_IRQ_ISA_MID ((TOSHIBA_RBTX4927_IRQ_ISA_BEG+TOSHIBA_RBTX4927_IRQ_ISA_END+1)/2)
219
220
221 #define TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC TX4927_IRQ_NEST_EXT_ON_PIC
222 #define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC (TOSHIBA_RBTX4927_IRQ_IOC_BEG+2)
223 #define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_ISA (TOSHIBA_RBTX4927_IRQ_ISA_BEG+2)
224
225 extern int tx4927_using_backplane;
226
227 #ifdef CONFIG_TOSHIBA_FPCIB0
228 extern void enable_8259A_irq(unsigned int irq);
229 extern void disable_8259A_irq(unsigned int irq);
230 extern void mask_and_ack_8259A(unsigned int irq);
231 #endif
232
233 static unsigned int toshiba_rbtx4927_irq_ioc_startup(unsigned int irq);
234 static void toshiba_rbtx4927_irq_ioc_shutdown(unsigned int irq);
235 static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq);
236 static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq);
237 static void toshiba_rbtx4927_irq_ioc_mask_and_ack(unsigned int irq);
238 static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq);
239
240 #ifdef CONFIG_TOSHIBA_FPCIB0
241 static unsigned int toshiba_rbtx4927_irq_isa_startup(unsigned int irq);
242 static void toshiba_rbtx4927_irq_isa_shutdown(unsigned int irq);
243 static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq);
244 static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq);
245 static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq);
246 static void toshiba_rbtx4927_irq_isa_end(unsigned int irq);
247 #endif
248
249 static spinlock_t toshiba_rbtx4927_ioc_lock = SPIN_LOCK_UNLOCKED;
250
251
252 #define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC"
253 static struct hw_interrupt_type toshiba_rbtx4927_irq_ioc_type = {
254 typename:TOSHIBA_RBTX4927_IOC_NAME,
255 startup:toshiba_rbtx4927_irq_ioc_startup,
256 shutdown:toshiba_rbtx4927_irq_ioc_shutdown,
257 enable:toshiba_rbtx4927_irq_ioc_enable,
258 disable:toshiba_rbtx4927_irq_ioc_disable,
259 ack:toshiba_rbtx4927_irq_ioc_mask_and_ack,
260 end:toshiba_rbtx4927_irq_ioc_end,
261 set_affinity:NULL
262 };
263 #define TOSHIBA_RBTX4927_IOC_INTR_ENAB 0xbc002000
264 #define TOSHIBA_RBTX4927_IOC_INTR_STAT 0xbc002006
265
266
267 #ifdef CONFIG_TOSHIBA_FPCIB0
268 #define TOSHIBA_RBTX4927_ISA_NAME "RBTX4927-ISA"
269 static struct hw_interrupt_type toshiba_rbtx4927_irq_isa_type = {
270 typename:TOSHIBA_RBTX4927_ISA_NAME,
271 startup:toshiba_rbtx4927_irq_isa_startup,
272 shutdown:toshiba_rbtx4927_irq_isa_shutdown,
273 enable:toshiba_rbtx4927_irq_isa_enable,
274 disable:toshiba_rbtx4927_irq_isa_disable,
275 ack:toshiba_rbtx4927_irq_isa_mask_and_ack,
276 end:toshiba_rbtx4927_irq_isa_end,
277 set_affinity:NULL
278 };
279 #endif
280
281
bit2num(u32 num)282 u32 bit2num(u32 num)
283 {
284 u32 i;
285
286 for (i = 0; i < (sizeof(num) * 8); i++) {
287 if (num & (1 << i)) {
288 return (i);
289 }
290 }
291 return (0);
292 }
293
toshiba_rbtx4927_irq_nested(int sw_irq)294 int toshiba_rbtx4927_irq_nested(int sw_irq)
295 {
296 u32 level3;
297
298 level3 = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f;
299 if (level3) {
300 sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + bit2num(level3);
301 if (sw_irq != TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC) {
302 goto RETURN;
303 }
304 }
305 #ifdef CONFIG_TOSHIBA_FPCIB0
306 {
307 u32 level4;
308 u32 level5;
309
310 if (tx4927_using_backplane) {
311 outb(0x0A, 0x20);
312 level4 = inb(0x20) & 0xff;
313 if (level4) {
314 sw_irq =
315 TOSHIBA_RBTX4927_IRQ_ISA_BEG +
316 bit2num(level4);
317 if (sw_irq !=
318 TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_ISA) {
319 goto RETURN;
320 }
321 }
322
323 outb(0x0A, 0xA0);
324 level5 = inb(0xA0) & 0xff;
325 if (level5) {
326 sw_irq =
327 TOSHIBA_RBTX4927_IRQ_ISA_MID +
328 bit2num(level5);
329 goto RETURN;
330 }
331 }
332 }
333 #endif
334
335 RETURN:
336 return (sw_irq);
337 }
338
339 //#define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, 0, 0, s, NULL, NULL }
340 #define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, SA_SHIRQ, 0, s, NULL, NULL }
341 static struct irqaction toshiba_rbtx4927_irq_ioc_action =
342 TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_IOC_NAME);
343 #ifdef CONFIG_TOSHIBA_FPCIB0
344 static struct irqaction toshiba_rbtx4927_irq_isa_master =
345 TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_ISA_NAME "/M");
346 static struct irqaction toshiba_rbtx4927_irq_isa_slave =
347 TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_ISA_NAME "/S");
348 #endif
349
350
351 /**********************************************************************************/
352 /* Functions for ioc */
353 /**********************************************************************************/
354
355
toshiba_rbtx4927_irq_ioc_init(void)356 static void __init toshiba_rbtx4927_irq_ioc_init(void)
357 {
358 int i;
359
360 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_INIT,
361 "beg=%d end=%d\n",
362 TOSHIBA_RBTX4927_IRQ_IOC_BEG,
363 TOSHIBA_RBTX4927_IRQ_IOC_END);
364
365 for (i = TOSHIBA_RBTX4927_IRQ_IOC_BEG;
366 i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++) {
367 irq_desc[i].status = IRQ_DISABLED;
368 irq_desc[i].action = 0;
369 irq_desc[i].depth = 3;
370 irq_desc[i].handler = &toshiba_rbtx4927_irq_ioc_type;
371 }
372
373 setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC,
374 &toshiba_rbtx4927_irq_ioc_action);
375
376 return;
377 }
378
toshiba_rbtx4927_irq_ioc_startup(unsigned int irq)379 static unsigned int toshiba_rbtx4927_irq_ioc_startup(unsigned int irq)
380 {
381 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_STARTUP,
382 "irq=%d\n", irq);
383
384 if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
385 || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
386 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
387 "bad irq=%d\n", irq);
388 panic("\n");
389 }
390
391 toshiba_rbtx4927_irq_ioc_enable(irq);
392
393 return (0);
394 }
395
396
toshiba_rbtx4927_irq_ioc_shutdown(unsigned int irq)397 static void toshiba_rbtx4927_irq_ioc_shutdown(unsigned int irq)
398 {
399 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN,
400 "irq=%d\n", irq);
401
402 if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
403 || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
404 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
405 "bad irq=%d\n", irq);
406 panic("\n");
407 }
408
409 toshiba_rbtx4927_irq_ioc_disable(irq);
410
411 return;
412 }
413
414
toshiba_rbtx4927_irq_ioc_enable(unsigned int irq)415 static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq)
416 {
417 unsigned long flags;
418 volatile unsigned char v;
419
420 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENABLE,
421 "irq=%d\n", irq);
422
423 if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
424 || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
425 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
426 "bad irq=%d\n", irq);
427 panic("\n");
428 }
429
430 spin_lock_irqsave(&toshiba_rbtx4927_ioc_lock, flags);
431
432 v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
433 v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
434 TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v);
435
436 spin_unlock_irqrestore(&toshiba_rbtx4927_ioc_lock, flags);
437
438 return;
439 }
440
441
toshiba_rbtx4927_irq_ioc_disable(unsigned int irq)442 static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq)
443 {
444 unsigned long flags;
445 volatile unsigned char v;
446
447 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_DISABLE,
448 "irq=%d\n", irq);
449
450 if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
451 || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
452 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
453 "bad irq=%d\n", irq);
454 panic("\n");
455 }
456
457 spin_lock_irqsave(&toshiba_rbtx4927_ioc_lock, flags);
458
459 v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
460 v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
461 TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v);
462
463 spin_unlock_irqrestore(&toshiba_rbtx4927_ioc_lock, flags);
464
465 return;
466 }
467
468
toshiba_rbtx4927_irq_ioc_mask_and_ack(unsigned int irq)469 static void toshiba_rbtx4927_irq_ioc_mask_and_ack(unsigned int irq)
470 {
471 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_MASK,
472 "irq=%d\n", irq);
473
474 if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
475 || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
476 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
477 "bad irq=%d\n", irq);
478 panic("\n");
479 }
480
481 toshiba_rbtx4927_irq_ioc_disable(irq);
482
483 return;
484 }
485
486
toshiba_rbtx4927_irq_ioc_end(unsigned int irq)487 static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq)
488 {
489 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ,
490 "irq=%d\n", irq);
491
492 if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
493 || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
494 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
495 "bad irq=%d\n", irq);
496 panic("\n");
497 }
498
499 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
500 toshiba_rbtx4927_irq_ioc_enable(irq);
501 }
502
503 return;
504 }
505
506
507 /**********************************************************************************/
508 /* Functions for isa */
509 /**********************************************************************************/
510
511
512 #ifdef CONFIG_TOSHIBA_FPCIB0
toshiba_rbtx4927_irq_isa_init(void)513 static void __init toshiba_rbtx4927_irq_isa_init(void)
514 {
515 int i;
516
517 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_INIT,
518 "beg=%d end=%d\n",
519 TOSHIBA_RBTX4927_IRQ_ISA_BEG,
520 TOSHIBA_RBTX4927_IRQ_ISA_END);
521
522 for (i = TOSHIBA_RBTX4927_IRQ_ISA_BEG;
523 i <= TOSHIBA_RBTX4927_IRQ_ISA_END; i++) {
524 irq_desc[i].status = IRQ_DISABLED;
525 irq_desc[i].action = 0;
526 irq_desc[i].depth =
527 ((i < TOSHIBA_RBTX4927_IRQ_ISA_MID) ? (4) : (5));
528 irq_desc[i].handler = &toshiba_rbtx4927_irq_isa_type;
529 }
530
531 setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC,
532 &toshiba_rbtx4927_irq_isa_master);
533 setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_ISA,
534 &toshiba_rbtx4927_irq_isa_slave);
535
536 /* make sure we are looking at IRR (not ISR) */
537 outb(0x0A, 0x20);
538 outb(0x0A, 0xA0);
539
540 return;
541 }
542 #endif
543
544
545 #ifdef CONFIG_TOSHIBA_FPCIB0
toshiba_rbtx4927_irq_isa_startup(unsigned int irq)546 static unsigned int toshiba_rbtx4927_irq_isa_startup(unsigned int irq)
547 {
548 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_STARTUP,
549 "irq=%d\n", irq);
550
551 if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
552 || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
553 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
554 "bad irq=%d\n", irq);
555 panic("\n");
556 }
557
558 toshiba_rbtx4927_irq_isa_enable(irq);
559
560 return (0);
561 }
562 #endif
563
564
565 #ifdef CONFIG_TOSHIBA_FPCIB0
toshiba_rbtx4927_irq_isa_shutdown(unsigned int irq)566 static void toshiba_rbtx4927_irq_isa_shutdown(unsigned int irq)
567 {
568 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN,
569 "irq=%d\n", irq);
570
571 if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
572 || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
573 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
574 "bad irq=%d\n", irq);
575 panic("\n");
576 }
577
578 toshiba_rbtx4927_irq_isa_disable(irq);
579
580 return;
581 }
582 #endif
583
584
585 #ifdef CONFIG_TOSHIBA_FPCIB0
toshiba_rbtx4927_irq_isa_enable(unsigned int irq)586 static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq)
587 {
588 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_ENABLE,
589 "irq=%d\n", irq);
590
591 if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
592 || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
593 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
594 "bad irq=%d\n", irq);
595 panic("\n");
596 }
597
598 enable_8259A_irq(irq);
599
600 return;
601 }
602 #endif
603
604
605 #ifdef CONFIG_TOSHIBA_FPCIB0
toshiba_rbtx4927_irq_isa_disable(unsigned int irq)606 static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq)
607 {
608 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_DISABLE,
609 "irq=%d\n", irq);
610
611 if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
612 || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
613 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
614 "bad irq=%d\n", irq);
615 panic("\n");
616 }
617
618 disable_8259A_irq(irq);
619
620 return;
621 }
622 #endif
623
624
625 #ifdef CONFIG_TOSHIBA_FPCIB0
toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq)626 static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq)
627 {
628 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_MASK,
629 "irq=%d\n", irq);
630
631 if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
632 || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
633 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
634 "bad irq=%d\n", irq);
635 panic("\n");
636 }
637
638 mask_and_ack_8259A(irq);
639
640 return;
641 }
642 #endif
643
644
645 #ifdef CONFIG_TOSHIBA_FPCIB0
toshiba_rbtx4927_irq_isa_end(unsigned int irq)646 static void toshiba_rbtx4927_irq_isa_end(unsigned int irq)
647 {
648 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ,
649 "irq=%d\n", irq);
650
651 if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
652 || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
653 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
654 "bad irq=%d\n", irq);
655 panic("\n");
656 }
657
658 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
659 toshiba_rbtx4927_irq_isa_enable(irq);
660 }
661
662 return;
663 }
664 #endif
665
666
init_IRQ(void)667 void __init init_IRQ(void)
668 {
669 extern void tx4927_irq_init(void);
670
671 cli();
672
673 tx4927_irq_init();
674 toshiba_rbtx4927_irq_ioc_init();
675 #ifdef CONFIG_TOSHIBA_FPCIB0
676 {
677 if (tx4927_using_backplane) {
678 toshiba_rbtx4927_irq_isa_init();
679 }
680 }
681 #endif
682
683 #ifdef CONFIG_PCI
684 {
685 extern void toshiba_rbtx4927_pci_irq_init(void);
686 toshiba_rbtx4927_pci_irq_init();
687 }
688 #endif
689
690 wbflush();
691
692 return;
693 }
694
toshiba_rbtx4927_irq_dump(char * key)695 void toshiba_rbtx4927_irq_dump(char *key)
696 {
697 #ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
698 {
699 u32 i, j = 0;
700 for (i = 0; i < NR_IRQS; i++) {
701 if (strcmp(irq_desc[i].handler->typename, "none")
702 == 0)
703 continue;
704
705 if ((i >= 1)
706 && (irq_desc[i - 1].handler->typename ==
707 irq_desc[i].handler->typename)) {
708 j++;
709 } else {
710 j = 0;
711 }
712 TOSHIBA_RBTX4927_IRQ_DPRINTK
713 (TOSHIBA_RBTX4927_IRQ_INFO,
714 "%s irq=0x%02x/%3d s=0x%08x h=0x%08x a=0x%08x ah=0x%08x d=%1d n=%s/%02d\n",
715 key, i, i, irq_desc[i].status,
716 (u32) irq_desc[i].handler,
717 (u32) irq_desc[i].action,
718 (u32) (irq_desc[i].action ? irq_desc[i].
719 action->handler : 0),
720 irq_desc[i].depth,
721 irq_desc[i].handler->typename, j);
722 }
723 }
724 #endif
725 return;
726 }
727
toshiba_rbtx4927_irq_dump_pics(char * s)728 void toshiba_rbtx4927_irq_dump_pics(char *s)
729 {
730 u32 level0_m;
731 u32 level0_s;
732 u32 level1_m;
733 u32 level1_s;
734 u32 level2;
735 u32 level2_p;
736 u32 level2_s;
737 u32 level3_m;
738 u32 level3_s;
739 u32 level4_m;
740 u32 level4_s;
741 u32 level5_m;
742 u32 level5_s;
743
744 if (s == NULL)
745 s = "null";
746
747 level0_m = (read_c0_status() & 0x0000ff00) >> 8;
748 level0_s = (read_c0_cause() & 0x0000ff00) >> 8;
749
750 level1_m = level0_m;
751 level1_s = level0_s & 0x87;
752
753 level2 = TX4927_RD(0xff1ff6a0);
754 level2_p = (((level2 & 0x10000)) ? 0 : 1);
755 level2_s = (((level2 & 0x1f) == 0x1f) ? 0 : (level2 & 0x1f));
756
757 level3_m = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_ENAB) & 0x1f;
758 level3_s = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f;
759
760 level4_m = inb(0x21);
761 outb(0x0A, 0x20);
762 level4_s = inb(0x20);
763
764 level5_m = inb(0xa1);
765 outb(0x0A, 0xa0);
766 level5_s = inb(0xa0);
767
768 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
769 "dump_raw_pic() ");
770 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
771 "cp0:m=0x%02x/s=0x%02x ", level0_m,
772 level0_s);
773 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
774 "cp0:m=0x%02x/s=0x%02x ", level1_m,
775 level1_s);
776 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
777 "pic:e=0x%02x/s=0x%02x ", level2_p,
778 level2_s);
779 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
780 "ioc:m=0x%02x/s=0x%02x ", level3_m,
781 level3_s);
782 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
783 "sbm:m=0x%02x/s=0x%02x ", level4_m,
784 level4_s);
785 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
786 "sbs:m=0x%02x/s=0x%02x ", level5_m,
787 level5_s);
788 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, "[%s]\n",
789 s);
790
791 return;
792 }
793