1 /* $Id: pgtsrmmu.h,v 1.31 2000/07/16 21:48:52 anton Exp $
2 * pgtsrmmu.h: SRMMU page table defines and code.
3 *
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 */
6
7 #ifndef _SPARC_PGTSRMMU_H
8 #define _SPARC_PGTSRMMU_H
9
10 #include <asm/page.h>
11
12 /* Number of contexts is implementation-dependent; 64k is the most we support */
13 #define SRMMU_MAX_CONTEXTS 65536
14
15 /* PMD_SHIFT determines the size of the area a second-level page table can map */
16 #define SRMMU_PMD_SHIFT 18
17 #define SRMMU_PMD_SIZE (1UL << SRMMU_PMD_SHIFT)
18 #define SRMMU_PMD_MASK (~(SRMMU_PMD_SIZE-1))
19 #define SRMMU_PMD_ALIGN(addr) (((addr)+SRMMU_PMD_SIZE-1)&SRMMU_PMD_MASK)
20
21 /* PGDIR_SHIFT determines what a third-level page table entry can map */
22 #define SRMMU_PGDIR_SHIFT 24
23 #define SRMMU_PGDIR_SIZE (1UL << SRMMU_PGDIR_SHIFT)
24 #define SRMMU_PGDIR_MASK (~(SRMMU_PGDIR_SIZE-1))
25 #define SRMMU_PGDIR_ALIGN(addr) (((addr)+SRMMU_PGDIR_SIZE-1)&SRMMU_PGDIR_MASK)
26
27 #define SRMMU_PTRS_PER_PTE 64
28 #define SRMMU_PTRS_PER_PMD 64
29 #define SRMMU_PTRS_PER_PGD 256
30
31 #define SRMMU_PTE_TABLE_SIZE 0x100 /* 64 entries, 4 bytes a piece */
32 #define SRMMU_PMD_TABLE_SIZE 0x100 /* 64 entries, 4 bytes a piece */
33 #define SRMMU_PGD_TABLE_SIZE 0x400 /* 256 entries, 4 bytes a piece */
34
35 /* Definition of the values in the ET field of PTD's and PTE's */
36 #define SRMMU_ET_MASK 0x3
37 #define SRMMU_ET_INVALID 0x0
38 #define SRMMU_ET_PTD 0x1
39 #define SRMMU_ET_PTE 0x2
40 #define SRMMU_ET_REPTE 0x3 /* AIEEE, SuperSparc II reverse endian page! */
41
42 /* Physical page extraction from PTP's and PTE's. */
43 #define SRMMU_CTX_PMASK 0xfffffff0
44 #define SRMMU_PTD_PMASK 0xfffffff0
45 #define SRMMU_PTE_PMASK 0xffffff00
46
47 /* The pte non-page bits. Some notes:
48 * 1) cache, dirty, valid, and ref are frobbable
49 * for both supervisor and user pages.
50 * 2) exec and write will only give the desired effect
51 * on user pages
52 * 3) use priv and priv_readonly for changing the
53 * characteristics of supervisor ptes
54 */
55 #define SRMMU_CACHE 0x80
56 #define SRMMU_DIRTY 0x40
57 #define SRMMU_REF 0x20
58 #define SRMMU_EXEC 0x08
59 #define SRMMU_WRITE 0x04
60 #define SRMMU_VALID 0x02 /* SRMMU_ET_PTE */
61 #define SRMMU_PRIV 0x1c
62 #define SRMMU_PRIV_RDONLY 0x18
63
64 #define SRMMU_CHG_MASK (0xffffff00 | SRMMU_REF | SRMMU_DIRTY)
65
66 /* Some day I will implement true fine grained access bits for
67 * user pages because the SRMMU gives us the capabilities to
68 * enforce all the protection levels that vma's can have.
69 * XXX But for now...
70 */
71 #define SRMMU_PAGE_NONE __pgprot(SRMMU_VALID | SRMMU_CACHE | \
72 SRMMU_PRIV | SRMMU_REF)
73 #define SRMMU_PAGE_SHARED __pgprot(SRMMU_VALID | SRMMU_CACHE | \
74 SRMMU_EXEC | SRMMU_WRITE | SRMMU_REF)
75 #define SRMMU_PAGE_COPY __pgprot(SRMMU_VALID | SRMMU_CACHE | \
76 SRMMU_EXEC | SRMMU_REF)
77 #define SRMMU_PAGE_RDONLY __pgprot(SRMMU_VALID | SRMMU_CACHE | \
78 SRMMU_EXEC | SRMMU_REF)
79 #define SRMMU_PAGE_KERNEL __pgprot(SRMMU_VALID | SRMMU_CACHE | SRMMU_PRIV | \
80 SRMMU_DIRTY | SRMMU_REF)
81
82 /* SRMMU Register addresses in ASI 0x4. These are valid for all
83 * current SRMMU implementations that exist.
84 */
85 #define SRMMU_CTRL_REG 0x00000000
86 #define SRMMU_CTXTBL_PTR 0x00000100
87 #define SRMMU_CTX_REG 0x00000200
88 #define SRMMU_FAULT_STATUS 0x00000300
89 #define SRMMU_FAULT_ADDR 0x00000400
90
91 #define WINDOW_FLUSH(tmp1, tmp2) \
92 mov 0, tmp1; \
93 98: ld [%g6 + AOFF_task_thread + AOFF_thread_uwinmask], tmp2; \
94 orcc %g0, tmp2, %g0; \
95 add tmp1, 1, tmp1; \
96 bne 98b; \
97 save %sp, -64, %sp; \
98 99: subcc tmp1, 1, tmp1; \
99 bne 99b; \
100 restore %g0, %g0, %g0;
101
102 #ifndef __ASSEMBLY__
103
104 /* Accessing the MMU control register. */
srmmu_get_mmureg(void)105 extern __inline__ unsigned int srmmu_get_mmureg(void)
106 {
107 unsigned int retval;
108 __asm__ __volatile__("lda [%%g0] %1, %0\n\t" :
109 "=r" (retval) :
110 "i" (ASI_M_MMUREGS));
111 return retval;
112 }
113
srmmu_set_mmureg(unsigned long regval)114 extern __inline__ void srmmu_set_mmureg(unsigned long regval)
115 {
116 __asm__ __volatile__("sta %0, [%%g0] %1\n\t" : :
117 "r" (regval), "i" (ASI_M_MMUREGS) : "memory");
118
119 }
120
srmmu_set_ctable_ptr(unsigned long paddr)121 extern __inline__ void srmmu_set_ctable_ptr(unsigned long paddr)
122 {
123 paddr = ((paddr >> 4) & SRMMU_CTX_PMASK);
124 __asm__ __volatile__("sta %0, [%1] %2\n\t" : :
125 "r" (paddr), "r" (SRMMU_CTXTBL_PTR),
126 "i" (ASI_M_MMUREGS) :
127 "memory");
128 }
129
srmmu_get_ctable_ptr(void)130 extern __inline__ unsigned long srmmu_get_ctable_ptr(void)
131 {
132 unsigned int retval;
133
134 __asm__ __volatile__("lda [%1] %2, %0\n\t" :
135 "=r" (retval) :
136 "r" (SRMMU_CTXTBL_PTR),
137 "i" (ASI_M_MMUREGS));
138 return (retval & SRMMU_CTX_PMASK) << 4;
139 }
140
srmmu_set_context(int context)141 extern __inline__ void srmmu_set_context(int context)
142 {
143 __asm__ __volatile__("sta %0, [%1] %2\n\t" : :
144 "r" (context), "r" (SRMMU_CTX_REG),
145 "i" (ASI_M_MMUREGS) : "memory");
146 }
147
srmmu_get_context(void)148 extern __inline__ int srmmu_get_context(void)
149 {
150 register int retval;
151 __asm__ __volatile__("lda [%1] %2, %0\n\t" :
152 "=r" (retval) :
153 "r" (SRMMU_CTX_REG),
154 "i" (ASI_M_MMUREGS));
155 return retval;
156 }
157
srmmu_get_fstatus(void)158 extern __inline__ unsigned int srmmu_get_fstatus(void)
159 {
160 unsigned int retval;
161
162 __asm__ __volatile__("lda [%1] %2, %0\n\t" :
163 "=r" (retval) :
164 "r" (SRMMU_FAULT_STATUS), "i" (ASI_M_MMUREGS));
165 return retval;
166 }
167
srmmu_get_faddr(void)168 extern __inline__ unsigned int srmmu_get_faddr(void)
169 {
170 unsigned int retval;
171
172 __asm__ __volatile__("lda [%1] %2, %0\n\t" :
173 "=r" (retval) :
174 "r" (SRMMU_FAULT_ADDR), "i" (ASI_M_MMUREGS));
175 return retval;
176 }
177
178 /* This is guaranteed on all SRMMU's. */
srmmu_flush_whole_tlb(void)179 extern __inline__ void srmmu_flush_whole_tlb(void)
180 {
181 __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
182 "r" (0x400), /* Flush entire TLB!! */
183 "i" (ASI_M_FLUSH_PROBE) : "memory");
184
185 }
186
187 /* These flush types are not available on all chips... */
srmmu_flush_tlb_ctx(void)188 extern __inline__ void srmmu_flush_tlb_ctx(void)
189 {
190 __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
191 "r" (0x300), /* Flush TLB ctx.. */
192 "i" (ASI_M_FLUSH_PROBE) : "memory");
193
194 }
195
srmmu_flush_tlb_region(unsigned long addr)196 extern __inline__ void srmmu_flush_tlb_region(unsigned long addr)
197 {
198 addr &= SRMMU_PGDIR_MASK;
199 __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
200 "r" (addr | 0x200), /* Flush TLB region.. */
201 "i" (ASI_M_FLUSH_PROBE) : "memory");
202
203 }
204
205
srmmu_flush_tlb_segment(unsigned long addr)206 extern __inline__ void srmmu_flush_tlb_segment(unsigned long addr)
207 {
208 addr &= SRMMU_PMD_MASK;
209 __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
210 "r" (addr | 0x100), /* Flush TLB segment.. */
211 "i" (ASI_M_FLUSH_PROBE) : "memory");
212
213 }
214
srmmu_flush_tlb_page(unsigned long page)215 extern __inline__ void srmmu_flush_tlb_page(unsigned long page)
216 {
217 page &= PAGE_MASK;
218 __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
219 "r" (page), /* Flush TLB page.. */
220 "i" (ASI_M_FLUSH_PROBE) : "memory");
221
222 }
223
srmmu_hwprobe(unsigned long vaddr)224 extern __inline__ unsigned long srmmu_hwprobe(unsigned long vaddr)
225 {
226 unsigned long retval;
227
228 vaddr &= PAGE_MASK;
229 __asm__ __volatile__("lda [%1] %2, %0\n\t" :
230 "=r" (retval) :
231 "r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE));
232
233 return retval;
234 }
235
236 extern __inline__ int
srmmu_get_pte(unsigned long addr)237 srmmu_get_pte (unsigned long addr)
238 {
239 register unsigned long entry;
240
241 __asm__ __volatile__("\n\tlda [%1] %2,%0\n\t" :
242 "=r" (entry):
243 "r" ((addr & 0xfffff000) | 0x400), "i" (ASI_M_FLUSH_PROBE));
244 return entry;
245 }
246
247 extern unsigned long (*srmmu_read_physical)(unsigned long paddr);
248 extern void (*srmmu_write_physical)(unsigned long paddr, unsigned long word);
249
250 #endif /* !(__ASSEMBLY__) */
251
252 #endif /* !(_SPARC_PGTSRMMU_H) */
253