1 /*
2 ** IA64 System Bus Adapter (SBA) I/O MMU manager
3 **
4 ** (c) Copyright 2002-2004 Alex Williamson
5 ** (c) Copyright 2002-2003 Grant Grundler
6 ** (c) Copyright 2002-2004 Hewlett-Packard Company
7 **
8 ** Portions (c) 2000 Grant Grundler (from parisc I/O MMU code)
9 ** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code)
10 **
11 ** This program is free software; you can redistribute it and/or modify
12 ** it under the terms of the GNU General Public License as published by
13 ** the Free Software Foundation; either version 2 of the License, or
14 ** (at your option) any later version.
15 **
16 **
17 ** This module initializes the IOC (I/O Controller) found on HP
18 ** McKinley machines and their successors.
19 **
20 */
21
22 #include <linux/config.h>
23 #include <linux/types.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/spinlock.h>
27 #include <linux/slab.h>
28 #include <linux/init.h>
29 #include <linux/mm.h>
30 #include <linux/string.h>
31 #include <linux/pci.h>
32 #include <linux/proc_fs.h>
33 #include <linux/seq_file.h>
34 #include <linux/acpi.h>
35 #include <linux/efi.h>
36
37 #include <asm/delay.h> /* ia64_get_itc() */
38 #include <asm/io.h>
39 #include <asm/page.h> /* PAGE_OFFSET */
40 #include <asm/system.h> /* wmb() */
41 #include <asm/bitops.h> /* hweight64() */
42
43
44 #define PFX "IOC: "
45
46 /*
47 ** Enabling timing search of the pdir resource map. Output in /proc.
48 ** Disabled by default to optimize performance.
49 */
50 #undef PDIR_SEARCH_TIMING
51
52 /*
53 ** This option allows cards capable of 64bit DMA to bypass the IOMMU. If
54 ** not defined, all DMA will be 32bit and go through the TLB.
55 */
56 #define ALLOW_IOV_BYPASS
57
58 /*
59 ** If a device prefetches beyond the end of a valid pdir entry, it will cause
60 ** a hard failure, ie. MCA. Version 3.0 and later of the zx1 LBA should
61 ** disconnect on 4k boundaries and prevent such issues. If the device is
62 ** particularly agressive, this option will keep the entire pdir valid such
63 ** that prefetching will hit a valid address. This could severely impact
64 ** error containment, and is therefore off by default. The page that is
65 ** used for spill-over is poisoned, so that should help debugging somewhat.
66 */
67 #undef FULL_VALID_PDIR
68
69 #define ENABLE_MARK_CLEAN
70
71 /*
72 ** The number of debug flags is a clue - this code is fragile.
73 */
74 #undef DEBUG_SBA_INIT
75 #undef DEBUG_SBA_RUN
76 #undef DEBUG_SBA_RUN_SG
77 #undef DEBUG_SBA_RESOURCE
78 #undef ASSERT_PDIR_SANITY
79 #undef DEBUG_LARGE_SG_ENTRIES
80 #undef DEBUG_BYPASS
81
82 #if defined(FULL_VALID_PDIR) && defined(ASSERT_PDIR_SANITY)
83 #error FULL_VALID_PDIR and ASSERT_PDIR_SANITY are mutually exclusive
84 #endif
85
86 #define SBA_INLINE __inline__
87 /* #define SBA_INLINE */
88
89 #ifdef DEBUG_SBA_INIT
90 #define DBG_INIT(x...) printk(x)
91 #else
92 #define DBG_INIT(x...)
93 #endif
94
95 #ifdef DEBUG_SBA_RUN
96 #define DBG_RUN(x...) printk(x)
97 #else
98 #define DBG_RUN(x...)
99 #endif
100
101 #ifdef DEBUG_SBA_RUN_SG
102 #define DBG_RUN_SG(x...) printk(x)
103 #else
104 #define DBG_RUN_SG(x...)
105 #endif
106
107
108 #ifdef DEBUG_SBA_RESOURCE
109 #define DBG_RES(x...) printk(x)
110 #else
111 #define DBG_RES(x...)
112 #endif
113
114 #ifdef DEBUG_BYPASS
115 #define DBG_BYPASS(x...) printk(x)
116 #else
117 #define DBG_BYPASS(x...)
118 #endif
119
120 #ifdef ASSERT_PDIR_SANITY
121 #define ASSERT(expr) \
122 if(!(expr)) { \
123 printk( "\n" __FILE__ ":%d: Assertion " #expr " failed!\n",__LINE__); \
124 panic(#expr); \
125 }
126 #else
127 #define ASSERT(expr)
128 #endif
129
130 /*
131 ** The number of pdir entries to "free" before issuing
132 ** a read to PCOM register to flush out PCOM writes.
133 ** Interacts with allocation granularity (ie 4 or 8 entries
134 ** allocated and free'd/purged at a time might make this
135 ** less interesting).
136 */
137 #define DELAYED_RESOURCE_CNT 16
138
139 #define DEFAULT_DMA_HINT_REG 0
140
141 #define ZX1_IOC_ID ((PCI_DEVICE_ID_HP_ZX1_IOC << 16) | PCI_VENDOR_ID_HP)
142 #define REO_IOC_ID ((PCI_DEVICE_ID_HP_REO_IOC << 16) | PCI_VENDOR_ID_HP)
143 #define SX1000_IOC_ID ((PCI_DEVICE_ID_HP_SX1000_IOC << 16) | PCI_VENDOR_ID_HP)
144
145 #define ZX1_IOC_OFFSET 0x1000 /* ACPI reports SBA, we want IOC */
146
147 #define IOC_FUNC_ID 0x000
148 #define IOC_FCLASS 0x008 /* function class, bist, header, rev... */
149 #define IOC_IBASE 0x300 /* IO TLB */
150 #define IOC_IMASK 0x308
151 #define IOC_PCOM 0x310
152 #define IOC_TCNFG 0x318
153 #define IOC_PDIR_BASE 0x320
154
155 /* AGP GART driver looks for this */
156 #define ZX1_SBA_IOMMU_COOKIE 0x0000badbadc0ffeeUL
157
158 /*
159 ** The zx1 IOC supports 4/8/16/64KB page sizes (see TCNFG register)
160 **
161 ** Some IOCs (sx1000) can run at the above pages sizes, but are
162 ** really only supported using the IOC at a 4k page size.
163 **
164 ** iovp_size could only be greater than PAGE_SIZE if we are
165 ** confident the drivers really only touch the next physical
166 ** page iff that driver instance owns it.
167 */
168 static unsigned long iovp_size;
169 static unsigned long iovp_shift;
170 static unsigned long iovp_mask;
171
172 struct ioc {
173 void *ioc_hpa; /* I/O MMU base address */
174 char *res_map; /* resource map, bit == pdir entry */
175 u64 *pdir_base; /* physical base address */
176 unsigned long ibase; /* pdir IOV Space base */
177 unsigned long imask; /* pdir IOV Space mask */
178
179 unsigned long *res_hint; /* next avail IOVP - circular search */
180 spinlock_t res_lock;
181 unsigned long hint_mask_pdir; /* bits used for DMA hints */
182 unsigned int res_bitshift; /* from the RIGHT! */
183 unsigned int res_size; /* size of resource map in bytes */
184 unsigned int hint_shift_pdir;
185 unsigned long dma_mask;
186 #if DELAYED_RESOURCE_CNT > 0
187 int saved_cnt;
188 struct sba_dma_pair {
189 dma_addr_t iova;
190 size_t size;
191 } saved[DELAYED_RESOURCE_CNT];
192 #endif
193
194 #ifdef PDIR_SEARCH_TIMING
195 #define SBA_SEARCH_SAMPLE 0x100
196 unsigned long avg_search[SBA_SEARCH_SAMPLE];
197 unsigned long avg_idx; /* current index into avg_search */
198 #endif
199
200 /* Stuff we don't need in performance path */
201 struct ioc *next; /* list of IOC's in system */
202 acpi_handle handle; /* for multiple IOC's */
203 const char *name;
204 unsigned int func_id;
205 unsigned int rev; /* HW revision of chip */
206 u32 iov_size;
207 unsigned int pdir_size; /* in bytes, determined by IOV Space size */
208 struct pci_dev *sac_only_dev;
209 };
210
211 static struct ioc *ioc_list;
212 static int reserve_sba_gart = 1;
213
214 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
215 #define sba_sg_address(sg) (page_address((sg)->page) + (sg)->offset)
216 #else
217 #define sba_sg_address(sg) ((sg)->address ? (sg)->address : \
218 page_address((sg)->page) + (sg)->offset)
219 #endif
220
221 #ifdef FULL_VALID_PDIR
222 static u64 prefetch_spill_page;
223 #endif
224
225 #ifdef CONFIG_PCI
226 # define GET_IOC(dev) ((struct ioc *) PCI_CONTROLLER(dev)->iommu)
227 #else
228 # define GET_IOC(dev) NULL
229 #endif
230
231 /*
232 ** DMA_CHUNK_SIZE is used by the SCSI mid-layer to break up
233 ** (or rather not merge) DMA's into managable chunks.
234 ** On parisc, this is more of the software/tuning constraint
235 ** rather than the HW. I/O MMU allocation alogorithms can be
236 ** faster with smaller size is (to some degree).
237 */
238 #define DMA_CHUNK_SIZE (BITS_PER_LONG*iovp_size)
239
240 #define ROUNDUP(x,y) ((x + ((y)-1)) & ~((y)-1))
241
242 /************************************
243 ** SBA register read and write support
244 **
245 ** BE WARNED: register writes are posted.
246 ** (ie follow writes which must reach HW with a read)
247 **
248 */
249 #define READ_REG(addr) __raw_readq(addr)
250 #define WRITE_REG(val, addr) __raw_writeq(val, addr)
251
252 #ifdef DEBUG_SBA_INIT
253
254 /**
255 * sba_dump_tlb - debugging only - print IOMMU operating parameters
256 * @hpa: base address of the IOMMU
257 *
258 * Print the size/location of the IO MMU PDIR.
259 */
260 static void
sba_dump_tlb(char * hpa)261 sba_dump_tlb(char *hpa)
262 {
263 DBG_INIT("IO TLB at 0x%p\n", (void *)hpa);
264 DBG_INIT("IOC_IBASE : %016lx\n", READ_REG(hpa+IOC_IBASE));
265 DBG_INIT("IOC_IMASK : %016lx\n", READ_REG(hpa+IOC_IMASK));
266 DBG_INIT("IOC_TCNFG : %016lx\n", READ_REG(hpa+IOC_TCNFG));
267 DBG_INIT("IOC_PDIR_BASE: %016lx\n", READ_REG(hpa+IOC_PDIR_BASE));
268 DBG_INIT("\n");
269 }
270 #endif
271
272
273 #ifdef ASSERT_PDIR_SANITY
274
275 /**
276 * sba_dump_pdir_entry - debugging only - print one IOMMU PDIR entry
277 * @ioc: IO MMU structure which owns the pdir we are interested in.
278 * @msg: text to print ont the output line.
279 * @pide: pdir index.
280 *
281 * Print one entry of the IO MMU PDIR in human readable form.
282 */
283 static void
sba_dump_pdir_entry(struct ioc * ioc,char * msg,uint pide)284 sba_dump_pdir_entry(struct ioc *ioc, char *msg, uint pide)
285 {
286 /* start printing from lowest pde in rval */
287 u64 *ptr = &ioc->pdir_base[pide & ~(BITS_PER_LONG - 1)];
288 unsigned long *rptr = (unsigned long *) &ioc->res_map[(pide >>3) & -sizeof(unsigned long)];
289 uint rcnt;
290
291 printk(KERN_DEBUG "SBA: %s rp %p bit %d rval 0x%lx\n",
292 msg, rptr, pide & (BITS_PER_LONG - 1), *rptr);
293
294 rcnt = 0;
295 while (rcnt < BITS_PER_LONG) {
296 printk(KERN_DEBUG "%s %2d %p %016Lx\n",
297 (rcnt == (pide & (BITS_PER_LONG - 1)))
298 ? " -->" : " ",
299 rcnt, ptr, (unsigned long long) *ptr );
300 rcnt++;
301 ptr++;
302 }
303 printk(KERN_DEBUG "%s", msg);
304 }
305
306
307 /**
308 * sba_check_pdir - debugging only - consistency checker
309 * @ioc: IO MMU structure which owns the pdir we are interested in.
310 * @msg: text to print ont the output line.
311 *
312 * Verify the resource map and pdir state is consistent
313 */
314 static int
sba_check_pdir(struct ioc * ioc,char * msg)315 sba_check_pdir(struct ioc *ioc, char *msg)
316 {
317 u64 *rptr_end = (u64 *) &(ioc->res_map[ioc->res_size]);
318 u64 *rptr = (u64 *) ioc->res_map; /* resource map ptr */
319 u64 *pptr = ioc->pdir_base; /* pdir ptr */
320 uint pide = 0;
321
322 while (rptr < rptr_end) {
323 u64 rval;
324 int rcnt; /* number of bits we might check */
325
326 rval = *rptr;
327 rcnt = 64;
328
329 while (rcnt) {
330 /* Get last byte and highest bit from that */
331 u32 pde = ((u32)((*pptr >> (63)) & 0x1));
332 if ((rval & 0x1) ^ pde)
333 {
334 /*
335 ** BUMMER! -- res_map != pdir --
336 ** Dump rval and matching pdir entries
337 */
338 sba_dump_pdir_entry(ioc, msg, pide);
339 return(1);
340 }
341 rcnt--;
342 rval >>= 1; /* try the next bit */
343 pptr++;
344 pide++;
345 }
346 rptr++; /* look at next word of res_map */
347 }
348 /* It'd be nice if we always got here :^) */
349 return 0;
350 }
351
352
353 /**
354 * sba_dump_sg - debugging only - print Scatter-Gather list
355 * @ioc: IO MMU structure which owns the pdir we are interested in.
356 * @startsg: head of the SG list
357 * @nents: number of entries in SG list
358 *
359 * print the SG list so we can verify it's correct by hand.
360 */
361 static void
sba_dump_sg(struct ioc * ioc,struct scatterlist * startsg,int nents)362 sba_dump_sg( struct ioc *ioc, struct scatterlist *startsg, int nents)
363 {
364 while (nents-- > 0) {
365 printk(KERN_DEBUG " %d : DMA %08lx/%05x CPU %p\n", nents,
366 startsg->dma_address, startsg->dma_length,
367 sba_sg_address(startsg));
368 startsg++;
369 }
370 }
371
372 static void
sba_check_sg(struct ioc * ioc,struct scatterlist * startsg,int nents)373 sba_check_sg( struct ioc *ioc, struct scatterlist *startsg, int nents)
374 {
375 struct scatterlist *the_sg = startsg;
376 int the_nents = nents;
377
378 while (the_nents-- > 0) {
379 if (sba_sg_address(the_sg) == 0x0UL)
380 sba_dump_sg(NULL, startsg, nents);
381 the_sg++;
382 }
383 }
384
385 #endif /* ASSERT_PDIR_SANITY */
386
387
388
389
390 /**************************************************************
391 *
392 * I/O Pdir Resource Management
393 *
394 * Bits set in the resource map are in use.
395 * Each bit can represent a number of pages.
396 * LSbs represent lower addresses (IOVA's).
397 *
398 ***************************************************************/
399 #define PAGES_PER_RANGE 1 /* could increase this to 4 or 8 if needed */
400
401 /* Convert from IOVP to IOVA and vice versa. */
402 #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((ioc->ibase) | (iovp) | (offset))
403 #define SBA_IOVP(ioc,iova) ((iova) & ~(ioc->ibase))
404
405 #define PDIR_ENTRY_SIZE sizeof(u64)
406
407 #define PDIR_INDEX(iovp) ((iovp)>>iovp_shift)
408
409 #define RESMAP_MASK(n) ~(~0UL << (n))
410 #define RESMAP_IDX_MASK (sizeof(unsigned long) - 1)
411
412
413 /**
414 * For most cases the normal get_order is sufficient, however it limits us
415 * to PAGE_SIZE being the minimum mapping alignment and TC flush granularity.
416 * It only incurs about 1 clock cycle to use this one with the static variable
417 * and makes the code more intuitive.
418 */
419 static SBA_INLINE int
get_iovp_order(unsigned long size)420 get_iovp_order (unsigned long size)
421 {
422 long double d = size - 1;
423 long order;
424
425 __asm__ ("getf.exp %0=%1" : "=r"(order) : "f"(d));
426 order = order - iovp_shift - 0xffff + 1;
427 if (order < 0)
428 order = 0;
429 return order;
430 }
431
432 /**
433 * sba_search_bitmap - find free space in IO PDIR resource bitmap
434 * @ioc: IO MMU structure which owns the pdir we are interested in.
435 * @bits_wanted: number of entries we need.
436 *
437 * Find consecutive free bits in resource bitmap.
438 * Each bit represents one entry in the IO Pdir.
439 * Cool perf optimization: search for log2(size) bits at a time.
440 */
441 static SBA_INLINE unsigned long
sba_search_bitmap(struct ioc * ioc,unsigned long bits_wanted)442 sba_search_bitmap(struct ioc *ioc, unsigned long bits_wanted)
443 {
444 unsigned long *res_ptr = ioc->res_hint;
445 unsigned long *res_end = (unsigned long *) &(ioc->res_map[ioc->res_size]);
446 unsigned long pide = ~0UL;
447
448 ASSERT(((unsigned long) ioc->res_hint & (sizeof(unsigned long) - 1UL)) == 0);
449 ASSERT(res_ptr < res_end);
450
451 /*
452 * N.B. REO/Grande defect AR2305 can cause TLB fetch timeouts
453 * if a TLB entry is purged while in use. sba_mark_invalid()
454 * purges IOTLB entries in power-of-two sizes, so we also
455 * allocate IOVA space in power-of-two sizes.
456 */
457 bits_wanted = 1UL << get_iovp_order(bits_wanted << PAGE_SHIFT);
458 if (bits_wanted > (BITS_PER_LONG/2)) {
459 /* Search word at a time - no mask needed */
460 for(; res_ptr < res_end; ++res_ptr) {
461 if (*res_ptr == 0) {
462 *res_ptr = RESMAP_MASK(bits_wanted);
463 pide = ((unsigned long)res_ptr - (unsigned long)ioc->res_map);
464 pide <<= 3; /* convert to bit address */
465 break;
466 }
467 }
468 /* point to the next word on next pass */
469 res_ptr++;
470 ioc->res_bitshift = 0;
471 } else {
472 /*
473 ** Search the resource bit map on well-aligned values.
474 ** "o" is the alignment.
475 ** We need the alignment to invalidate I/O TLB using
476 ** SBA HW features in the unmap path.
477 */
478 unsigned long o = 1 << get_iovp_order(bits_wanted << iovp_shift);
479 uint bitshiftcnt = ROUNDUP(ioc->res_bitshift, o);
480 unsigned long mask;
481
482 if (bitshiftcnt >= BITS_PER_LONG) {
483 bitshiftcnt = 0;
484 res_ptr++;
485 }
486 mask = RESMAP_MASK(bits_wanted) << bitshiftcnt;
487
488 DBG_RES("%s() o %ld %p", __FUNCTION__, o, res_ptr);
489 while(res_ptr < res_end)
490 {
491 DBG_RES(" %p %lx %lx\n", res_ptr, mask, *res_ptr);
492 ASSERT(0 != mask);
493 if(0 == ((*res_ptr) & mask)) {
494 *res_ptr |= mask; /* mark resources busy! */
495 pide = ((unsigned long)res_ptr - (unsigned long)ioc->res_map);
496 pide <<= 3; /* convert to bit address */
497 pide += bitshiftcnt;
498 break;
499 }
500 mask <<= o;
501 bitshiftcnt += o;
502 if (0 == mask) {
503 mask = RESMAP_MASK(bits_wanted);
504 bitshiftcnt=0;
505 res_ptr++;
506 }
507 }
508 /* look in the same word on the next pass */
509 ioc->res_bitshift = bitshiftcnt + bits_wanted;
510 }
511
512 /* wrapped ? */
513 if (res_end <= res_ptr) {
514 ioc->res_hint = (unsigned long *) ioc->res_map;
515 ioc->res_bitshift = 0;
516 } else {
517 ioc->res_hint = res_ptr;
518 }
519 return (pide);
520 }
521
522
523 /**
524 * sba_alloc_range - find free bits and mark them in IO PDIR resource bitmap
525 * @ioc: IO MMU structure which owns the pdir we are interested in.
526 * @size: number of bytes to create a mapping for
527 *
528 * Given a size, find consecutive unmarked and then mark those bits in the
529 * resource bit map.
530 */
531 static int
sba_alloc_range(struct ioc * ioc,size_t size)532 sba_alloc_range(struct ioc *ioc, size_t size)
533 {
534 unsigned int pages_needed = size >> iovp_shift;
535 #ifdef PDIR_SEARCH_TIMING
536 unsigned long itc_start = ia64_get_itc();
537 #endif
538 unsigned long pide;
539
540 ASSERT(pages_needed);
541 ASSERT(pages_needed <= BITS_PER_LONG);
542 ASSERT(0 == (size & ~iovp_mask));
543
544 /*
545 ** "seek and ye shall find"...praying never hurts either...
546 */
547
548 pide = sba_search_bitmap(ioc, pages_needed);
549 if (pide >= (ioc->res_size << 3)) {
550 pide = sba_search_bitmap(ioc, pages_needed);
551 if (pide >= (ioc->res_size << 3))
552 panic(__FILE__ ": I/O MMU @ %p is out of mapping resources\n",
553 ioc->ioc_hpa);
554 }
555
556 #ifdef ASSERT_PDIR_SANITY
557 /* verify the first enable bit is clear */
558 if(0x00 != ((u8 *) ioc->pdir_base)[pide*PDIR_ENTRY_SIZE + 7]) {
559 sba_dump_pdir_entry(ioc, "sba_search_bitmap() botched it?", pide);
560 }
561 #endif
562
563 DBG_RES("%s(%x) %d -> %lx hint %x/%x\n",
564 __FUNCTION__, size, pages_needed, pide,
565 (uint) ((unsigned long) ioc->res_hint - (unsigned long) ioc->res_map),
566 ioc->res_bitshift );
567
568 #ifdef PDIR_SEARCH_TIMING
569 ioc->avg_search[ioc->avg_idx++] = ia64_get_itc() - itc_start;
570 ioc->avg_idx &= SBA_SEARCH_SAMPLE - 1;
571 #endif
572
573 return (pide);
574 }
575
576
577 /**
578 * sba_free_range - unmark bits in IO PDIR resource bitmap
579 * @ioc: IO MMU structure which owns the pdir we are interested in.
580 * @iova: IO virtual address which was previously allocated.
581 * @size: number of bytes to create a mapping for
582 *
583 * clear bits in the ioc's resource map
584 */
585 static SBA_INLINE void
sba_free_range(struct ioc * ioc,dma_addr_t iova,size_t size)586 sba_free_range(struct ioc *ioc, dma_addr_t iova, size_t size)
587 {
588 unsigned long iovp = SBA_IOVP(ioc, iova);
589 unsigned int pide = PDIR_INDEX(iovp);
590 unsigned int ridx = pide >> 3; /* convert bit to byte address */
591 unsigned long *res_ptr = (unsigned long *) &((ioc)->res_map[ridx & ~RESMAP_IDX_MASK]);
592
593 int bits_not_wanted = size >> iovp_shift;
594 bits_not_wanted = 1UL << get_iovp_order(bits_not_wanted << PAGE_SHIFT);
595
596 /* 3-bits "bit" address plus 2 (or 3) bits for "byte" == bit in word */
597 unsigned long m = RESMAP_MASK(bits_not_wanted) << (pide & (BITS_PER_LONG - 1));
598
599 DBG_RES("%s( ,%x,%x) %x/%lx %x %p %lx\n",
600 __FUNCTION__, (uint) iova, size,
601 bits_not_wanted, m, pide, res_ptr, *res_ptr);
602
603 ASSERT(m != 0);
604 ASSERT(bits_not_wanted);
605 ASSERT((bits_not_wanted * iovp_size) <= DMA_CHUNK_SIZE);
606 ASSERT(bits_not_wanted <= BITS_PER_LONG);
607 ASSERT((*res_ptr & m) == m); /* verify same bits are set */
608 *res_ptr &= ~m;
609 }
610
611
612 /**************************************************************
613 *
614 * "Dynamic DMA Mapping" support (aka "Coherent I/O")
615 *
616 ***************************************************************/
617
618 #define SBA_DMA_HINT(ioc, val) ((val) << (ioc)->hint_shift_pdir)
619
620
621 /**
622 * sba_io_pdir_entry - fill in one IO PDIR entry
623 * @pdir_ptr: pointer to IO PDIR entry
624 * @vba: Virtual CPU address of buffer to map
625 *
626 * SBA Mapping Routine
627 *
628 * Given a virtual address (vba, arg1) sba_io_pdir_entry()
629 * loads the I/O PDIR entry pointed to by pdir_ptr (arg0).
630 * Each IO Pdir entry consists of 8 bytes as shown below
631 * (LSB == bit 0):
632 *
633 * 63 40 11 7 0
634 * +-+---------------------+----------------------------------+----+--------+
635 * |V| U | PPN[39:12] | U | FF |
636 * +-+---------------------+----------------------------------+----+--------+
637 *
638 * V == Valid Bit
639 * U == Unused
640 * PPN == Physical Page Number
641 *
642 * The physical address fields are filled with the results of virt_to_phys()
643 * on the vba.
644 */
645
646 #if 1
647 #define sba_io_pdir_entry(pdir_ptr, vba) *pdir_ptr = ((vba & ~0xE000000000000FFFULL) \
648 | 0x8000000000000000ULL)
649 #else
650 void SBA_INLINE
sba_io_pdir_entry(u64 * pdir_ptr,unsigned long vba)651 sba_io_pdir_entry(u64 *pdir_ptr, unsigned long vba)
652 {
653 *pdir_ptr = ((vba & ~0xE000000000000FFFULL) | 0x80000000000000FFULL);
654 }
655 #endif
656
657 #ifdef ENABLE_MARK_CLEAN
658 /**
659 * Since DMA is i-cache coherent, any (complete) pages that were written via
660 * DMA can be marked as "clean" so that update_mmu_cache() doesn't have to
661 * flush them when they get mapped into an executable vm-area.
662 */
663 static void
mark_clean(void * addr,size_t size)664 mark_clean (void *addr, size_t size)
665 {
666 unsigned long pg_addr, end;
667
668 pg_addr = PAGE_ALIGN((unsigned long) addr);
669 end = (unsigned long) addr + size;
670 while (pg_addr + PAGE_SIZE <= end) {
671 struct page *page = virt_to_page((void *)pg_addr);
672 set_bit(PG_arch_1, &page->flags);
673 pg_addr += PAGE_SIZE;
674 }
675 }
676 #endif
677
678 /**
679 * sba_mark_invalid - invalidate one or more IO PDIR entries
680 * @ioc: IO MMU structure which owns the pdir we are interested in.
681 * @iova: IO Virtual Address mapped earlier
682 * @byte_cnt: number of bytes this mapping covers.
683 *
684 * Marking the IO PDIR entry(ies) as Invalid and invalidate
685 * corresponding IO TLB entry. The PCOM (Purge Command Register)
686 * is to purge stale entries in the IO TLB when unmapping entries.
687 *
688 * The PCOM register supports purging of multiple pages, with a minium
689 * of 1 page and a maximum of 2GB. Hardware requires the address be
690 * aligned to the size of the range being purged. The size of the range
691 * must be a power of 2. The "Cool perf optimization" in the
692 * allocation routine helps keep that true.
693 */
694 static SBA_INLINE void
sba_mark_invalid(struct ioc * ioc,dma_addr_t iova,size_t byte_cnt)695 sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt)
696 {
697 u32 iovp = (u32) SBA_IOVP(ioc,iova);
698
699 int off = PDIR_INDEX(iovp);
700
701 /* Must be non-zero and rounded up */
702 ASSERT(byte_cnt > 0);
703 ASSERT(0 == (byte_cnt & ~iovp_mask));
704
705 #ifdef ASSERT_PDIR_SANITY
706 /* Assert first pdir entry is set */
707 if (!(ioc->pdir_base[off] >> 60)) {
708 sba_dump_pdir_entry(ioc,"sba_mark_invalid()", PDIR_INDEX(iovp));
709 }
710 #endif
711
712 if (byte_cnt <= iovp_size)
713 {
714 ASSERT(off < ioc->pdir_size);
715
716 iovp |= iovp_shift; /* set "size" field for PCOM */
717
718 #ifndef FULL_VALID_PDIR
719 /*
720 ** clear I/O PDIR entry "valid" bit
721 ** Do NOT clear the rest - save it for debugging.
722 ** We should only clear bits that have previously
723 ** been enabled.
724 */
725 ioc->pdir_base[off] &= ~(0x80000000000000FFULL);
726 #else
727 /*
728 ** If we want to maintain the PDIR as valid, put in
729 ** the spill page so devices prefetching won't
730 ** cause a hard fail.
731 */
732 ioc->pdir_base[off] = (0x80000000000000FFULL | prefetch_spill_page);
733 #endif
734 } else {
735 u32 t = get_iovp_order(byte_cnt) + iovp_shift;
736
737 iovp |= t;
738 ASSERT(t <= 31); /* 2GB! Max value of "size" field */
739
740 do {
741 /* verify this pdir entry is enabled */
742 ASSERT(ioc->pdir_base[off] >> 63);
743 #ifndef FULL_VALID_PDIR
744 /* clear I/O Pdir entry "valid" bit first */
745 ioc->pdir_base[off] &= ~(0x80000000000000FFULL);
746 #else
747 ioc->pdir_base[off] = (0x80000000000000FFULL | prefetch_spill_page);
748 #endif
749 off++;
750 byte_cnt -= iovp_size;
751 } while (byte_cnt > 0);
752 }
753
754 WRITE_REG(iovp | ioc->ibase, ioc->ioc_hpa+IOC_PCOM);
755 }
756
757 /**
758 * sba_map_single - map one buffer and return IOVA for DMA
759 * @dev: instance of PCI owned by the driver that's asking.
760 * @addr: driver buffer to map.
761 * @size: number of bytes to map in driver buffer.
762 * @dir: R/W or both.
763 *
764 * See Documentation/DMA-mapping.txt
765 */
766 dma_addr_t
sba_map_single(struct pci_dev * dev,void * addr,size_t size,int dir)767 sba_map_single(struct pci_dev *dev, void *addr, size_t size, int dir)
768 {
769 struct ioc *ioc;
770 unsigned long flags;
771 dma_addr_t iovp;
772 dma_addr_t offset;
773 u64 *pdir_start;
774 int pide;
775 #ifdef ALLOW_IOV_BYPASS
776 unsigned long pci_addr = virt_to_phys(addr);
777 #endif
778
779 ioc = GET_IOC(dev);
780 ASSERT(ioc);
781
782 #ifdef ALLOW_IOV_BYPASS
783 /*
784 ** Check if the PCI device can DMA to ptr... if so, just return ptr
785 */
786 if ((pci_addr & ~dev->dma_mask) == 0) {
787 /*
788 ** Device is bit capable of DMA'ing to the buffer...
789 ** just return the PCI address of ptr
790 */
791 DBG_BYPASS("sba_map_single() bypass mask/addr: 0x%lx/0x%lx\n",
792 dev->dma_mask, pci_addr);
793 return pci_addr;
794 }
795 #endif
796
797 ASSERT(size > 0);
798 ASSERT(size <= DMA_CHUNK_SIZE);
799
800 /* save offset bits */
801 offset = ((dma_addr_t) (long) addr) & ~iovp_mask;
802
803 /* round up to nearest iovp_size */
804 size = (size + offset + ~iovp_mask) & iovp_mask;
805
806 spin_lock_irqsave(&ioc->res_lock, flags);
807 #ifdef ASSERT_PDIR_SANITY
808 if (sba_check_pdir(ioc,"Check before sba_map_single()"))
809 panic("Sanity check failed");
810 #endif
811
812 pide = sba_alloc_range(ioc, size);
813 iovp = (dma_addr_t) pide << iovp_shift;
814
815 DBG_RUN("%s() 0x%p -> 0x%lx\n",
816 __FUNCTION__, addr, (long) iovp | offset);
817
818 pdir_start = &(ioc->pdir_base[pide]);
819
820 while (size > 0) {
821 ASSERT(((u8 *)pdir_start)[7] == 0); /* verify availability */
822 sba_io_pdir_entry(pdir_start, (unsigned long) addr);
823
824 DBG_RUN(" pdir 0x%p %lx\n", pdir_start, *pdir_start);
825
826 addr += iovp_size;
827 size -= iovp_size;
828 pdir_start++;
829 }
830 /* force pdir update */
831 wmb();
832
833 /* form complete address */
834 #ifdef ASSERT_PDIR_SANITY
835 sba_check_pdir(ioc,"Check after sba_map_single()");
836 #endif
837 spin_unlock_irqrestore(&ioc->res_lock, flags);
838 return SBA_IOVA(ioc, iovp, offset, DEFAULT_DMA_HINT_REG);
839 }
840
841 /**
842 * sba_unmap_single - unmap one IOVA and free resources
843 * @dev: instance of PCI owned by the driver that's asking.
844 * @iova: IOVA of driver buffer previously mapped.
845 * @size: number of bytes mapped in driver buffer.
846 * @dir: R/W or both.
847 *
848 * See Documentation/DMA-mapping.txt
849 */
sba_unmap_single(struct pci_dev * dev,dma_addr_t iova,size_t size,int dir)850 void sba_unmap_single(struct pci_dev *dev, dma_addr_t iova, size_t size, int dir)
851 {
852 struct ioc *ioc;
853 #if DELAYED_RESOURCE_CNT > 0
854 struct sba_dma_pair *d;
855 #endif
856 unsigned long flags;
857 dma_addr_t offset;
858
859 ioc = GET_IOC(dev);
860 ASSERT(ioc);
861
862 #ifdef ALLOW_IOV_BYPASS
863 if ((iova & ioc->imask) != ioc->ibase) {
864 /*
865 ** Address does not fall w/in IOVA, must be bypassing
866 */
867 DBG_BYPASS("sba_unmap_single() bypass addr: 0x%lx\n", iova);
868
869 #ifdef ENABLE_MARK_CLEAN
870 if (dir == PCI_DMA_FROMDEVICE) {
871 mark_clean(phys_to_virt(iova), size);
872 }
873 #endif
874 return;
875 }
876 #endif
877 offset = iova & ~iovp_mask;
878
879 DBG_RUN("%s() iovp 0x%lx/%x\n",
880 __FUNCTION__, (long) iova, size);
881
882 iova ^= offset; /* clear offset bits */
883 size += offset;
884 size = ROUNDUP(size, iovp_size);
885
886 spin_lock_irqsave(&ioc->res_lock, flags);
887
888 #if DELAYED_RESOURCE_CNT > 0
889 d = &(ioc->saved[ioc->saved_cnt]);
890 d->iova = iova;
891 d->size = size;
892 if (++(ioc->saved_cnt) >= DELAYED_RESOURCE_CNT) {
893 int cnt = ioc->saved_cnt;
894 while (cnt--) {
895 sba_mark_invalid(ioc, d->iova, d->size);
896 sba_free_range(ioc, d->iova, d->size);
897 d--;
898 }
899 ioc->saved_cnt = 0;
900 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
901 }
902 #else /* DELAYED_RESOURCE_CNT == 0 */
903 sba_mark_invalid(ioc, iova, size);
904 sba_free_range(ioc, iova, size);
905 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
906 #endif /* DELAYED_RESOURCE_CNT == 0 */
907 #ifdef ENABLE_MARK_CLEAN
908 if (dir == PCI_DMA_FROMDEVICE) {
909 u32 iovp = (u32) SBA_IOVP(ioc,iova);
910 int off = PDIR_INDEX(iovp);
911 void *addr;
912
913 if (size <= iovp_size) {
914 addr = phys_to_virt(ioc->pdir_base[off] &
915 ~0xE000000000000FFFULL);
916 mark_clean(addr, size);
917 } else {
918 size_t byte_cnt = size;
919
920 do {
921 addr = phys_to_virt(ioc->pdir_base[off] &
922 ~0xE000000000000FFFULL);
923 mark_clean(addr, min(byte_cnt, iovp_size));
924 off++;
925 byte_cnt -= iovp_size;
926
927 } while (byte_cnt > 0);
928 }
929 }
930 #endif
931 spin_unlock_irqrestore(&ioc->res_lock, flags);
932
933 /* XXX REVISIT for 2.5 Linux - need syncdma for zero-copy support.
934 ** For Astro based systems this isn't a big deal WRT performance.
935 ** As long as 2.4 kernels copyin/copyout data from/to userspace,
936 ** we don't need the syncdma. The issue here is I/O MMU cachelines
937 ** are *not* coherent in all cases. May be hwrev dependent.
938 ** Need to investigate more.
939 asm volatile("syncdma");
940 */
941 }
942
943
944 /**
945 * sba_alloc_coherent - allocate/map shared mem for DMA
946 * @dev: instance of PCI owned by the driver that's asking.
947 * @size: number of bytes mapped in driver buffer.
948 * @dma_handle: IOVA of new buffer.
949 *
950 * See Documentation/DMA-mapping.txt
951 */
952 void *
sba_alloc_coherent(struct pci_dev * dev,size_t size,dma_addr_t * dma_handle)953 sba_alloc_coherent (struct pci_dev *dev, size_t size, dma_addr_t *dma_handle)
954 {
955 struct ioc *ioc;
956 void *addr;
957
958 if (!dev)
959 return NULL; /* only support PCI */
960
961 addr = (void *) __get_free_pages(GFP_ATOMIC, get_order(size));
962 if (!addr)
963 return NULL;
964
965 /*
966 * REVISIT: if sba_map_single starts needing more than dma_mask from the
967 * device, this needs to be updated.
968 */
969 ioc = GET_IOC(dev);
970 ASSERT(ioc);
971 *dma_handle = sba_map_single(ioc->sac_only_dev, addr, size, 0);
972
973 memset(addr, 0, size);
974 return addr;
975 }
976
977
978 /**
979 * sba_free_coherent - free/unmap shared mem for DMA
980 * @dev: instance of PCI owned by the driver that's asking.
981 * @size: number of bytes mapped in driver buffer.
982 * @vaddr: virtual address IOVA of "consistent" buffer.
983 * @dma_handler: IO virtual address of "consistent" buffer.
984 *
985 * See Documentation/DMA-mapping.txt
986 */
sba_free_coherent(struct pci_dev * dev,size_t size,void * vaddr,dma_addr_t dma_handle)987 void sba_free_coherent (struct pci_dev *dev, size_t size, void *vaddr, dma_addr_t dma_handle)
988 {
989 sba_unmap_single(dev, dma_handle, size, 0);
990 free_pages((unsigned long) vaddr, get_order(size));
991 }
992
993
994 /*
995 ** Since 0 is a valid pdir_base index value, can't use that
996 ** to determine if a value is valid or not. Use a flag to indicate
997 ** the SG list entry contains a valid pdir index.
998 */
999 #define PIDE_FLAG 0x1UL
1000
1001 #ifdef DEBUG_LARGE_SG_ENTRIES
1002 int dump_run_sg = 0;
1003 #endif
1004
1005
1006 /**
1007 * sba_fill_pdir - write allocated SG entries into IO PDIR
1008 * @ioc: IO MMU structure which owns the pdir we are interested in.
1009 * @startsg: list of IOVA/size pairs
1010 * @nents: number of entries in startsg list
1011 *
1012 * Take preprocessed SG list and write corresponding entries
1013 * in the IO PDIR.
1014 */
1015
1016 static SBA_INLINE int
sba_fill_pdir(struct ioc * ioc,struct scatterlist * startsg,int nents)1017 sba_fill_pdir(
1018 struct ioc *ioc,
1019 struct scatterlist *startsg,
1020 int nents)
1021 {
1022 struct scatterlist *dma_sg = startsg; /* pointer to current DMA */
1023 int n_mappings = 0;
1024 u64 *pdirp = 0;
1025 unsigned long dma_offset = 0;
1026
1027 dma_sg--;
1028 while (nents-- > 0) {
1029 int cnt = startsg->dma_length;
1030 startsg->dma_length = 0;
1031
1032 #ifdef DEBUG_LARGE_SG_ENTRIES
1033 if (dump_run_sg)
1034 printk(" %2d : %08lx/%05x %p\n",
1035 nents, startsg->dma_address, cnt,
1036 sba_sg_address(startsg));
1037 #else
1038 DBG_RUN_SG(" %d : %08lx/%05x %p\n",
1039 nents, startsg->dma_address, cnt,
1040 sba_sg_address(startsg));
1041 #endif
1042 /*
1043 ** Look for the start of a new DMA stream
1044 */
1045 if (startsg->dma_address & PIDE_FLAG) {
1046 u32 pide = startsg->dma_address & ~PIDE_FLAG;
1047 dma_offset = (unsigned long) pide & ~iovp_mask;
1048 startsg->dma_address = 0;
1049 dma_sg++;
1050 dma_sg->dma_address = pide | ioc->ibase;
1051 pdirp = &(ioc->pdir_base[pide >> iovp_shift]);
1052 n_mappings++;
1053 }
1054
1055 /*
1056 ** Look for a VCONTIG chunk
1057 */
1058 if (cnt) {
1059 unsigned long vaddr = (unsigned long) sba_sg_address(startsg);
1060 ASSERT(pdirp);
1061
1062 /* Since multiple Vcontig blocks could make up
1063 ** one DMA stream, *add* cnt to dma_len.
1064 */
1065 dma_sg->dma_length += cnt;
1066 cnt += dma_offset;
1067 dma_offset=0; /* only want offset on first chunk */
1068 cnt = ROUNDUP(cnt, iovp_size);
1069 do {
1070 sba_io_pdir_entry(pdirp, vaddr);
1071 vaddr += iovp_size;
1072 cnt -= iovp_size;
1073 pdirp++;
1074 } while (cnt > 0);
1075 }
1076 startsg++;
1077 }
1078 /* force pdir update */
1079 wmb();
1080
1081 #ifdef DEBUG_LARGE_SG_ENTRIES
1082 dump_run_sg = 0;
1083 #endif
1084 return(n_mappings);
1085 }
1086
1087
1088 /*
1089 ** Two address ranges are DMA contiguous *iff* "end of prev" and
1090 ** "start of next" are both on an IOV page boundary.
1091 **
1092 ** (shift left is a quick trick to mask off upper bits)
1093 */
1094 #define DMA_CONTIG(__X, __Y) \
1095 (((((unsigned long) __X) | ((unsigned long) __Y)) << (BITS_PER_LONG - iovp_shift)) == 0UL)
1096
1097
1098 /**
1099 * sba_coalesce_chunks - preprocess the SG list
1100 * @ioc: IO MMU structure which owns the pdir we are interested in.
1101 * @startsg: list of IOVA/size pairs
1102 * @nents: number of entries in startsg list
1103 *
1104 * First pass is to walk the SG list and determine where the breaks are
1105 * in the DMA stream. Allocates PDIR entries but does not fill them.
1106 * Returns the number of DMA chunks.
1107 *
1108 * Doing the fill separate from the coalescing/allocation keeps the
1109 * code simpler. Future enhancement could make one pass through
1110 * the sglist do both.
1111 */
1112 static SBA_INLINE int
sba_coalesce_chunks(struct ioc * ioc,struct scatterlist * startsg,int nents)1113 sba_coalesce_chunks( struct ioc *ioc,
1114 struct scatterlist *startsg,
1115 int nents)
1116 {
1117 struct scatterlist *vcontig_sg; /* VCONTIG chunk head */
1118 unsigned long vcontig_len; /* len of VCONTIG chunk */
1119 unsigned long vcontig_end;
1120 struct scatterlist *dma_sg; /* next DMA stream head */
1121 unsigned long dma_offset, dma_len; /* start/len of DMA stream */
1122 int n_mappings = 0;
1123
1124 while (nents > 0) {
1125 unsigned long vaddr = (unsigned long) sba_sg_address(startsg);
1126
1127 /*
1128 ** Prepare for first/next DMA stream
1129 */
1130 dma_sg = vcontig_sg = startsg;
1131 dma_len = vcontig_len = vcontig_end = startsg->length;
1132 vcontig_end += vaddr;
1133 dma_offset = vaddr & ~iovp_mask;
1134
1135 /* PARANOID: clear entries */
1136 startsg->dma_address = startsg->dma_length = 0;
1137
1138 /*
1139 ** This loop terminates one iteration "early" since
1140 ** it's always looking one "ahead".
1141 */
1142 while (--nents > 0) {
1143 unsigned long vaddr; /* tmp */
1144
1145 startsg++;
1146
1147 /* PARANOID */
1148 startsg->dma_address = startsg->dma_length = 0;
1149
1150 /* catch brokenness in SCSI layer */
1151 ASSERT(startsg->length <= DMA_CHUNK_SIZE);
1152
1153 /*
1154 ** First make sure current dma stream won't
1155 ** exceed DMA_CHUNK_SIZE if we coalesce the
1156 ** next entry.
1157 */
1158 if (((dma_len + dma_offset + startsg->length + ~iovp_mask) & iovp_mask)
1159 > DMA_CHUNK_SIZE)
1160 break;
1161
1162 /*
1163 ** Then look for virtually contiguous blocks.
1164 **
1165 ** append the next transaction?
1166 */
1167 vaddr = (unsigned long) sba_sg_address(startsg);
1168 if (vcontig_end == vaddr)
1169 {
1170 vcontig_len += startsg->length;
1171 vcontig_end += startsg->length;
1172 dma_len += startsg->length;
1173 continue;
1174 }
1175
1176 #ifdef DEBUG_LARGE_SG_ENTRIES
1177 dump_run_sg = (vcontig_len > iovp_size);
1178 #endif
1179
1180 /*
1181 ** Not virtually contigous.
1182 ** Terminate prev chunk.
1183 ** Start a new chunk.
1184 **
1185 ** Once we start a new VCONTIG chunk, dma_offset
1186 ** can't change. And we need the offset from the first
1187 ** chunk - not the last one. Ergo Successive chunks
1188 ** must start on page boundaries and dove tail
1189 ** with it's predecessor.
1190 */
1191 vcontig_sg->dma_length = vcontig_len;
1192
1193 vcontig_sg = startsg;
1194 vcontig_len = startsg->length;
1195
1196 /*
1197 ** 3) do the entries end/start on page boundaries?
1198 ** Don't update vcontig_end until we've checked.
1199 */
1200 if (DMA_CONTIG(vcontig_end, vaddr))
1201 {
1202 vcontig_end = vcontig_len + vaddr;
1203 dma_len += vcontig_len;
1204 continue;
1205 } else {
1206 break;
1207 }
1208 }
1209
1210 /*
1211 ** End of DMA Stream
1212 ** Terminate last VCONTIG block.
1213 ** Allocate space for DMA stream.
1214 */
1215 vcontig_sg->dma_length = vcontig_len;
1216 dma_len = (dma_len + dma_offset + ~iovp_mask) & iovp_mask;
1217 ASSERT(dma_len <= DMA_CHUNK_SIZE);
1218 dma_sg->dma_address = (dma_addr_t) (PIDE_FLAG
1219 | (sba_alloc_range(ioc, dma_len) << iovp_shift)
1220 | dma_offset);
1221 n_mappings++;
1222 }
1223
1224 return n_mappings;
1225 }
1226
1227
1228 /**
1229 * sba_map_sg - map Scatter/Gather list
1230 * @dev: instance of PCI owned by the driver that's asking.
1231 * @sglist: array of buffer/length pairs
1232 * @nents: number of entries in list
1233 * @dir: R/W or both.
1234 *
1235 * See Documentation/DMA-mapping.txt
1236 */
sba_map_sg(struct pci_dev * dev,struct scatterlist * sglist,int nents,int dir)1237 int sba_map_sg(struct pci_dev *dev, struct scatterlist *sglist, int nents, int dir)
1238 {
1239 struct ioc *ioc;
1240 int coalesced, filled = 0;
1241 unsigned long flags;
1242 #ifdef ALLOW_IOV_BYPASS
1243 struct scatterlist *sg;
1244 #endif
1245
1246 DBG_RUN_SG("%s() START %d entries\n", __FUNCTION__, nents);
1247 ioc = GET_IOC(dev);
1248 ASSERT(ioc);
1249
1250 #ifdef ALLOW_IOV_BYPASS
1251 if (dev->dma_mask >= ioc->dma_mask) {
1252 for (sg = sglist ; filled < nents ; filled++, sg++){
1253 sg->dma_length = sg->length;
1254 sg->dma_address = virt_to_phys(sba_sg_address(sg));
1255 }
1256 return filled;
1257 }
1258 #endif
1259 /* Fast path single entry scatterlists. */
1260 if (nents == 1) {
1261 sglist->dma_length = sglist->length;
1262 sglist->dma_address = sba_map_single(dev, sba_sg_address(sglist), sglist->length,
1263 dir);
1264 return 1;
1265 }
1266
1267 spin_lock_irqsave(&ioc->res_lock, flags);
1268
1269 #ifdef ASSERT_PDIR_SANITY
1270 if (sba_check_pdir(ioc,"Check before sba_map_sg()"))
1271 {
1272 sba_dump_sg(ioc, sglist, nents);
1273 panic("Check before sba_map_sg()");
1274 }
1275 #endif
1276
1277 /*
1278 ** First coalesce the chunks and allocate I/O pdir space
1279 **
1280 ** If this is one DMA stream, we can properly map using the
1281 ** correct virtual address associated with each DMA page.
1282 ** w/o this association, we wouldn't have coherent DMA!
1283 ** Access to the virtual address is what forces a two pass algorithm.
1284 */
1285 coalesced = sba_coalesce_chunks(ioc, sglist, nents);
1286
1287 /*
1288 ** Program the I/O Pdir
1289 **
1290 ** map the virtual addresses to the I/O Pdir
1291 ** o dma_address will contain the pdir index
1292 ** o dma_len will contain the number of bytes to map
1293 ** o address contains the virtual address.
1294 */
1295 filled = sba_fill_pdir(ioc, sglist, nents);
1296
1297 #ifdef ASSERT_PDIR_SANITY
1298 if (sba_check_pdir(ioc,"Check after sba_map_sg()"))
1299 {
1300 sba_dump_sg(ioc, sglist, nents);
1301 panic("Check after sba_map_sg()\n");
1302 }
1303 #endif
1304
1305 spin_unlock_irqrestore(&ioc->res_lock, flags);
1306
1307 ASSERT(coalesced == filled);
1308 DBG_RUN_SG("%s() DONE %d mappings\n", __FUNCTION__, filled);
1309
1310 return filled;
1311 }
1312
1313
1314 /**
1315 * sba_unmap_sg - unmap Scatter/Gather list
1316 * @dev: instance of PCI owned by the driver that's asking.
1317 * @sglist: array of buffer/length pairs
1318 * @nents: number of entries in list
1319 * @dir: R/W or both.
1320 *
1321 * See Documentation/DMA-mapping.txt
1322 */
sba_unmap_sg(struct pci_dev * dev,struct scatterlist * sglist,int nents,int dir)1323 void sba_unmap_sg (struct pci_dev *dev, struct scatterlist *sglist, int nents, int dir)
1324 {
1325 struct ioc *ioc;
1326 #ifdef ASSERT_PDIR_SANITY
1327 unsigned long flags;
1328 #endif
1329
1330 DBG_RUN_SG("%s() START %d entries, %p,%x\n",
1331 __FUNCTION__, nents, sba_sg_address(sglist), sglist->length);
1332
1333 ioc = GET_IOC(dev);
1334 ASSERT(ioc);
1335
1336 #ifdef ASSERT_PDIR_SANITY
1337 spin_lock_irqsave(&ioc->res_lock, flags);
1338 sba_check_pdir(ioc,"Check before sba_unmap_sg()");
1339 spin_unlock_irqrestore(&ioc->res_lock, flags);
1340 #endif
1341
1342 while (nents && sglist->dma_length) {
1343
1344 sba_unmap_single(dev, sglist->dma_address, sglist->dma_length, dir);
1345 sglist++;
1346 nents--;
1347 }
1348
1349 DBG_RUN_SG("%s() DONE (nents %d)\n", __FUNCTION__, nents);
1350
1351 #ifdef ASSERT_PDIR_SANITY
1352 spin_lock_irqsave(&ioc->res_lock, flags);
1353 sba_check_pdir(ioc,"Check after sba_unmap_sg()");
1354 spin_unlock_irqrestore(&ioc->res_lock, flags);
1355 #endif
1356
1357 }
1358
1359 /**************************************************************
1360 *
1361 * Initialization and claim
1362 *
1363 ***************************************************************/
1364
1365 static void __init
ioc_iova_init(struct ioc * ioc)1366 ioc_iova_init(struct ioc *ioc)
1367 {
1368 int tcnfg;
1369 int agp_found = 0;
1370 struct pci_dev *device = NULL;
1371 #ifdef FULL_VALID_PDIR
1372 unsigned long index;
1373 #endif
1374
1375 /*
1376 ** Firmware programs the base and size of a "safe IOVA space"
1377 ** (one that doesn't overlap memory or LMMIO space) in the
1378 ** IBASE and IMASK registers.
1379 */
1380 ioc->ibase = READ_REG(ioc->ioc_hpa + IOC_IBASE) & ~0x1UL;
1381 ioc->imask = READ_REG(ioc->ioc_hpa + IOC_IMASK) | 0xFFFFFFFF00000000UL;
1382
1383 ioc->iov_size = ~ioc->imask + 1;
1384
1385 DBG_INIT("%s() hpa %p IOV base 0x%lx mask 0x%lx (%dMB)\n",
1386 __FUNCTION__, ioc->ioc_hpa, ioc->ibase, ioc->imask,
1387 ioc->iov_size >> 20);
1388
1389 switch (iovp_size) {
1390 case 4*1024: tcnfg = 0; break;
1391 case 8*1024: tcnfg = 1; break;
1392 case 16*1024: tcnfg = 2; break;
1393 case 64*1024: tcnfg = 3; break;
1394 default:
1395 panic(PFX "Unsupported IOTLB page size %ldK",
1396 iovp_size >> 10);
1397 break;
1398 }
1399 WRITE_REG(tcnfg, ioc->ioc_hpa + IOC_TCNFG);
1400
1401 ioc->pdir_size = (ioc->iov_size / iovp_size) * PDIR_ENTRY_SIZE;
1402 ioc->pdir_base = (void *) __get_free_pages(GFP_KERNEL,
1403 get_order(ioc->pdir_size));
1404 if (!ioc->pdir_base)
1405 panic(PFX "Couldn't allocate I/O Page Table\n");
1406
1407 memset(ioc->pdir_base, 0, ioc->pdir_size);
1408
1409 DBG_INIT("%s() IOV page size %ldK pdir %p size %x\n", __FUNCTION__,
1410 iovp_size >> 10, ioc->pdir_base, ioc->pdir_size);
1411
1412 ASSERT(ALIGN((unsigned long) ioc->pdir_base, 4*1024) == (unsigned long) ioc->pdir_base);
1413 WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
1414
1415 /*
1416 ** If an AGP device is present, only use half of the IOV space
1417 ** for PCI DMA. Unfortunately we can't know ahead of time
1418 ** whether GART support will actually be used, for now we
1419 ** can just key on an AGP device found in the system.
1420 ** We program the next pdir index after we stop w/ a key for
1421 ** the GART code to handshake on.
1422 */
1423 while ((device = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, device)) != NULL)
1424 agp_found |= pci_find_capability(device, PCI_CAP_ID_AGP);
1425
1426 if (agp_found && reserve_sba_gart) {
1427 printk(KERN_INFO PFX "reserving %dMb of IOVA space at 0x%lx for agpgart\n",
1428 ioc->iov_size/2 >> 20, ioc->ibase + ioc->iov_size/2);
1429 ioc->pdir_size /= 2;
1430 ((u64 *)ioc->pdir_base)[PDIR_INDEX(ioc->iov_size/2)] = ZX1_SBA_IOMMU_COOKIE;
1431 }
1432 #ifdef FULL_VALID_PDIR
1433 /*
1434 ** Check to see if the spill page has been allocated, we don't need more than
1435 ** one across multiple SBAs.
1436 */
1437 if (!prefetch_spill_page) {
1438 char *spill_poison = "SBAIOMMU POISON";
1439 int poison_size = 16;
1440 void *poison_addr, *addr;
1441
1442 addr = (void *)__get_free_pages(GFP_KERNEL, get_order(iovp_size));
1443 if (!addr)
1444 panic(PFX "Couldn't allocate PDIR spill page\n");
1445
1446 poison_addr = addr;
1447 for ( ; (u64) poison_addr < addr + iovp_size; poison_addr += poison_size)
1448 memcpy(poison_addr, spill_poison, poison_size);
1449
1450 prefetch_spill_page = virt_to_phys(addr);
1451
1452 DBG_INIT("%s() prefetch spill addr: 0x%lx\n", __FUNCTION__, prefetch_spill_page);
1453 }
1454 /*
1455 ** Set all the PDIR entries valid w/ the spill page as the target
1456 */
1457 for (index = 0 ; index < (ioc->pdir_size / PDIR_ENTRY_SIZE) ; index++)
1458 ((u64 *)ioc->pdir_base)[index] = (0x80000000000000FF | prefetch_spill_page);
1459 #endif
1460
1461 /* Clear I/O TLB of any possible entries */
1462 WRITE_REG(ioc->ibase | (get_iovp_order(ioc->iov_size) + iovp_shift), ioc->ioc_hpa + IOC_PCOM);
1463 READ_REG(ioc->ioc_hpa + IOC_PCOM);
1464
1465 /* Enable IOVA translation */
1466 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE);
1467 READ_REG(ioc->ioc_hpa + IOC_IBASE);
1468 }
1469
1470 static void __init
ioc_resource_init(struct ioc * ioc)1471 ioc_resource_init(struct ioc *ioc)
1472 {
1473 spin_lock_init(&ioc->res_lock);
1474
1475 /* resource map size dictated by pdir_size */
1476 ioc->res_size = ioc->pdir_size / PDIR_ENTRY_SIZE; /* entries */
1477 ioc->res_size >>= 3; /* convert bit count to byte count */
1478 DBG_INIT("%s() res_size 0x%x\n", __FUNCTION__, ioc->res_size);
1479
1480 ioc->res_map = (char *) __get_free_pages(GFP_KERNEL,
1481 get_order(ioc->res_size));
1482 if (!ioc->res_map)
1483 panic(PFX "Couldn't allocate resource map\n");
1484
1485 memset(ioc->res_map, 0, ioc->res_size);
1486 /* next available IOVP - circular search */
1487 ioc->res_hint = (unsigned long *) ioc->res_map;
1488
1489 #ifdef ASSERT_PDIR_SANITY
1490 /* Mark first bit busy - ie no IOVA 0 */
1491 ioc->res_map[0] = 0x1;
1492 ioc->pdir_base[0] = 0x8000000000000000ULL | ZX1_SBA_IOMMU_COOKIE;
1493 #endif
1494 #ifdef FULL_VALID_PDIR
1495 /* Mark the last resource used so we don't prefetch beyond IOVA space */
1496 ioc->res_map[ioc->res_size - 1] |= 0x80UL; /* res_map is chars */
1497 ioc->pdir_base[(ioc->pdir_size / PDIR_ENTRY_SIZE) - 1] = (0x80000000000000FF
1498 | prefetch_spill_page);
1499 #endif
1500
1501 DBG_INIT("%s() res_map %x %p\n", __FUNCTION__,
1502 ioc->res_size, (void *) ioc->res_map);
1503 }
1504
1505 static void __init
ioc_sac_init(struct ioc * ioc)1506 ioc_sac_init(struct ioc *ioc)
1507 {
1508 struct pci_dev *sac = NULL;
1509 struct pci_controller *controller = NULL;
1510
1511 /*
1512 * pci_alloc_coherent() must return a DMA address which is
1513 * SAC (single address cycle) addressable, so allocate a
1514 * pseudo-device to enforce that.
1515 */
1516 sac = kmalloc(sizeof(*sac), GFP_KERNEL);
1517 if (!sac)
1518 panic(PFX "Couldn't allocate struct pci_dev");
1519 memset(sac, 0, sizeof(*sac));
1520
1521 controller = kmalloc(sizeof(*controller), GFP_KERNEL);
1522 if (!controller)
1523 panic(PFX "Couldn't allocate struct pci_controller");
1524 memset(controller, 0, sizeof(*controller));
1525
1526 controller->iommu = ioc;
1527 sac->sysdata = controller;
1528 sac->dma_mask = 0xFFFFFFFFUL;
1529 ioc->sac_only_dev = sac;
1530 }
1531
1532 static void __init
ioc_zx1_init(struct ioc * ioc)1533 ioc_zx1_init(struct ioc *ioc)
1534 {
1535 if (ioc->rev < 0x20)
1536 panic(PFX "IOC 2.0 or later required for IOMMU support\n");
1537
1538 ioc->dma_mask = 0xFFFFFFFFFFUL;
1539
1540 if (!iovp_shift) {
1541 /* 64k is max iommu page size */
1542 iovp_shift = min(PAGE_SHIFT, 16);
1543 iovp_size = (1 << iovp_shift);
1544 iovp_mask = ~(iovp_size - 1);
1545 }
1546 }
1547
1548 static void __init
ioc_sx1000_init(struct ioc * ioc)1549 ioc_sx1000_init(struct ioc *ioc)
1550 {
1551 if (!iovp_shift) {
1552 iovp_shift = 12; /* 4K for now */
1553 iovp_size = (1 << iovp_shift);
1554 iovp_mask = ~(iovp_size - 1);
1555 }
1556 }
1557
1558 typedef void (initfunc)(struct ioc *);
1559
1560 struct ioc_iommu {
1561 u32 func_id;
1562 char *name;
1563 initfunc *init;
1564 };
1565
1566 static struct ioc_iommu ioc_iommu_info[] __initdata = {
1567 { ZX1_IOC_ID, "zx1", ioc_zx1_init },
1568 { REO_IOC_ID, "REO", ioc_sx1000_init },
1569 { SX1000_IOC_ID, "sx1000", ioc_sx1000_init },
1570 };
1571
1572 static struct ioc * __init
ioc_init(u64 hpa,void * handle)1573 ioc_init(u64 hpa, void *handle)
1574 {
1575 struct ioc *ioc;
1576 struct ioc_iommu *info;
1577
1578 ioc = kmalloc(sizeof(*ioc), GFP_KERNEL);
1579 if (!ioc)
1580 return NULL;
1581
1582 memset(ioc, 0, sizeof(*ioc));
1583
1584 ioc->next = ioc_list;
1585 ioc_list = ioc;
1586
1587 ioc->handle = handle;
1588 ioc->ioc_hpa = ioremap(hpa, 0x1000);
1589
1590 ioc->func_id = READ_REG(ioc->ioc_hpa + IOC_FUNC_ID);
1591 ioc->rev = READ_REG(ioc->ioc_hpa + IOC_FCLASS) & 0xFFUL;
1592 ioc->dma_mask = 0xFFFFFFFFFFFFFFFFUL; /* conservative */
1593
1594 if (iovp_shift) {
1595 iovp_size = (1 << iovp_shift);
1596 iovp_mask = ~(iovp_size - 1);
1597 }
1598
1599 for (info = ioc_iommu_info; info < ioc_iommu_info + ARRAY_SIZE(ioc_iommu_info); info++) {
1600 if (ioc->func_id == info->func_id) {
1601 ioc->name = info->name;
1602 if (info->init)
1603 (info->init)(ioc);
1604 }
1605 }
1606 DBG_INIT("%s: PAGE_SIZE %ldK, iovp_size %ldK\n", __FUNCTION__,
1607 PAGE_SIZE >> 10, iovp_size >> 10);
1608
1609 if (!ioc->name) {
1610 ioc->name = kmalloc(24, GFP_KERNEL);
1611 if (ioc->name)
1612 sprintf((char *) ioc->name, "Unknown (%04x:%04x)",
1613 ioc->func_id & 0xFFFF, (ioc->func_id >> 16) & 0xFFFF);
1614 else
1615 ioc->name = "Unknown";
1616 }
1617
1618 ioc_iova_init(ioc);
1619 ioc_resource_init(ioc);
1620 ioc_sac_init(ioc);
1621
1622 printk(KERN_INFO PFX
1623 "%s %d.%d HPA 0x%lx IOVA space %dMb at 0x%lx\n",
1624 ioc->name, (ioc->rev >> 4) & 0xF, ioc->rev & 0xF,
1625 hpa, ioc->iov_size >> 20, ioc->ibase);
1626
1627 return ioc;
1628 }
1629
1630
1631
1632 /**************************************************************************
1633 **
1634 ** SBA initialization code (HW and SW)
1635 **
1636 ** o identify SBA chip itself
1637 ** o FIXME: initialize DMA hints for reasonable defaults
1638 **
1639 **************************************************************************/
1640
1641 #ifdef CONFIG_PROC_FS
1642 static void *
ioc_start(struct seq_file * s,loff_t * pos)1643 ioc_start(struct seq_file *s, loff_t *pos)
1644 {
1645 struct ioc *ioc;
1646 loff_t n = *pos;
1647
1648 for (ioc = ioc_list; ioc; ioc = ioc->next)
1649 if (!n--)
1650 return ioc;
1651
1652 return NULL;
1653 }
1654
1655 static void *
ioc_next(struct seq_file * s,void * v,loff_t * pos)1656 ioc_next(struct seq_file *s, void *v, loff_t *pos)
1657 {
1658 struct ioc *ioc = v;
1659
1660 ++*pos;
1661 return ioc->next;
1662 }
1663
1664 static void
ioc_stop(struct seq_file * s,void * v)1665 ioc_stop(struct seq_file *s, void *v)
1666 {
1667 }
1668
1669 static int
ioc_show(struct seq_file * s,void * v)1670 ioc_show(struct seq_file *s, void *v)
1671 {
1672 struct ioc *ioc = v;
1673 unsigned long *res_ptr = (unsigned long *)ioc->res_map;
1674 int i, used = 0;
1675
1676 seq_printf(s, "Hewlett Packard %s IOC rev %d.%d\n",
1677 ioc->name, ((ioc->rev >> 4) & 0xF), (ioc->rev & 0xF));
1678 seq_printf(s, "IOVA size : %d MB\n", ioc->iov_size/(1024*1024));
1679 seq_printf(s, "IOVA page size : %ld kb\n", iovp_size/1024);
1680
1681 for (i = 0; i < (ioc->res_size / sizeof(unsigned long)); ++i, ++res_ptr)
1682 used += hweight64(*res_ptr);
1683
1684 seq_printf(s, "PDIR size : %d entries\n", ioc->res_size << 3);
1685 seq_printf(s, "PDIR used : %d entries\n", used);
1686
1687 #ifdef PDIR_SEARCH_TIMING
1688 {
1689 unsigned long i = 0, avg = 0, min, max;
1690 min = max = ioc->avg_search[0];
1691 for (i = 0; i < SBA_SEARCH_SAMPLE; i++) {
1692 avg += ioc->avg_search[i];
1693 if (ioc->avg_search[i] > max) max = ioc->avg_search[i];
1694 if (ioc->avg_search[i] < min) min = ioc->avg_search[i];
1695 }
1696 avg /= SBA_SEARCH_SAMPLE;
1697 seq_printf(s, "Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n",
1698 min, avg, max);
1699 }
1700 #endif
1701 #ifndef ALLOW_IOV_BYPASS
1702 seq_printf(s, "IOVA bypass disabled\n");
1703 #endif
1704 return 0;
1705 }
1706
1707 static struct seq_operations ioc_seq_ops = {
1708 .start = ioc_start,
1709 .next = ioc_next,
1710 .stop = ioc_stop,
1711 .show = ioc_show
1712 };
1713
1714 static int
ioc_open(struct inode * inode,struct file * file)1715 ioc_open(struct inode *inode, struct file *file)
1716 {
1717 return seq_open(file, &ioc_seq_ops);
1718 }
1719
1720 static struct file_operations ioc_fops = {
1721 .open = ioc_open,
1722 .read = seq_read,
1723 .llseek = seq_lseek,
1724 .release = seq_release
1725 };
1726
1727 static void __init
ioc_proc_init(void)1728 ioc_proc_init(void)
1729 {
1730 struct proc_dir_entry *dir, *entry;
1731
1732 dir = proc_mkdir("bus/mckinley", 0);
1733 if (!dir)
1734 return;
1735
1736 entry = create_proc_entry(ioc_list->name, 0, dir);
1737 if (entry)
1738 entry->proc_fops = &ioc_fops;
1739 }
1740 #endif
1741
1742 static void
sba_connect_bus(struct pci_bus * bus)1743 sba_connect_bus(struct pci_bus *bus)
1744 {
1745 acpi_handle handle, parent;
1746 acpi_status status;
1747 struct ioc *ioc;
1748
1749 if (!PCI_CONTROLLER(bus))
1750 panic(PFX "no sysdata on bus %d!\n", bus->number);
1751
1752 if (PCI_CONTROLLER(bus)->iommu)
1753 return;
1754
1755 handle = PCI_CONTROLLER(bus)->acpi_handle;
1756 if (!handle)
1757 return;
1758
1759 /*
1760 * The IOC scope encloses PCI root bridges in the ACPI
1761 * namespace, so work our way out until we find an IOC we
1762 * claimed previously.
1763 */
1764 do {
1765 for (ioc = ioc_list; ioc; ioc = ioc->next)
1766 if (ioc->handle == handle) {
1767 PCI_CONTROLLER(bus)->iommu = ioc;
1768 return;
1769 }
1770
1771 status = acpi_get_parent(handle, &parent);
1772 handle = parent;
1773 } while (ACPI_SUCCESS(status));
1774
1775 printk(KERN_WARNING "No IOC for PCI Bus %04x:%02x in ACPI\n", PCI_SEGMENT(bus), bus->number);
1776 }
1777
1778 extern acpi_status acpi_hp_csr_space (acpi_handle obj, u64 *csr_base, u64 *csr_length);
1779
1780 static int __init
acpi_sba_ioc_add(struct acpi_device * device)1781 acpi_sba_ioc_add(struct acpi_device *device)
1782 {
1783 struct ioc *ioc;
1784 acpi_status status;
1785 u64 hpa, length;
1786 struct acpi_buffer buffer;
1787 struct acpi_device_info *dev_info;
1788
1789 status = acpi_hp_csr_space(device->handle, &hpa, &length);
1790 if (ACPI_FAILURE(status))
1791 return 1;
1792
1793 buffer.length = ACPI_ALLOCATE_LOCAL_BUFFER;
1794 status = acpi_get_object_info(device->handle, &buffer);
1795 if (ACPI_FAILURE(status))
1796 return 1;
1797 dev_info = buffer.pointer;
1798
1799 /*
1800 * For HWP0001, only SBA appears in ACPI namespace. It encloses the PCI
1801 * root bridges, and its CSR space includes the IOC function.
1802 */
1803 if (strncmp("HWP0001", dev_info->hardware_id.value, 7) == 0)
1804 hpa += ZX1_IOC_OFFSET;
1805 ACPI_MEM_FREE(dev_info);
1806
1807 ioc = ioc_init(hpa, device->handle);
1808 if (!ioc)
1809 return 1;
1810
1811 return 0;
1812 }
1813
1814 static struct acpi_driver acpi_sba_ioc_driver = {
1815 .name = "IOC IOMMU Driver",
1816 .ids = "HWP0001,HWP0004",
1817 .ops = {
1818 .add = acpi_sba_ioc_add,
1819 },
1820 };
1821
1822 void __init
sba_init(void)1823 sba_init(void)
1824 {
1825 acpi_bus_register_driver(&acpi_sba_ioc_driver);
1826 if (!ioc_list)
1827 return;
1828
1829 #ifdef CONFIG_PCI
1830 {
1831 struct pci_bus *b = NULL;
1832 pci_for_each_bus(b)
1833 sba_connect_bus(b);
1834 }
1835 #endif
1836
1837 #ifdef CONFIG_PROC_FS
1838 ioc_proc_init();
1839 #endif
1840 }
1841
1842 static int __init
nosbagart(char * str)1843 nosbagart(char *str)
1844 {
1845 reserve_sba_gart = 0;
1846 return 1;
1847 }
1848
1849 int
sba_dma_supported(struct pci_dev * dev,u64 mask)1850 sba_dma_supported (struct pci_dev *dev, u64 mask)
1851 {
1852 /* make sure it's at least 32bit capable */
1853 return ((mask & 0xFFFFFFFFUL) == 0xFFFFFFFFUL);
1854 }
1855
1856 __setup("nosbagart", nosbagart);
1857
1858 static int __init
sba_page_override(char * str)1859 sba_page_override(char *str)
1860 {
1861 unsigned long page_size;
1862
1863 page_size = memparse(str, &str);
1864 switch (page_size) {
1865 case 4096:
1866 case 8192:
1867 case 16384:
1868 case 65536:
1869 iovp_shift = ffs(page_size) - 1;
1870 break;
1871 default:
1872 printk("%s: unknown/unsupported iommu page size %ld\n",
1873 __FUNCTION__, page_size);
1874 }
1875
1876 return 1;
1877 }
1878
1879 __setup("sbapagesize=",sba_page_override);
1880
1881 EXPORT_SYMBOL(sba_init);
1882 EXPORT_SYMBOL(sba_map_single);
1883 EXPORT_SYMBOL(sba_unmap_single);
1884 EXPORT_SYMBOL(sba_map_sg);
1885 EXPORT_SYMBOL(sba_unmap_sg);
1886 EXPORT_SYMBOL(sba_dma_supported);
1887 EXPORT_SYMBOL(sba_alloc_coherent);
1888 EXPORT_SYMBOL(sba_free_coherent);
1889