1 /*
2 * FarSync WAN driver for Linux (2.4.x kernel version)
3 *
4 * Actually sync driver for X.21, V.35 and V.24 on FarSync T-series cards
5 *
6 * Copyright (C) 2001-2004 FarSite Communications Ltd.
7 * www.farsite.co.uk
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 *
14 * Author: R.J.Dunlop <bob.dunlop@farsite.co.uk>
15 * Maintainer: Kevin Curtis <kevin.curtis@farsite.co.uk>
16 */
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/version.h>
21 #include <linux/pci.h>
22 #include <linux/ioport.h>
23 #include <linux/init.h>
24 #include <asm/uaccess.h>
25 #include <linux/if.h>
26 #include <linux/hdlc.h>
27 #include <asm/delay.h>
28 #include <asm/io.h>
29
30 #include "farsync.h"
31
32 /*
33 * Module info
34 */
35 MODULE_AUTHOR("R.J.Dunlop <bob.dunlop@farsite.co.uk>");
36 MODULE_DESCRIPTION("FarSync T-Series WAN driver. FarSite Communications Ltd.");
37 MODULE_PARM(fst_txq_low, "i");
38 MODULE_PARM(fst_txq_high, "i");
39 MODULE_PARM(fst_max_reads, "i");
40 MODULE_PARM(fst_excluded_cards, "i");
41 MODULE_PARM(fst_excluded_list, "0-32i");
42 MODULE_LICENSE("GPL");
43
44 EXPORT_NO_SYMBOLS;
45
46 /* Driver configuration and global parameters
47 * ==========================================
48 */
49
50 /* Number of ports (per card) and cards supported
51 */
52 #define FST_MAX_PORTS 4
53 #define FST_MAX_CARDS 32
54
55 /* Default parameters for the link
56 */
57 #define FST_TX_QUEUE_LEN 100 /* At 8Mbps a longer queue length is
58 * useful, the syncppp module forces
59 * this down assuming a slower line I
60 * guess.
61 */
62 #define FST_TXQ_DEPTH 16 /* This one is for the buffering
63 * of frames on the way down to the card
64 * so that we can keep the card busy
65 * and maximise throughput
66 */
67 #define FST_HIGH_WATER_MARK 12 /* Point at which we flow control
68 * network layer */
69 #define FST_LOW_WATER_MARK 8 /* Point at which we remove flow
70 * control from network layer */
71 #define FST_MAX_MTU 8000 /* Huge but possible */
72 #define FST_DEF_MTU 1500 /* Common sane value */
73
74 #define FST_TX_TIMEOUT (2*HZ)
75
76 #ifdef ARPHRD_RAWHDLC
77 #define ARPHRD_MYTYPE ARPHRD_RAWHDLC /* Raw frames */
78 #else
79 #define ARPHRD_MYTYPE ARPHRD_HDLC /* Cisco-HDLC (keepalives etc) */
80 #endif
81
82 /*
83 * Modules parameters and associated varaibles
84 */
85 int fst_txq_low = FST_LOW_WATER_MARK;
86 int fst_txq_high = FST_HIGH_WATER_MARK;
87 int fst_max_reads = 7;
88 int fst_excluded_cards = 0;
89 int fst_excluded_list[FST_MAX_CARDS];
90
91 /* Card shared memory layout
92 * =========================
93 */
94 #pragma pack(1)
95
96 /* This information is derived in part from the FarSite FarSync Smc.h
97 * file. Unfortunately various name clashes and the non-portability of the
98 * bit field declarations in that file have meant that I have chosen to
99 * recreate the information here.
100 *
101 * The SMC (Shared Memory Configuration) has a version number that is
102 * incremented every time there is a significant change. This number can
103 * be used to check that we have not got out of step with the firmware
104 * contained in the .CDE files.
105 */
106 #define SMC_VERSION 24
107
108 #define FST_MEMSIZE 0x100000 /* Size of card memory (1Mb) */
109
110 #define SMC_BASE 0x00002000L /* Base offset of the shared memory window main
111 * configuration structure */
112 #define BFM_BASE 0x00010000L /* Base offset of the shared memory window DMA
113 * buffers */
114
115 #define LEN_TX_BUFFER 8192 /* Size of packet buffers */
116 #define LEN_RX_BUFFER 8192
117
118 #define LEN_SMALL_TX_BUFFER 256 /* Size of obsolete buffs used for DOS diags */
119 #define LEN_SMALL_RX_BUFFER 256
120
121 #define NUM_TX_BUFFER 2 /* Must be power of 2. Fixed by firmware */
122 #define NUM_RX_BUFFER 8
123
124 /* Interrupt retry time in milliseconds */
125 #define INT_RETRY_TIME 2
126
127 /* The Am186CH/CC processors support a SmartDMA mode using circular pools
128 * of buffer descriptors. The structure is almost identical to that used
129 * in the LANCE Ethernet controllers. Details available as PDF from the
130 * AMD web site: http://www.amd.com/products/epd/processors/\
131 * 2.16bitcont/3.am186cxfa/a21914/21914.pdf
132 */
133 struct txdesc { /* Transmit descriptor */
134 volatile u16 ladr; /* Low order address of packet. This is a
135 * linear address in the Am186 memory space
136 */
137 volatile u8 hadr; /* High order address. Low 4 bits only, high 4
138 * bits must be zero
139 */
140 volatile u8 bits; /* Status and config */
141 volatile u16 bcnt; /* 2s complement of packet size in low 15 bits.
142 * Transmit terminal count interrupt enable in
143 * top bit.
144 */
145 u16 unused; /* Not used in Tx */
146 };
147
148 struct rxdesc { /* Receive descriptor */
149 volatile u16 ladr; /* Low order address of packet */
150 volatile u8 hadr; /* High order address */
151 volatile u8 bits; /* Status and config */
152 volatile u16 bcnt; /* 2s complement of buffer size in low 15 bits.
153 * Receive terminal count interrupt enable in
154 * top bit.
155 */
156 volatile u16 mcnt; /* Message byte count (15 bits) */
157 };
158
159 /* Convert a length into the 15 bit 2's complement */
160 /* #define cnv_bcnt(len) (( ~(len) + 1 ) & 0x7FFF ) */
161 /* Since we need to set the high bit to enable the completion interrupt this
162 * can be made a lot simpler
163 */
164 #define cnv_bcnt(len) (-(len))
165
166 /* Status and config bits for the above */
167 #define DMA_OWN 0x80 /* SmartDMA owns the descriptor */
168 #define TX_STP 0x02 /* Tx: start of packet */
169 #define TX_ENP 0x01 /* Tx: end of packet */
170 #define RX_ERR 0x40 /* Rx: error (OR of next 4 bits) */
171 #define RX_FRAM 0x20 /* Rx: framing error */
172 #define RX_OFLO 0x10 /* Rx: overflow error */
173 #define RX_CRC 0x08 /* Rx: CRC error */
174 #define RX_HBUF 0x04 /* Rx: buffer error */
175 #define RX_STP 0x02 /* Rx: start of packet */
176 #define RX_ENP 0x01 /* Rx: end of packet */
177
178 /* Interrupts from the card are caused by various events which are presented
179 * in a circular buffer as several events may be processed on one physical int
180 */
181 #define MAX_CIRBUFF 32
182
183 struct cirbuff {
184 u8 rdindex; /* read, then increment and wrap */
185 u8 wrindex; /* write, then increment and wrap */
186 u8 evntbuff[MAX_CIRBUFF];
187 };
188
189 /* Interrupt event codes.
190 * Where appropriate the two low order bits indicate the port number
191 */
192 #define CTLA_CHG 0x18 /* Control signal changed */
193 #define CTLB_CHG 0x19
194 #define CTLC_CHG 0x1A
195 #define CTLD_CHG 0x1B
196
197 #define INIT_CPLT 0x20 /* Initialisation complete */
198 #define INIT_FAIL 0x21 /* Initialisation failed */
199
200 #define ABTA_SENT 0x24 /* Abort sent */
201 #define ABTB_SENT 0x25
202 #define ABTC_SENT 0x26
203 #define ABTD_SENT 0x27
204
205 #define TXA_UNDF 0x28 /* Transmission underflow */
206 #define TXB_UNDF 0x29
207 #define TXC_UNDF 0x2A
208 #define TXD_UNDF 0x2B
209
210 #define F56_INT 0x2C
211 #define M32_INT 0x2D
212
213 #define TE1_ALMA 0x30
214
215 /* Port physical configuration. See farsync.h for field values */
216 struct port_cfg {
217 u16 lineInterface; /* Physical interface type */
218 u8 x25op; /* Unused at present */
219 u8 internalClock; /* 1 => internal clock, 0 => external */
220 u8 transparentMode; /* 1 => on, 0 => off */
221 u8 invertClock; /* 0 => normal, 1 => inverted */
222 u8 padBytes[6]; /* Padding */
223 u32 lineSpeed; /* Speed in bps */
224 };
225
226 /* TE1 port physical configuration */
227 struct su_config {
228 u32 dataRate;
229 u8 clocking;
230 u8 framing;
231 u8 structure;
232 u8 interface;
233 u8 coding;
234 u8 lineBuildOut;
235 u8 equalizer;
236 u8 transparentMode;
237 u8 loopMode;
238 u8 range;
239 u8 txBufferMode;
240 u8 rxBufferMode;
241 u8 startingSlot;
242 u8 losThreshold;
243 u8 enableIdleCode;
244 u8 idleCode;
245 u8 spare[44];
246 };
247
248 /* TE1 Status */
249 struct su_status {
250 u32 receiveBufferDelay;
251 u32 framingErrorCount;
252 u32 codeViolationCount;
253 u32 crcErrorCount;
254 u32 lineAttenuation;
255 u8 portStarted;
256 u8 lossOfSignal;
257 u8 receiveRemoteAlarm;
258 u8 alarmIndicationSignal;
259 u8 spare[40];
260 };
261
262 /* Finally sling all the above together into the shared memory structure.
263 * Sorry it's a hodge podge of arrays, structures and unused bits, it's been
264 * evolving under NT for some time so I guess we're stuck with it.
265 * The structure starts at offset SMC_BASE.
266 * See farsync.h for some field values.
267 */
268 struct fst_shared {
269 /* DMA descriptor rings */
270 struct rxdesc rxDescrRing[FST_MAX_PORTS][NUM_RX_BUFFER];
271 struct txdesc txDescrRing[FST_MAX_PORTS][NUM_TX_BUFFER];
272
273 /* Obsolete small buffers */
274 u8 smallRxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_SMALL_RX_BUFFER];
275 u8 smallTxBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_SMALL_TX_BUFFER];
276
277 u8 taskStatus; /* 0x00 => initialising, 0x01 => running,
278 * 0xFF => halted
279 */
280
281 u8 interruptHandshake; /* Set to 0x01 by adapter to signal interrupt,
282 * set to 0xEE by host to acknowledge interrupt
283 */
284
285 u16 smcVersion; /* Must match SMC_VERSION */
286
287 u32 smcFirmwareVersion; /* 0xIIVVRRBB where II = product ID, VV = major
288 * version, RR = revision and BB = build
289 */
290
291 u16 txa_done; /* Obsolete completion flags */
292 u16 rxa_done;
293 u16 txb_done;
294 u16 rxb_done;
295 u16 txc_done;
296 u16 rxc_done;
297 u16 txd_done;
298 u16 rxd_done;
299
300 u16 mailbox[4]; /* Diagnostics mailbox. Not used */
301
302 struct cirbuff interruptEvent; /* interrupt causes */
303
304 u32 v24IpSts[FST_MAX_PORTS]; /* V.24 control input status */
305 u32 v24OpSts[FST_MAX_PORTS]; /* V.24 control output status */
306
307 struct port_cfg portConfig[FST_MAX_PORTS];
308
309 u16 clockStatus[FST_MAX_PORTS]; /* lsb: 0=> present, 1=> absent */
310
311 u16 cableStatus; /* lsb: 0=> present, 1=> absent */
312
313 u16 txDescrIndex[FST_MAX_PORTS]; /* transmit descriptor ring index */
314 u16 rxDescrIndex[FST_MAX_PORTS]; /* receive descriptor ring index */
315
316 u16 portMailbox[FST_MAX_PORTS][2]; /* command, modifier */
317 u16 cardMailbox[4]; /* Not used */
318
319 /* Number of times the card thinks the host has
320 * missed an interrupt by not acknowledging
321 * within 2mS (I guess NT has problems)
322 */
323 u32 interruptRetryCount;
324
325 /* Driver private data used as an ID. We'll not
326 * use this as I'd rather keep such things
327 * in main memory rather than on the PCI bus
328 */
329 u32 portHandle[FST_MAX_PORTS];
330
331 /* Count of Tx underflows for stats */
332 u32 transmitBufferUnderflow[FST_MAX_PORTS];
333
334 /* Debounced V.24 control input status */
335 u32 v24DebouncedSts[FST_MAX_PORTS];
336
337 /* Adapter debounce timers. Don't touch */
338 u32 ctsTimer[FST_MAX_PORTS];
339 u32 ctsTimerRun[FST_MAX_PORTS];
340 u32 dcdTimer[FST_MAX_PORTS];
341 u32 dcdTimerRun[FST_MAX_PORTS];
342
343 u32 numberOfPorts; /* Number of ports detected at startup */
344
345 u16 _reserved[64];
346
347 u16 cardMode; /* Bit-mask to enable features:
348 * Bit 0: 1 enables LED identify mode
349 */
350
351 u16 portScheduleOffset;
352
353 struct su_config suConfig; /* TE1 Bits */
354 struct su_status suStatus;
355
356 u32 endOfSmcSignature; /* endOfSmcSignature MUST be the last member of
357 * the structure and marks the end of shared
358 * memory. Adapter code initializes it as
359 * END_SIG.
360 */
361 };
362
363 /* endOfSmcSignature value */
364 #define END_SIG 0x12345678
365
366 /* Mailbox values. (portMailbox) */
367 #define NOP 0 /* No operation */
368 #define ACK 1 /* Positive acknowledgement to PC driver */
369 #define NAK 2 /* Negative acknowledgement to PC driver */
370 #define STARTPORT 3 /* Start an HDLC port */
371 #define STOPPORT 4 /* Stop an HDLC port */
372 #define ABORTTX 5 /* Abort the transmitter for a port */
373 #define SETV24O 6 /* Set V24 outputs */
374
375 /* PLX Chip Register Offsets */
376 #define CNTRL_9052 0x50 /* Control Register */
377 #define CNTRL_9054 0x6c /* Control Register */
378
379 #define INTCSR_9052 0x4c /* Interrupt control/status register */
380 #define INTCSR_9054 0x68 /* Interrupt control/status register */
381
382 /* 9054 DMA Registers */
383 /*
384 * Note that we will be using DMA Channel 0 for copying rx data
385 * and Channel 1 for copying tx data
386 */
387 #define DMAMODE0 0x80
388 #define DMAPADR0 0x84
389 #define DMALADR0 0x88
390 #define DMASIZ0 0x8c
391 #define DMADPR0 0x90
392 #define DMAMODE1 0x94
393 #define DMAPADR1 0x98
394 #define DMALADR1 0x9c
395 #define DMASIZ1 0xa0
396 #define DMADPR1 0xa4
397 #define DMACSR0 0xa8
398 #define DMACSR1 0xa9
399 #define DMAARB 0xac
400 #define DMATHR 0xb0
401 #define DMADAC0 0xb4
402 #define DMADAC1 0xb8
403 #define DMAMARBR 0xac
404
405 #define FST_MIN_DMA_LEN 64
406 #define FST_RX_DMA_INT 0x01
407 #define FST_TX_DMA_INT 0x02
408 #define FST_CARD_INT 0x04
409
410 /* Larger buffers are positioned in memory at offset BFM_BASE */
411 struct buf_window {
412 u8 txBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_TX_BUFFER];
413 u8 rxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_RX_BUFFER];
414 };
415
416 /* Calculate offset of a buffer object within the shared memory window */
417 #define BUF_OFFSET(X) ((unsigned int)&(((struct buf_window *)BFM_BASE)->X))
418
419 #pragma pack()
420
421 /* Device driver private information
422 * =================================
423 */
424 /* Per port (line or channel) information
425 */
426 struct fst_port_info {
427 hdlc_device hdlc; /* HDLC device struct - must be first */
428 struct fst_card_info *card; /* Card we're associated with */
429 int index; /* Port index on the card */
430 int hwif; /* Line hardware (lineInterface copy) */
431 int run; /* Port is running */
432 int mode; /* Normal or FarSync raw */
433 int rxpos; /* Next Rx buffer to use */
434 int txpos; /* Next Tx buffer to use */
435 int txipos; /* Next Tx buffer to check for free */
436 int start; /* Indication of start/stop to network */
437 /*
438 * A sixteen entry transmit queue
439 */
440 int txqs; /* index to get next buffer to tx */
441 int txqe; /* index to queue next packet */
442 struct sk_buff *txq[FST_TXQ_DEPTH]; /* The queue */
443 int rxqdepth;
444 };
445
446 /* Per card information
447 */
448 struct fst_card_info {
449 char *mem; /* Card memory mapped to kernel space */
450 char *ctlmem; /* Control memory for PCI cards */
451 unsigned int phys_mem; /* Physical memory window address */
452 unsigned int phys_ctlmem; /* Physical control memory address */
453 unsigned int irq; /* Interrupt request line number */
454 unsigned int nports; /* Number of serial ports */
455 unsigned int type; /* Type index of card */
456 unsigned int state; /* State of card */
457 spinlock_t card_lock; /* Lock for SMP access */
458 unsigned short pci_conf; /* PCI card config in I/O space */
459 /* Per port info */
460 struct fst_port_info ports[FST_MAX_PORTS];
461 struct pci_dev *device; /* Information about the pci device */
462 int card_no; /* Inst of the card on the system */
463 int family; /* TxP or TxU */
464 int dmarx_in_progress;
465 int dmatx_in_progress;
466 unsigned long int_count;
467 unsigned long int_time_ave;
468 void *rx_dma_handle_host;
469 dma_addr_t rx_dma_handle_card;
470 void *tx_dma_handle_host;
471 dma_addr_t tx_dma_handle_card;
472 struct sk_buff *dma_skb_rx;
473 struct fst_port_info *dma_port_rx;
474 struct fst_port_info *dma_port_tx;
475 int dma_len_rx;
476 int dma_len_tx;
477 int dma_txpos;
478 int dma_rxpos;
479 };
480
481 /* Convert an HDLC device pointer into a port info pointer and similar */
482 #define hdlc_to_port(H) ((struct fst_port_info *)(H))
483 #define dev_to_port(D) hdlc_to_port(dev_to_hdlc(D))
484 #define port_to_dev(P) hdlc_to_dev(&(P)->hdlc)
485
486 /*
487 * Shared memory window access macros
488 *
489 * We have a nice memory based structure above, which could be directly
490 * mapped on i386 but might not work on other architectures unless we use
491 * the readb,w,l and writeb,w,l macros. Unfortunately these macros take
492 * physical offsets so we have to convert. The only saving grace is that
493 * this should all collapse back to a simple indirection eventually.
494 */
495 #define WIN_OFFSET(X) ((long)&(((struct fst_shared *)SMC_BASE)->X))
496
497 #define FST_RDB(C,E) readb ((C)->mem + WIN_OFFSET(E))
498 #define FST_RDW(C,E) readw ((C)->mem + WIN_OFFSET(E))
499 #define FST_RDL(C,E) readl ((C)->mem + WIN_OFFSET(E))
500
501 #define FST_WRB(C,E,B) writeb ((B), (C)->mem + WIN_OFFSET(E))
502 #define FST_WRW(C,E,W) writew ((W), (C)->mem + WIN_OFFSET(E))
503 #define FST_WRL(C,E,L) writel ((L), (C)->mem + WIN_OFFSET(E))
504
505 /*
506 * Debug support
507 */
508 #if FST_DEBUG
509
510 static int fst_debug_mask = { FST_DEBUG };
511
512 /* Most common debug activity is to print something if the corresponding bit
513 * is set in the debug mask. Note: this uses a non-ANSI extension in GCC to
514 * support variable numbers of macro parameters. The inverted if prevents us
515 * eating someone else's else clause.
516 */
517 #define dbg(F,fmt,A...) if ( ! ( fst_debug_mask & (F))) \
518 ; \
519 else \
520 printk ( KERN_DEBUG FST_NAME ": " fmt, ## A )
521
522 #else
523 #define dbg(X...) /* NOP */
524 #endif
525
526 /* Printing short cuts
527 */
528 #define printk_err(fmt,A...) printk ( KERN_ERR FST_NAME ": " fmt, ## A )
529 #define printk_warn(fmt,A...) printk ( KERN_WARNING FST_NAME ": " fmt, ## A )
530 #define printk_info(fmt,A...) printk ( KERN_INFO FST_NAME ": " fmt, ## A )
531
532 /*
533 * PCI ID lookup table
534 */
535 static struct pci_device_id fst_pci_dev_id[] __devinitdata = {
536 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2P, PCI_ANY_ID,
537 PCI_ANY_ID, 0, 0, FST_TYPE_T2P},
538
539 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4P, PCI_ANY_ID,
540 PCI_ANY_ID, 0, 0, FST_TYPE_T4P},
541
542 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T1U, PCI_ANY_ID,
543 PCI_ANY_ID, 0, 0, FST_TYPE_T1U},
544
545 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2U, PCI_ANY_ID,
546 PCI_ANY_ID, 0, 0, FST_TYPE_T2U},
547
548 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4U, PCI_ANY_ID,
549 PCI_ANY_ID, 0, 0, FST_TYPE_T4U},
550
551 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1, PCI_ANY_ID,
552 PCI_ANY_ID, 0, 0, FST_TYPE_TE1},
553
554 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1C, PCI_ANY_ID,
555 PCI_ANY_ID, 0, 0, FST_TYPE_TE1},
556 {0,} /* End */
557 };
558
559 MODULE_DEVICE_TABLE(pci, fst_pci_dev_id);
560
561 /*
562 * Device Driver Work Queues
563 *
564 * So that we don't spend too much time processing events in the
565 * Interrupt Service routine, we will declare a work queue per Card
566 * and make the ISR schedule a task in the queue for later execution.
567 */
568
569 static void do_bottom_half_tx(struct fst_card_info *card);
570 static void do_bottom_half_rx(struct fst_card_info *card);
571 static void fst_process_tx_work_q(unsigned long work_q);
572 static void fst_process_int_work_q(unsigned long work_q);
573
574 DECLARE_TASKLET(fst_tx_task, fst_process_tx_work_q, 0);
575 DECLARE_TASKLET(fst_int_task, fst_process_int_work_q, 0);
576
577 struct fst_card_info *fst_card_array[FST_MAX_CARDS];
578 spinlock_t fst_work_q_lock;
579 u64 fst_work_txq;
580 u64 fst_work_intq;
581
582 static void
fst_q_work_item(u64 * queue,int card_index)583 fst_q_work_item(u64 * queue, int card_index)
584 {
585 unsigned long flags;
586 u64 mask;
587
588 /*
589 * Grab the queue exclusively
590 */
591 spin_lock_irqsave(&fst_work_q_lock, flags);
592
593 /*
594 * Making an entry in the queue is simply a matter of setting
595 * a bit for the card indicating that there is work to do in the
596 * bottom half for the card. Note the limitation of 64 cards.
597 * That ought to be enough
598 */
599 mask = 1 << card_index;
600 *queue |= mask;
601 spin_unlock_irqrestore(&fst_work_q_lock, flags);
602 }
603
604 static void
fst_process_tx_work_q(unsigned long work_q)605 fst_process_tx_work_q(unsigned long work_q)
606 {
607 unsigned long flags;
608 u64 work_txq;
609 int i;
610
611 /*
612 * Grab the queue exclusively
613 */
614 dbg(DBG_TX, "fst_process_tx_work_q\n");
615 spin_lock_irqsave(&fst_work_q_lock, flags);
616 work_txq = fst_work_txq;
617 fst_work_txq = 0;
618 spin_unlock_irqrestore(&fst_work_q_lock, flags);
619
620 /*
621 * Call the bottom half for each card with work waiting
622 */
623 for (i = 0; i < FST_MAX_CARDS; i++) {
624 if (work_txq & 0x01) {
625 if (fst_card_array[i] != NULL) {
626 dbg(DBG_TX, "Calling tx bh for card %d\n", i);
627 do_bottom_half_tx(fst_card_array[i]);
628 }
629 }
630 work_txq = work_txq >> 1;
631 }
632 }
633
634 static void
fst_process_int_work_q(unsigned long work_q)635 fst_process_int_work_q(unsigned long work_q)
636 {
637 unsigned long flags;
638 u64 work_intq;
639 int i;
640
641 /*
642 * Grab the queue exclusively
643 */
644 dbg(DBG_INTR, "fst_process_int_work_q\n");
645 spin_lock_irqsave(&fst_work_q_lock, flags);
646 work_intq = fst_work_intq;
647 fst_work_intq = 0;
648 spin_unlock_irqrestore(&fst_work_q_lock, flags);
649
650 /*
651 * Call the bottom half for each card with work waiting
652 */
653 for (i = 0; i < FST_MAX_CARDS; i++) {
654 if (work_intq & 0x01) {
655 if (fst_card_array[i] != NULL) {
656 dbg(DBG_INTR,
657 "Calling rx & tx bh for card %d\n", i);
658 do_bottom_half_rx(fst_card_array[i]);
659 do_bottom_half_tx(fst_card_array[i]);
660 }
661 }
662 work_intq = work_intq >> 1;
663 }
664 }
665
666 /* Card control functions
667 * ======================
668 */
669 /* Place the processor in reset state
670 *
671 * Used to be a simple write to card control space but a glitch in the latest
672 * AMD Am186CH processor means that we now have to do it by asserting and de-
673 * asserting the PLX chip PCI Adapter Software Reset. Bit 30 in CNTRL register
674 * at offset 9052_CNTRL. Note the updates for the TXU.
675 */
676 static inline void
fst_cpureset(struct fst_card_info * card)677 fst_cpureset(struct fst_card_info *card)
678 {
679 unsigned char interrupt_line_register;
680 unsigned long j = jiffies + 1;
681 unsigned int regval;
682
683 if (card->family == FST_FAMILY_TXU) {
684 if (pci_read_config_byte
685 (card->device, PCI_INTERRUPT_LINE, &interrupt_line_register)) {
686 dbg(DBG_ASS,
687 "Error in reading interrupt line register\n");
688 }
689 /*
690 * Assert PLX software reset and Am186 hardware reset
691 * and then deassert the PLX software reset but 186 still in reset
692 */
693 outw(0x440f, card->pci_conf + CNTRL_9054 + 2);
694 outw(0x040f, card->pci_conf + CNTRL_9054 + 2);
695 /*
696 * We are delaying here to allow the 9054 to reset itself
697 */
698 j = jiffies + 1;
699 while (jiffies < j)
700 /* Do nothing */ ;
701 outw(0x240f, card->pci_conf + CNTRL_9054 + 2);
702 /*
703 * We are delaying here to allow the 9054 to reload its eeprom
704 */
705 j = jiffies + 1;
706 while (jiffies < j)
707 /* Do nothing */ ;
708 outw(0x040f, card->pci_conf + CNTRL_9054 + 2);
709
710 if (pci_write_config_byte
711 (card->device, PCI_INTERRUPT_LINE, interrupt_line_register)) {
712 dbg(DBG_ASS,
713 "Error in writing interrupt line register\n");
714 }
715
716 } else {
717 regval = inl(card->pci_conf + CNTRL_9052);
718
719 outl(regval | 0x40000000, card->pci_conf + CNTRL_9052);
720 outl(regval & ~0x40000000, card->pci_conf + CNTRL_9052);
721 }
722 }
723
724 /* Release the processor from reset
725 */
726 static inline void
fst_cpurelease(struct fst_card_info * card)727 fst_cpurelease(struct fst_card_info *card)
728 {
729 if (card->family == FST_FAMILY_TXU) {
730 /*
731 * Force posted writes to complete
732 */
733 (void) readb(card->mem);
734
735 /*
736 * Release LRESET DO = 1
737 * Then release Local Hold, DO = 1
738 */
739 outw(0x040e, card->pci_conf + CNTRL_9054 + 2);
740 outw(0x040f, card->pci_conf + CNTRL_9054 + 2);
741 } else {
742 (void) readb(card->ctlmem);
743 }
744 }
745
746 /* Clear the cards interrupt flag
747 */
748 static inline void
fst_clear_intr(struct fst_card_info * card)749 fst_clear_intr(struct fst_card_info *card)
750 {
751 if (card->family == FST_FAMILY_TXU) {
752 (void) readb(card->ctlmem);
753 } else {
754 /* Poke the appropriate PLX chip register (same as enabling interrupts)
755 */
756 outw(0x0543, card->pci_conf + INTCSR_9052);
757 }
758 }
759
760 /* Enable card interrupts
761 */
762 static inline void
fst_enable_intr(struct fst_card_info * card)763 fst_enable_intr(struct fst_card_info *card)
764 {
765 if (card->family == FST_FAMILY_TXU) {
766 outl(0x0f0c0900, card->pci_conf + INTCSR_9054);
767 } else {
768 outw(0x0543, card->pci_conf + INTCSR_9052);
769 }
770 }
771
772 /* Disable card interrupts
773 */
774 static inline void
fst_disable_intr(struct fst_card_info * card)775 fst_disable_intr(struct fst_card_info *card)
776 {
777 if (card->family == FST_FAMILY_TXU) {
778 outl(0x00000000, card->pci_conf + INTCSR_9054);
779 } else {
780 outw(0x0000, card->pci_conf + INTCSR_9052);
781 }
782 }
783
784 /* Process the result of trying to pass a recieved frame up the stack
785 */
786 static void
fst_process_rx_status(int rx_status,char * name)787 fst_process_rx_status(int rx_status, char *name)
788 {
789 switch (rx_status) {
790 case NET_RX_SUCCESS:
791 {
792 /*
793 * Nothing to do here
794 */
795 break;
796 }
797
798 case NET_RX_CN_LOW:
799 {
800 dbg(DBG_ASS, "%s: Receive Low Congestion\n", name);
801 break;
802 }
803
804 case NET_RX_CN_MOD:
805 {
806 dbg(DBG_ASS, "%s: Receive Moderate Congestion\n", name);
807 break;
808 }
809
810 case NET_RX_CN_HIGH:
811 {
812 dbg(DBG_ASS, "%s: Receive High Congestion\n", name);
813 break;
814 }
815
816 case NET_RX_DROP:
817 {
818 dbg(DBG_ASS, "%s: Received packet dropped\n", name);
819 break;
820 }
821 }
822 }
823
824 /* Initilaise DMA for PLX 9054
825 */
826 static inline void
fst_init_dma(struct fst_card_info * card)827 fst_init_dma(struct fst_card_info *card)
828 {
829 /*
830 * This is only required for the PLX 9054
831 */
832 if (card->family == FST_FAMILY_TXU) {
833 pci_set_master(card->device);
834 outl(0x00020441, card->pci_conf + DMAMODE0);
835 outl(0x00020441, card->pci_conf + DMAMODE1);
836 outl(0x0, card->pci_conf + DMATHR);
837 }
838 }
839
840 /* Tx dma complete interrupt
841 */
842 static void
fst_tx_dma_complete(struct fst_card_info * card,struct fst_port_info * port,int len,int txpos)843 fst_tx_dma_complete(struct fst_card_info *card, struct fst_port_info *port,
844 int len, int txpos)
845 {
846 /*
847 * Everything is now set, just tell the card to go
848 */
849 dbg(DBG_TX, "fst_tx_dma_complete\n");
850 FST_WRB(card, txDescrRing[port->index][txpos].bits,
851 DMA_OWN | TX_STP | TX_ENP);
852 port->hdlc.stats.tx_packets++;
853 port->hdlc.stats.tx_bytes += len;
854 port_to_dev(port)->trans_start = jiffies;
855 }
856
857 /* Rx dma complete interrupt
858 */
859 static void
fst_rx_dma_complete(struct fst_card_info * card,struct fst_port_info * port,int len,struct sk_buff * skb,int rxp)860 fst_rx_dma_complete(struct fst_card_info *card, struct fst_port_info *port,
861 int len, struct sk_buff *skb, int rxp)
862 {
863
864 int pi;
865 int rx_status;
866
867 dbg(DBG_TX, "fst_rx_dma_complete\n");
868 pi = port->index;
869 memcpy(skb_put(skb, len), card->rx_dma_handle_host, len);
870
871 /* Reset buffer descriptor */
872 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
873
874 /* Update stats */
875 port->hdlc.stats.rx_packets++;
876 port->hdlc.stats.rx_bytes += len;
877
878 /* Push upstream */
879 dbg(DBG_RX, "Pushing the frame up the stack\n");
880 skb->mac.raw = skb->data;
881 skb->dev = hdlc_to_dev(&port->hdlc);
882 if (port->mode == FST_RAW) {
883 /*
884 * Mark it for our own raw sockets interface
885 */
886 skb->protocol = htons(ETH_P_CUST);
887 skb->pkt_type = PACKET_HOST;
888 } else {
889 skb->protocol = hdlc_type_trans(skb, skb->dev);
890 }
891 rx_status = netif_rx(skb);
892 fst_process_rx_status(rx_status, port_to_dev(port)->name);
893 if (rx_status == NET_RX_DROP)
894 port->hdlc.stats.rx_dropped++;
895 port_to_dev(port)->last_rx = jiffies;
896 }
897
898 /*
899 * Receive a frame through the DMA
900 */
901 static inline void
fst_rx_dma(struct fst_card_info * card,unsigned char * skb,unsigned char * mem,int len)902 fst_rx_dma(struct fst_card_info *card, unsigned char *skb,
903 unsigned char *mem, int len)
904 {
905 /*
906 * This routine will setup the DMA and start it
907 */
908
909 dbg(DBG_RX, "In fst_rx_dma %p %p %d\n", skb, mem, len);
910 if (card->dmarx_in_progress) {
911 dbg(DBG_ASS, "In fst_rx_dma while dma in progress\n");
912 }
913
914 outl((unsigned long) skb, card->pci_conf + DMAPADR0); /* Copy to here */
915 outl((unsigned long) mem, card->pci_conf + DMALADR0); /* from here */
916 outl(len, card->pci_conf + DMASIZ0); /* for this length */
917 outl(0x00000000c, card->pci_conf + DMADPR0); /* In this direction */
918
919 /*
920 * We use the dmarx_in_progress flag to flag the channel as busy
921 */
922 card->dmarx_in_progress = 1;
923 outb(0x03, card->pci_conf + DMACSR0); /* Start the transfer */
924 }
925
926 /*
927 * Send a frame through the DMA
928 */
929 static inline void
fst_tx_dma(struct fst_card_info * card,unsigned char * skb,unsigned char * mem,int len)930 fst_tx_dma(struct fst_card_info *card, unsigned char *skb,
931 unsigned char *mem, int len)
932 {
933 /*
934 * This routine will setup the DMA and start it.
935 */
936
937 dbg(DBG_TX, "In fst_tx_dma %p %p %d\n", skb, mem, len);
938 if (card->dmatx_in_progress) {
939 dbg(DBG_ASS, "In fst_tx_dma while dma in progress\n");
940 }
941
942 outl((unsigned long) skb, card->pci_conf + DMAPADR1); /* Copy from here */
943 outl((unsigned long) mem, card->pci_conf + DMALADR1); /* to here */
944 outl(len, card->pci_conf + DMASIZ1); /* for this length */
945 outl(0x000000004, card->pci_conf + DMADPR1); /* In this direction */
946
947 /*
948 * We use the dmatx_in_progress to flag the channel as busy
949 */
950 card->dmatx_in_progress = 1;
951 outb(0x03, card->pci_conf + DMACSR1); /* Start the transfer */
952 }
953
954 /* Issue a Mailbox command for a port.
955 * Note we issue them on a fire and forget basis, not expecting to see an
956 * error and not waiting for completion.
957 */
958 static void
fst_issue_cmd(struct fst_port_info * port,unsigned short cmd)959 fst_issue_cmd(struct fst_port_info *port, unsigned short cmd)
960 {
961 struct fst_card_info *card;
962 unsigned short mbval;
963 unsigned long flags;
964 int safety;
965
966 card = port->card;
967 spin_lock_irqsave(&card->card_lock, flags);
968 mbval = FST_RDW(card, portMailbox[port->index][0]);
969
970 safety = 0;
971 /* Wait for any previous command to complete */
972 while (mbval > NAK) {
973 spin_unlock_irqrestore(&card->card_lock, flags);
974 schedule_timeout(1);
975 spin_lock_irqsave(&card->card_lock, flags);
976
977 if (++safety > 2000) {
978 printk_err("Mailbox safety timeout\n");
979 break;
980 }
981
982 mbval = FST_RDW(card, portMailbox[port->index][0]);
983 }
984 if (safety > 0) {
985 dbg(DBG_CMD, "Mailbox clear after %d jiffies\n", safety);
986 }
987 if (mbval == NAK) {
988 dbg(DBG_CMD, "issue_cmd: previous command was NAK'd\n");
989 }
990
991 FST_WRW(card, portMailbox[port->index][0], cmd);
992
993 if (cmd == ABORTTX || cmd == STARTPORT) {
994 port->txpos = 0;
995 port->txipos = 0;
996 port->start = 0;
997 }
998
999 spin_unlock_irqrestore(&card->card_lock, flags);
1000 }
1001
1002 /* Port output signals control
1003 */
1004 static inline void
fst_op_raise(struct fst_port_info * port,unsigned int outputs)1005 fst_op_raise(struct fst_port_info *port, unsigned int outputs)
1006 {
1007 outputs |= FST_RDL(port->card, v24OpSts[port->index]);
1008 FST_WRL(port->card, v24OpSts[port->index], outputs);
1009
1010 if (port->run)
1011 fst_issue_cmd(port, SETV24O);
1012 }
1013
1014 static inline void
fst_op_lower(struct fst_port_info * port,unsigned int outputs)1015 fst_op_lower(struct fst_port_info *port, unsigned int outputs)
1016 {
1017 outputs = ~outputs & FST_RDL(port->card, v24OpSts[port->index]);
1018 FST_WRL(port->card, v24OpSts[port->index], outputs);
1019
1020 if (port->run)
1021 fst_issue_cmd(port, SETV24O);
1022 }
1023
1024 /*
1025 * Setup port Rx buffers
1026 */
1027 static void
fst_rx_config(struct fst_port_info * port)1028 fst_rx_config(struct fst_port_info *port)
1029 {
1030 int i;
1031 int pi;
1032 unsigned int offset;
1033 unsigned long flags;
1034 struct fst_card_info *card;
1035
1036 pi = port->index;
1037 card = port->card;
1038 spin_lock_irqsave(&card->card_lock, flags);
1039 for (i = 0; i < NUM_RX_BUFFER; i++) {
1040 offset = BUF_OFFSET(rxBuffer[pi][i][0]);
1041
1042 FST_WRW(card, rxDescrRing[pi][i].ladr, (u16) offset);
1043 FST_WRB(card, rxDescrRing[pi][i].hadr, (u8) (offset >> 16));
1044 FST_WRW(card, rxDescrRing[pi][i].bcnt, cnv_bcnt(LEN_RX_BUFFER));
1045 FST_WRW(card, rxDescrRing[pi][i].mcnt, LEN_RX_BUFFER);
1046 FST_WRB(card, rxDescrRing[pi][i].bits, DMA_OWN);
1047 }
1048 port->rxpos = 0;
1049 spin_unlock_irqrestore(&card->card_lock, flags);
1050 }
1051
1052 /*
1053 * Setup port Tx buffers
1054 */
1055 static void
fst_tx_config(struct fst_port_info * port)1056 fst_tx_config(struct fst_port_info *port)
1057 {
1058 int i;
1059 int pi;
1060 unsigned int offset;
1061 unsigned long flags;
1062 struct fst_card_info *card;
1063
1064 pi = port->index;
1065 card = port->card;
1066 spin_lock_irqsave(&card->card_lock, flags);
1067 for (i = 0; i < NUM_TX_BUFFER; i++) {
1068 offset = BUF_OFFSET(txBuffer[pi][i][0]);
1069
1070 FST_WRW(card, txDescrRing[pi][i].ladr, (u16) offset);
1071 FST_WRB(card, txDescrRing[pi][i].hadr, (u8) (offset >> 16));
1072 FST_WRW(card, txDescrRing[pi][i].bcnt, 0);
1073 FST_WRB(card, txDescrRing[pi][i].bits, 0);
1074 }
1075 port->txpos = 0;
1076 port->txipos = 0;
1077 port->start = 0;
1078 spin_unlock_irqrestore(&card->card_lock, flags);
1079 }
1080
1081 /* TE1 Alarm change interrupt event
1082 */
1083 static void
fst_intr_te1_alarm(struct fst_card_info * card,struct fst_port_info * port)1084 fst_intr_te1_alarm(struct fst_card_info *card, struct fst_port_info *port)
1085 {
1086 u8 los;
1087 u8 rra;
1088 u8 ais;
1089
1090 los = FST_RDB(card, suStatus.lossOfSignal);
1091 rra = FST_RDB(card, suStatus.receiveRemoteAlarm);
1092 ais = FST_RDB(card, suStatus.alarmIndicationSignal);
1093
1094 if (los) {
1095 /*
1096 * Lost the link
1097 */
1098 if (netif_carrier_ok(port_to_dev(port))) {
1099 dbg(DBG_INTR, "Net carrier off\n");
1100 netif_carrier_off(port_to_dev(port));
1101 }
1102 } else {
1103 /*
1104 * Link available
1105 */
1106 if (!netif_carrier_ok(port_to_dev(port))) {
1107 dbg(DBG_INTR, "Net carrier on\n");
1108 netif_carrier_on(port_to_dev(port));
1109 }
1110 }
1111
1112 if (los)
1113 dbg(DBG_INTR, "Assert LOS Alarm\n");
1114 else
1115 dbg(DBG_INTR, "De-assert LOS Alarm\n");
1116 if (rra)
1117 dbg(DBG_INTR, "Assert RRA Alarm\n");
1118 else
1119 dbg(DBG_INTR, "De-assert RRA Alarm\n");
1120
1121 if (ais)
1122 dbg(DBG_INTR, "Assert AIS Alarm\n");
1123 else
1124 dbg(DBG_INTR, "De-assert AIS Alarm\n");
1125 }
1126
1127 /* Control signal change interrupt event
1128 */
1129 static void
fst_intr_ctlchg(struct fst_card_info * card,struct fst_port_info * port)1130 fst_intr_ctlchg(struct fst_card_info *card, struct fst_port_info *port)
1131 {
1132 int signals;
1133
1134 signals = FST_RDL(card, v24DebouncedSts[port->index]);
1135
1136 if (signals & (((port->hwif == X21) || (port->hwif == X21D))
1137 ? IPSTS_INDICATE : IPSTS_DCD)) {
1138 if (!netif_carrier_ok(port_to_dev(port))) {
1139 dbg(DBG_INTR, "DCD active\n");
1140 netif_carrier_on(port_to_dev(port));
1141 }
1142 } else {
1143 if (netif_carrier_ok(port_to_dev(port))) {
1144 dbg(DBG_INTR, "DCD lost\n");
1145 netif_carrier_off(port_to_dev(port));
1146 }
1147 }
1148 }
1149
1150 /* Log Rx Errors
1151 */
1152 static void
fst_log_rx_error(struct fst_card_info * card,struct fst_port_info * port,unsigned char dmabits,int rxp,unsigned short len)1153 fst_log_rx_error(struct fst_card_info *card, struct fst_port_info *port,
1154 unsigned char dmabits, int rxp, unsigned short len)
1155 {
1156 /*
1157 * Increment the appropriate error counter
1158 */
1159 port->hdlc.stats.rx_errors++;
1160 if (dmabits & RX_OFLO) {
1161 port->hdlc.stats.rx_fifo_errors++;
1162 dbg(DBG_ASS, "Rx fifo error on card %d port %d buffer %d\n",
1163 card->card_no, port->index, rxp);
1164 }
1165 if (dmabits & RX_CRC) {
1166 port->hdlc.stats.rx_crc_errors++;
1167 dbg(DBG_ASS, "Rx crc error on card %d port %d\n",
1168 card->card_no, port->index);
1169 }
1170 if (dmabits & RX_FRAM) {
1171 port->hdlc.stats.rx_frame_errors++;
1172 dbg(DBG_ASS, "Rx frame error on card %d port %d\n",
1173 card->card_no, port->index);
1174 }
1175 if (dmabits == (RX_STP | RX_ENP)) {
1176 port->hdlc.stats.rx_length_errors++;
1177 dbg(DBG_ASS, "Rx length error (%d) on card %d port %d\n",
1178 len, card->card_no, port->index);
1179 }
1180 }
1181
1182 /* Rx Error Recovery
1183 */
1184 static void
fst_recover_rx_error(struct fst_card_info * card,struct fst_port_info * port,unsigned char dmabits,int rxp,unsigned short len)1185 fst_recover_rx_error(struct fst_card_info *card, struct fst_port_info *port,
1186 unsigned char dmabits, int rxp, unsigned short len)
1187 {
1188 int i;
1189 int pi;
1190
1191 pi = port->index;
1192 /*
1193 * Discard buffer descriptors until we see the start of the
1194 * next frame. Note that for long frames this could be in
1195 * a subsequent interrupt.
1196 */
1197 i = 0;
1198 while ((dmabits & (DMA_OWN | RX_STP)) == 0) {
1199 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1200 rxp = (rxp+1) % NUM_RX_BUFFER;
1201 if (++i > NUM_RX_BUFFER) {
1202 dbg(DBG_ASS, "intr_rx: Discarding more bufs"
1203 " than we have\n");
1204 break;
1205 }
1206 dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits);
1207 dbg(DBG_ASS, "DMA Bits of next buffer was %x\n", dmabits);
1208 }
1209 dbg(DBG_ASS, "There were %d subsequent buffers in error\n", i);
1210
1211 /* Discard the terminal buffer */
1212 if (!(dmabits & DMA_OWN)) {
1213 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1214 rxp = (rxp+1) % NUM_RX_BUFFER;
1215 }
1216 port->rxpos = rxp;
1217 return;
1218
1219 }
1220
1221 /* Rx complete interrupt
1222 */
1223 static void
fst_intr_rx(struct fst_card_info * card,struct fst_port_info * port)1224 fst_intr_rx(struct fst_card_info *card, struct fst_port_info *port)
1225 {
1226 unsigned char dmabits;
1227 int pi;
1228 int rxp;
1229 int rx_status;
1230 unsigned short len;
1231 struct sk_buff *skb;
1232
1233 /* Check we have a buffer to process */
1234 pi = port->index;
1235 rxp = port->rxpos;
1236 dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits);
1237 if (dmabits & DMA_OWN) {
1238 dbg(DBG_RX | DBG_INTR, "intr_rx: No buffer port %d pos %d\n",
1239 pi, rxp);
1240 return;
1241 }
1242 if (card->dmarx_in_progress) {
1243 return;
1244 }
1245
1246 /* Get buffer length */
1247 len = FST_RDW(card, rxDescrRing[pi][rxp].mcnt);
1248 /* Discard the CRC */
1249 len -= 2;
1250 if (len == 0) {
1251 /*
1252 * This seems to happen on the TE1 interface sometimes
1253 * so throw the frame away and log the event.
1254 */
1255 printk_err("Frame received with 0 length. Card %d Port %d\n",
1256 card->card_no, port->index);
1257 /* Return descriptor to card */
1258 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1259
1260 rxp = (rxp+1) % NUM_RX_BUFFER;
1261 port->rxpos = rxp;
1262 return;
1263 }
1264
1265 /* Check buffer length and for other errors. We insist on one packet
1266 * in one buffer. This simplifies things greatly and since we've
1267 * allocated 8K it shouldn't be a real world limitation
1268 */
1269 dbg(DBG_RX, "intr_rx: %d,%d: flags %x len %d\n", pi, rxp, dmabits, len);
1270 if (dmabits != (RX_STP | RX_ENP) || len > LEN_RX_BUFFER - 2) {
1271 fst_log_rx_error(card, port, dmabits, rxp, len);
1272 fst_recover_rx_error(card, port, dmabits, rxp, len);
1273 return;
1274 }
1275
1276 /* Allocate SKB */
1277 if ((skb = dev_alloc_skb(len)) == NULL) {
1278 dbg(DBG_RX, "intr_rx: can't allocate buffer\n");
1279
1280 port->hdlc.stats.rx_dropped++;
1281
1282 /* Return descriptor to card */
1283 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1284
1285 rxp = (rxp+1) % NUM_RX_BUFFER;
1286 port->rxpos = rxp;
1287 return;
1288 }
1289
1290 /*
1291 * We know the length we need to receive, len.
1292 * It's not worth using the DMA for reads of less than
1293 * FST_MIN_DMA_LEN
1294 */
1295
1296 if ((len < FST_MIN_DMA_LEN) || (card->family == FST_FAMILY_TXP)) {
1297 memcpy_fromio(skb_put(skb, len),
1298 card->mem + BUF_OFFSET(rxBuffer[pi][rxp][0]),
1299 len);
1300
1301 /* Reset buffer descriptor */
1302 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1303
1304 /* Update stats */
1305 port->hdlc.stats.rx_packets++;
1306 port->hdlc.stats.rx_bytes += len;
1307
1308 /* Push upstream */
1309 dbg(DBG_RX, "Pushing frame up the stack\n");
1310 skb->mac.raw = skb->data;
1311 skb->dev = hdlc_to_dev(&port->hdlc);
1312 if (port->mode == FST_RAW) {
1313 /*
1314 * Mark it for our own raw sockets interface
1315 */
1316 skb->protocol = htons(ETH_P_CUST);
1317 skb->pkt_type = PACKET_HOST;
1318 } else {
1319 skb->protocol = hdlc_type_trans(skb, skb->dev);
1320 }
1321 rx_status = netif_rx(skb);
1322 fst_process_rx_status(rx_status, port_to_dev(port)->name);
1323 if (rx_status == NET_RX_DROP) {
1324 port->hdlc.stats.rx_dropped++;
1325 }
1326 port_to_dev(port)->last_rx = jiffies;
1327 } else {
1328 card->dma_skb_rx = skb;
1329 card->dma_port_rx = port;
1330 card->dma_len_rx = len;
1331 card->dma_rxpos = rxp;
1332 fst_rx_dma(card, (char *) card->rx_dma_handle_card,
1333 (char *) BUF_OFFSET(rxBuffer[pi][rxp][0]), len);
1334 }
1335 if (rxp != port->rxpos) {
1336 dbg(DBG_ASS, "About to increment rxpos by more than 1\n");
1337 dbg(DBG_ASS, "rxp = %d rxpos = %d\n", rxp, port->rxpos);
1338 }
1339 rxp = (rxp+1) % NUM_RX_BUFFER;
1340 port->rxpos = rxp;
1341 }
1342
1343 /*
1344 * The bottom halfs to the ISR
1345 *
1346 */
1347
1348 static void
do_bottom_half_tx(struct fst_card_info * card)1349 do_bottom_half_tx(struct fst_card_info *card)
1350 {
1351 struct fst_port_info *port;
1352 int pi;
1353 int txq_length;
1354 struct sk_buff *skb;
1355 unsigned long flags;
1356
1357 /*
1358 * Find a free buffer for the transmit
1359 * Step through each port on this card
1360 */
1361
1362 dbg(DBG_TX, "do_bottom_half_tx\n");
1363 for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) {
1364 if (!port->run)
1365 continue;
1366
1367 while (!
1368 (FST_RDB(card, txDescrRing[pi][port->txpos].bits) &
1369 DMA_OWN)
1370 && !(card->dmatx_in_progress)) {
1371 /*
1372 * There doesn't seem to be a txdone event per-se
1373 * We seem to have to deduce it, by checking the DMA_OWN
1374 * bit on the next buffer we think we can use
1375 */
1376 spin_lock_irqsave(&card->card_lock, flags);
1377 if ((txq_length = port->txqe - port->txqs) < 0) {
1378 /*
1379 * This is the case where one has wrapped and the
1380 * maths gives us a negative number
1381 */
1382 txq_length = txq_length + FST_TXQ_DEPTH;
1383 }
1384 spin_unlock_irqrestore(&card->card_lock, flags);
1385 if (txq_length > 0) {
1386 /*
1387 * There is something to send
1388 */
1389 spin_lock_irqsave(&card->card_lock, flags);
1390 skb = port->txq[port->txqs];
1391 port->txqs++;
1392 if (port->txqs == FST_TXQ_DEPTH) {
1393 port->txqs = 0;
1394 }
1395 spin_unlock_irqrestore(&card->card_lock, flags);
1396 /*
1397 * copy the data and set the required indicators on the
1398 * card.
1399 */
1400 FST_WRW(card, txDescrRing[pi][port->txpos].bcnt,
1401 cnv_bcnt(skb->len));
1402 if ((skb->len < FST_MIN_DMA_LEN)
1403 || (card->family == FST_FAMILY_TXP)) {
1404 /* Enqueue the packet with normal io */
1405 memcpy_toio(card->mem +
1406 BUF_OFFSET(txBuffer[pi]
1407 [port->
1408 txpos][0]),
1409 skb->data, skb->len);
1410 FST_WRB(card,
1411 txDescrRing[pi][port->txpos].
1412 bits,
1413 DMA_OWN | TX_STP | TX_ENP);
1414 port->hdlc.stats.tx_packets++;
1415 port->hdlc.stats.tx_bytes += skb->len;
1416 port_to_dev(port)->trans_start =
1417 jiffies;
1418 } else {
1419 /* Or do it through dma */
1420 memcpy(card->tx_dma_handle_host,
1421 skb->data, skb->len);
1422 card->dma_port_tx = port;
1423 card->dma_len_tx = skb->len;
1424 card->dma_txpos = port->txpos;
1425 fst_tx_dma(card,
1426 (char *) card->
1427 tx_dma_handle_card,
1428 (char *)
1429 BUF_OFFSET(txBuffer[pi]
1430 [port->txpos][0]),
1431 skb->len);
1432 }
1433 if (++port->txpos >= NUM_TX_BUFFER)
1434 port->txpos = 0;
1435 /*
1436 * If we have flow control on, can we now release it?
1437 */
1438 if (port->start) {
1439 if (txq_length < fst_txq_low) {
1440 netif_wake_queue(port_to_dev
1441 (port));
1442 port->start = 0;
1443 }
1444 }
1445 dev_kfree_skb(skb);
1446 } else {
1447 /*
1448 * Nothing to send so break out of the while loop
1449 */
1450 break;
1451 }
1452 }
1453 }
1454 }
1455
1456 static void
do_bottom_half_rx(struct fst_card_info * card)1457 do_bottom_half_rx(struct fst_card_info *card)
1458 {
1459 struct fst_port_info *port;
1460 int pi;
1461 int rx_count = 0;
1462
1463 /* Check for rx completions on all ports on this card */
1464 dbg(DBG_RX, "do_bottom_half_rx\n");
1465 for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) {
1466 if (!port->run)
1467 continue;
1468 while (!(FST_RDB(card, rxDescrRing[pi][port->rxpos].bits)
1469 & DMA_OWN) && !(card->dmarx_in_progress)) {
1470 if (rx_count > fst_max_reads) {
1471 /*
1472 * Don't spend forever in receive processing
1473 * Schedule another event
1474 */
1475 fst_q_work_item(&fst_work_intq, card->card_no);
1476 tasklet_schedule(&fst_int_task);
1477 break; /* Leave the loop */
1478 }
1479 fst_intr_rx(card, port);
1480 rx_count++;
1481 }
1482 }
1483 }
1484
1485 /*
1486 * The interrupt service routine
1487 * Dev_id is our fst_card_info pointer
1488 */
1489 static void
fst_intr(int irq,void * dev_id,struct pt_regs * regs)1490 fst_intr(int irq, void *dev_id, struct pt_regs *regs)
1491 {
1492 struct fst_card_info *card;
1493 struct fst_port_info *port;
1494 int rdidx; /* Event buffer indices */
1495 int wridx;
1496 int event; /* Actual event for processing */
1497 unsigned int dma_intcsr = 0;
1498 unsigned int do_card_interrupt;
1499 unsigned int int_retry_count;
1500
1501 if ((card = dev_id) == NULL) {
1502 dbg(DBG_INTR, "intr: spurious %d\n", irq);
1503 return;
1504 }
1505
1506 /*
1507 * Check to see if the interrupt was for this card
1508 * return if not
1509 * Note that the call to clear the interrupt is important
1510 */
1511 dbg(DBG_INTR, "intr: %d %p\n", irq, card);
1512 if (card->state != FST_RUNNING) {
1513 printk_err
1514 ("Interrupt received for card %d in a non running state (%d)\n",
1515 card->card_no, card->state);
1516
1517 /*
1518 * It is possible to really be running, i.e. we have re-loaded
1519 * a running card
1520 * Clear and reprime the interrupt source
1521 */
1522 fst_clear_intr(card);
1523 return;
1524 }
1525
1526 /* Clear and reprime the interrupt source */
1527 fst_clear_intr(card);
1528
1529 /*
1530 * Is the interrupt for this card (handshake == 1)
1531 */
1532 do_card_interrupt = 0;
1533 if (FST_RDB(card, interruptHandshake) == 1) {
1534 do_card_interrupt += FST_CARD_INT;
1535 /* Set the software acknowledge */
1536 FST_WRB(card, interruptHandshake, 0xEE);
1537 }
1538 if (card->family == FST_FAMILY_TXU) {
1539 /*
1540 * Is it a DMA Interrupt
1541 */
1542 dma_intcsr = inl(card->pci_conf + INTCSR_9054);
1543 if (dma_intcsr & 0x00200000) {
1544 /*
1545 * DMA Channel 0 (Rx transfer complete)
1546 */
1547 dbg(DBG_RX, "DMA Rx xfer complete\n");
1548 outb(0x8, card->pci_conf + DMACSR0);
1549 fst_rx_dma_complete(card, card->dma_port_rx,
1550 card->dma_len_rx, card->dma_skb_rx,
1551 card->dma_rxpos);
1552 card->dmarx_in_progress = 0;
1553 do_card_interrupt += FST_RX_DMA_INT;
1554 }
1555 if (dma_intcsr & 0x00400000) {
1556 /*
1557 * DMA Channel 1 (Tx transfer complete)
1558 */
1559 dbg(DBG_TX, "DMA Tx xfer complete\n");
1560 outb(0x8, card->pci_conf + DMACSR1);
1561 fst_tx_dma_complete(card, card->dma_port_tx,
1562 card->dma_len_tx, card->dma_txpos);
1563 card->dmatx_in_progress = 0;
1564 do_card_interrupt += FST_TX_DMA_INT;
1565 }
1566 }
1567
1568 /*
1569 * Have we been missing Interrupts
1570 */
1571 int_retry_count = FST_RDL(card, interruptRetryCount);
1572 if (int_retry_count) {
1573 dbg(DBG_ASS, "Card %d int_retry_count is %d\n",
1574 card->card_no, int_retry_count);
1575 FST_WRL(card, interruptRetryCount, 0);
1576 }
1577
1578 if (!do_card_interrupt) {
1579 return;
1580 }
1581
1582 /* Scehdule the bottom half of the ISR */
1583 fst_q_work_item(&fst_work_intq, card->card_no);
1584 tasklet_schedule(&fst_int_task);
1585
1586 /* Drain the event queue */
1587 rdidx = FST_RDB(card, interruptEvent.rdindex) & 0x1f;
1588 wridx = FST_RDB(card, interruptEvent.wrindex) & 0x1f;
1589 while (rdidx != wridx) {
1590 event = FST_RDB(card, interruptEvent.evntbuff[rdidx]);
1591 port = &card->ports[event & 0x03];
1592
1593 dbg(DBG_INTR, "Processing Interrupt event: %x\n", event);
1594
1595 switch (event) {
1596 case TE1_ALMA:
1597 dbg(DBG_INTR, "TE1 Alarm intr\n");
1598 if (port->run)
1599 fst_intr_te1_alarm(card, port);
1600 break;
1601
1602 case CTLA_CHG:
1603 case CTLB_CHG:
1604 case CTLC_CHG:
1605 case CTLD_CHG:
1606 if (port->run)
1607 fst_intr_ctlchg(card, port);
1608 break;
1609
1610 case ABTA_SENT:
1611 case ABTB_SENT:
1612 case ABTC_SENT:
1613 case ABTD_SENT:
1614 dbg(DBG_TX, "Abort complete port %d\n", port->index);
1615 break;
1616
1617 case TXA_UNDF:
1618 case TXB_UNDF:
1619 case TXC_UNDF:
1620 case TXD_UNDF:
1621 /* Difficult to see how we'd get this given that we
1622 * always load up the entire packet for DMA.
1623 */
1624 dbg(DBG_TX, "Tx underflow port %d\n", port->index);
1625
1626 port->hdlc.stats.tx_errors++;
1627 port->hdlc.stats.tx_fifo_errors++;
1628 dbg(DBG_ASS, "Tx underflow on card %d port %d\n",
1629 card->card_no, port->index);
1630 break;
1631
1632 case INIT_CPLT:
1633 dbg(DBG_INIT, "Card init OK intr\n");
1634 break;
1635
1636 case INIT_FAIL:
1637 dbg(DBG_INIT, "Card init FAILED intr\n");
1638 card->state = FST_IFAILED;
1639 break;
1640
1641 default:
1642 printk_err("intr: unknown card event %d. ignored\n",
1643 event);
1644 break;
1645 }
1646
1647 /* Bump and wrap the index */
1648 if (++rdidx >= MAX_CIRBUFF)
1649 rdidx = 0;
1650 }
1651 FST_WRB(card, interruptEvent.rdindex, rdidx);
1652 }
1653
1654 /* Check that the shared memory configuration is one that we can handle
1655 * and that some basic parameters are correct
1656 */
1657 static void
check_started_ok(struct fst_card_info * card)1658 check_started_ok(struct fst_card_info *card)
1659 {
1660 int i;
1661
1662 /* Check structure version and end marker */
1663 if (FST_RDW(card, smcVersion) != SMC_VERSION) {
1664 printk_err("Bad shared memory version %d expected %d\n",
1665 FST_RDW(card, smcVersion), SMC_VERSION);
1666 card->state = FST_BADVERSION;
1667 return;
1668 }
1669 if (FST_RDL(card, endOfSmcSignature) != END_SIG) {
1670 printk_err("Missing shared memory signature\n");
1671 card->state = FST_BADVERSION;
1672 return;
1673 }
1674 /* Firmware status flag, 0x00 = initialising, 0x01 = OK, 0xFF = fail */
1675 if ((i = FST_RDB(card, taskStatus)) == 0x01) {
1676 card->state = FST_RUNNING;
1677 } else if (i == 0xFF) {
1678 printk_err("Firmware initialisation failed. Card halted\n");
1679 card->state = FST_HALTED;
1680 return;
1681 } else if (i != 0x00) {
1682 printk_err("Unknown firmware status 0x%x\n", i);
1683 card->state = FST_HALTED;
1684 return;
1685 }
1686
1687 /* Finally check the number of ports reported by firmware against the
1688 * number we assumed at card detection. Should never happen with
1689 * existing firmware etc so we just report it for the moment.
1690 */
1691 if (FST_RDL(card, numberOfPorts) != card->nports) {
1692 printk_warn("Port count mismatch on card %d."
1693 " Firmware thinks %d we say %d\n", card->card_no,
1694 FST_RDL(card, numberOfPorts), card->nports);
1695 }
1696 }
1697
1698 static int
set_conf_from_info(struct fst_card_info * card,struct fst_port_info * port,struct fstioc_info * info)1699 set_conf_from_info(struct fst_card_info *card, struct fst_port_info *port,
1700 struct fstioc_info *info)
1701 {
1702 int err;
1703 unsigned char my_framing;
1704
1705 /* Set things according to the user set valid flags
1706 * Several of the old options have been invalidated/replaced by the
1707 * generic hdlc package.
1708 */
1709 err = 0;
1710 if (info->valid & FSTVAL_PROTO) {
1711 if (info->proto == FST_RAW)
1712 port->mode = FST_RAW;
1713 else
1714 port->mode = FST_GEN_HDLC;
1715 }
1716
1717 if (info->valid & FSTVAL_CABLE)
1718 err = -EINVAL;
1719
1720 if (info->valid & FSTVAL_SPEED)
1721 err = -EINVAL;
1722
1723 if (info->valid & FSTVAL_PHASE)
1724 FST_WRB(card, portConfig[port->index].invertClock,
1725 info->invertClock);
1726 if (info->valid & FSTVAL_MODE)
1727 FST_WRW(card, cardMode, info->cardMode);
1728 if (info->valid & FSTVAL_TE1) {
1729 FST_WRL(card, suConfig.dataRate, info->lineSpeed);
1730 FST_WRB(card, suConfig.clocking, info->clockSource);
1731 my_framing = FRAMING_E1;
1732 if (info->framing == E1)
1733 my_framing = FRAMING_E1;
1734 if (info->framing == T1)
1735 my_framing = FRAMING_T1;
1736 if (info->framing == J1)
1737 my_framing = FRAMING_J1;
1738 FST_WRB(card, suConfig.framing, my_framing);
1739 FST_WRB(card, suConfig.structure, info->structure);
1740 FST_WRB(card, suConfig.interface, info->interface);
1741 FST_WRB(card, suConfig.coding, info->coding);
1742 FST_WRB(card, suConfig.lineBuildOut, info->lineBuildOut);
1743 FST_WRB(card, suConfig.equalizer, info->equalizer);
1744 FST_WRB(card, suConfig.transparentMode, info->transparentMode);
1745 FST_WRB(card, suConfig.loopMode, info->loopMode);
1746 FST_WRB(card, suConfig.range, info->range);
1747 FST_WRB(card, suConfig.txBufferMode, info->txBufferMode);
1748 FST_WRB(card, suConfig.rxBufferMode, info->rxBufferMode);
1749 FST_WRB(card, suConfig.startingSlot, info->startingSlot);
1750 FST_WRB(card, suConfig.losThreshold, info->losThreshold);
1751 if (info->idleCode)
1752 FST_WRB(card, suConfig.enableIdleCode, 1);
1753 else
1754 FST_WRB(card, suConfig.enableIdleCode, 0);
1755 FST_WRB(card, suConfig.idleCode, info->idleCode);
1756 #if FST_DEBUG
1757 if (info->valid & FSTVAL_TE1) {
1758 printk("Setting TE1 data\n");
1759 printk("Line Speed = %d\n", info->lineSpeed);
1760 printk("Start slot = %d\n", info->startingSlot);
1761 printk("Clock source = %d\n", info->clockSource);
1762 printk("Framing = %d\n", my_framing);
1763 printk("Structure = %d\n", info->structure);
1764 printk("interface = %d\n", info->interface);
1765 printk("Coding = %d\n", info->coding);
1766 printk("Line build out = %d\n", info->lineBuildOut);
1767 printk("Equaliser = %d\n", info->equalizer);
1768 printk("Transparent mode = %d\n",
1769 info->transparentMode);
1770 printk("Loop mode = %d\n", info->loopMode);
1771 printk("Range = %d\n", info->range);
1772 printk("Tx Buffer mode = %d\n", info->txBufferMode);
1773 printk("Rx Buffer mode = %d\n", info->rxBufferMode);
1774 printk("LOS Threshold = %d\n", info->losThreshold);
1775 printk("Idle Code = %d\n", info->idleCode);
1776 }
1777 #endif
1778 }
1779 #if FST_DEBUG
1780 if (info->valid & FSTVAL_DEBUG) {
1781 fst_debug_mask = info->debug;
1782 }
1783 #endif
1784
1785 return err;
1786 }
1787
1788 static void
gather_conf_info(struct fst_card_info * card,struct fst_port_info * port,struct fstioc_info * info)1789 gather_conf_info(struct fst_card_info *card, struct fst_port_info *port,
1790 struct fstioc_info *info)
1791 {
1792 int i;
1793
1794 memset(info, 0, sizeof (struct fstioc_info));
1795
1796 i = port->index;
1797 info->kernelVersion = LINUX_VERSION_CODE;
1798 info->nports = card->nports;
1799 info->type = card->type;
1800 info->state = card->state;
1801 info->proto = FST_GEN_HDLC;
1802 info->index = i;
1803 #if FST_DEBUG
1804 info->debug = fst_debug_mask;
1805 #endif
1806
1807 /* Only mark information as valid if card is running.
1808 * Copy the data anyway in case it is useful for diagnostics
1809 */
1810 info->valid = ((card->state == FST_RUNNING) ? FSTVAL_ALL : FSTVAL_CARD)
1811 #if FST_DEBUG
1812 | FSTVAL_DEBUG
1813 #endif
1814 ;
1815
1816 info->lineInterface = FST_RDW(card, portConfig[i].lineInterface);
1817 info->internalClock = FST_RDB(card, portConfig[i].internalClock);
1818 info->lineSpeed = FST_RDL(card, portConfig[i].lineSpeed);
1819 info->invertClock = FST_RDB(card, portConfig[i].invertClock);
1820 info->v24IpSts = FST_RDL(card, v24IpSts[i]);
1821 info->v24OpSts = FST_RDL(card, v24OpSts[i]);
1822 info->clockStatus = FST_RDW(card, clockStatus[i]);
1823 info->cableStatus = FST_RDW(card, cableStatus);
1824 info->cardMode = FST_RDW(card, cardMode);
1825 info->smcFirmwareVersion = FST_RDL(card, smcFirmwareVersion);
1826
1827 /*
1828 * The T2U can report cable presence for both A or B
1829 * in bits 0 and 1 of cableStatus. See which port we are and
1830 * do the mapping.
1831 */
1832 if (card->family == FST_FAMILY_TXU) {
1833 if (port->index == 0) {
1834 /*
1835 * Port A
1836 */
1837 info->cableStatus = info->cableStatus & 1;
1838 } else {
1839 /*
1840 * Port B
1841 */
1842 info->cableStatus = info->cableStatus >> 1;
1843 info->cableStatus = info->cableStatus & 1;
1844 }
1845 }
1846 /*
1847 * Some additional bits if we are TE1
1848 */
1849 if (card->type == FST_TYPE_TE1) {
1850 info->lineSpeed = FST_RDL(card, suConfig.dataRate);
1851 info->clockSource = FST_RDB(card, suConfig.clocking);
1852 info->framing = FST_RDB(card, suConfig.framing);
1853 info->structure = FST_RDB(card, suConfig.structure);
1854 info->interface = FST_RDB(card, suConfig.interface);
1855 info->coding = FST_RDB(card, suConfig.coding);
1856 info->lineBuildOut = FST_RDB(card, suConfig.lineBuildOut);
1857 info->equalizer = FST_RDB(card, suConfig.equalizer);
1858 info->loopMode = FST_RDB(card, suConfig.loopMode);
1859 info->range = FST_RDB(card, suConfig.range);
1860 info->txBufferMode = FST_RDB(card, suConfig.txBufferMode);
1861 info->rxBufferMode = FST_RDB(card, suConfig.rxBufferMode);
1862 info->startingSlot = FST_RDB(card, suConfig.startingSlot);
1863 info->losThreshold = FST_RDB(card, suConfig.losThreshold);
1864 if (FST_RDB(card, suConfig.enableIdleCode))
1865 info->idleCode = FST_RDB(card, suConfig.idleCode);
1866 else
1867 info->idleCode = 0;
1868 info->receiveBufferDelay =
1869 FST_RDL(card, suStatus.receiveBufferDelay);
1870 info->framingErrorCount =
1871 FST_RDL(card, suStatus.framingErrorCount);
1872 info->codeViolationCount =
1873 FST_RDL(card, suStatus.codeViolationCount);
1874 info->crcErrorCount = FST_RDL(card, suStatus.crcErrorCount);
1875 info->lineAttenuation = FST_RDL(card, suStatus.lineAttenuation);
1876 info->lossOfSignal = FST_RDB(card, suStatus.lossOfSignal);
1877 info->receiveRemoteAlarm =
1878 FST_RDB(card, suStatus.receiveRemoteAlarm);
1879 info->alarmIndicationSignal =
1880 FST_RDB(card, suStatus.alarmIndicationSignal);
1881 }
1882 }
1883
1884 static int
fst_set_iface(struct fst_card_info * card,struct fst_port_info * port,struct ifreq * ifr)1885 fst_set_iface(struct fst_card_info *card, struct fst_port_info *port,
1886 struct ifreq *ifr)
1887 {
1888 sync_serial_settings sync;
1889 int i;
1890
1891 if (ifr->ifr_settings.size != sizeof (sync)) {
1892 return -ENOMEM;
1893 }
1894
1895 if (copy_from_user
1896 (&sync, ifr->ifr_settings.ifs_ifsu.sync, sizeof (sync))) {
1897 return -EFAULT;
1898 }
1899
1900 if (sync.loopback)
1901 return -EINVAL;
1902
1903 i = port->index;
1904
1905 switch (ifr->ifr_settings.type) {
1906 case IF_IFACE_V35:
1907 FST_WRW(card, portConfig[i].lineInterface, V35);
1908 port->hwif = V35;
1909 break;
1910
1911 case IF_IFACE_V24:
1912 FST_WRW(card, portConfig[i].lineInterface, V24);
1913 port->hwif = V24;
1914 break;
1915
1916 case IF_IFACE_X21:
1917 FST_WRW(card, portConfig[i].lineInterface, X21);
1918 port->hwif = X21;
1919 break;
1920
1921 case IF_IFACE_X21D:
1922 FST_WRW(card, portConfig[i].lineInterface, X21D);
1923 port->hwif = X21D;
1924 break;
1925
1926 case IF_IFACE_T1:
1927 FST_WRW(card, portConfig[i].lineInterface, T1);
1928 port->hwif = T1;
1929 break;
1930
1931 case IF_IFACE_E1:
1932 FST_WRW(card, portConfig[i].lineInterface, E1);
1933 port->hwif = E1;
1934 break;
1935
1936 case IF_IFACE_SYNC_SERIAL:
1937 break;
1938
1939 default:
1940 return -EINVAL;
1941 }
1942
1943 switch (sync.clock_type) {
1944 case CLOCK_EXT:
1945 FST_WRB(card, portConfig[i].internalClock, EXTCLK);
1946 break;
1947
1948 case CLOCK_INT:
1949 FST_WRB(card, portConfig[i].internalClock, INTCLK);
1950 break;
1951
1952 default:
1953 return -EINVAL;
1954 }
1955 FST_WRL(card, portConfig[i].lineSpeed, sync.clock_rate);
1956 return 0;
1957 }
1958
1959 static int
fst_get_iface(struct fst_card_info * card,struct fst_port_info * port,struct ifreq * ifr)1960 fst_get_iface(struct fst_card_info *card, struct fst_port_info *port,
1961 struct ifreq *ifr)
1962 {
1963 sync_serial_settings sync;
1964 int i;
1965
1966 /* First check what line type is set, we'll default to reporting X.21
1967 * if nothing is set as IF_IFACE_SYNC_SERIAL implies it can't be
1968 * changed
1969 */
1970 switch (port->hwif) {
1971 case E1:
1972 ifr->ifr_settings.type = IF_IFACE_E1;
1973 break;
1974 case T1:
1975 ifr->ifr_settings.type = IF_IFACE_T1;
1976 break;
1977 case V35:
1978 ifr->ifr_settings.type = IF_IFACE_V35;
1979 break;
1980 case V24:
1981 ifr->ifr_settings.type = IF_IFACE_V24;
1982 break;
1983 case X21D:
1984 ifr->ifr_settings.type = IF_IFACE_X21D;
1985 break;
1986 case X21:
1987 default:
1988 ifr->ifr_settings.type = IF_IFACE_X21;
1989 break;
1990 }
1991 if (ifr->ifr_settings.size == 0) {
1992 return 0; /* only type requested */
1993 }
1994 if (ifr->ifr_settings.size < sizeof (sync)) {
1995 return -ENOMEM;
1996 }
1997
1998 i = port->index;
1999 sync.clock_rate = FST_RDL(card, portConfig[i].lineSpeed);
2000 /* Lucky card and linux use same encoding here */
2001 sync.clock_type = FST_RDB(card, portConfig[i].internalClock) ==
2002 INTCLK ? CLOCK_INT : CLOCK_EXT;
2003 sync.loopback = 0;
2004
2005 if (copy_to_user(ifr->ifr_settings.ifs_ifsu.sync, &sync, sizeof (sync))) {
2006 return -EFAULT;
2007 }
2008
2009 ifr->ifr_settings.size = sizeof (sync);
2010 return 0;
2011 }
2012
2013 static int
fst_ioctl(struct net_device * dev,struct ifreq * ifr,int cmd)2014 fst_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2015 {
2016 struct fst_card_info *card;
2017 struct fst_port_info *port;
2018 struct fstioc_write wrthdr;
2019 struct fstioc_info info;
2020 unsigned long flags;
2021
2022 dbg(DBG_IOCTL, "ioctl: %x, %p\n", cmd, ifr->ifr_data);
2023
2024 port = dev_to_port(dev);
2025 card = port->card;
2026
2027 if (!capable(CAP_NET_ADMIN))
2028 return -EPERM;
2029
2030 switch (cmd) {
2031 case FSTCPURESET:
2032 fst_cpureset(card);
2033 card->state = FST_RESET;
2034 return 0;
2035
2036 case FSTCPURELEASE:
2037 fst_cpurelease(card);
2038 card->state = FST_STARTING;
2039 return 0;
2040
2041 case FSTWRITE: /* Code write (download) */
2042
2043 /* First copy in the header with the length and offset of data
2044 * to write
2045 */
2046 if (ifr->ifr_data == NULL) {
2047 return -EINVAL;
2048 }
2049 if (copy_from_user(&wrthdr, ifr->ifr_data,
2050 sizeof (struct fstioc_write))) {
2051 return -EFAULT;
2052 }
2053
2054 /* Sanity check the parameters. We don't support partial writes
2055 * when going over the top
2056 */
2057 if (wrthdr.size > FST_MEMSIZE || wrthdr.offset > FST_MEMSIZE
2058 || wrthdr.size + wrthdr.offset > FST_MEMSIZE) {
2059 return -ENXIO;
2060 }
2061
2062 /* Now copy the data to the card.
2063 * This will probably break on some architectures.
2064 * I'll fix it when I have something to test on.
2065 */
2066 if (copy_from_user(card->mem + wrthdr.offset,
2067 ifr->ifr_data + sizeof (struct fstioc_write),
2068 wrthdr.size)) {
2069 return -EFAULT;
2070 }
2071
2072 /* Writes to the memory of a card in the reset state constitute
2073 * a download
2074 */
2075 if (card->state == FST_RESET) {
2076 card->state = FST_DOWNLOAD;
2077 }
2078 return 0;
2079
2080 case FSTGETCONF:
2081
2082 /* If card has just been started check the shared memory config
2083 * version and marker
2084 */
2085 if (card->state == FST_STARTING) {
2086 check_started_ok(card);
2087
2088 /* If everything checked out enable card interrupts */
2089 if (card->state == FST_RUNNING) {
2090 spin_lock_irqsave(&card->card_lock, flags);
2091 fst_enable_intr(card);
2092 FST_WRB(card, interruptHandshake, 0xEE);
2093 spin_unlock_irqrestore(&card->card_lock, flags);
2094 }
2095 }
2096
2097 if (ifr->ifr_data == NULL) {
2098 return -EINVAL;
2099 }
2100
2101 gather_conf_info(card, port, &info);
2102
2103 if (copy_to_user(ifr->ifr_data, &info, sizeof (info))) {
2104 return -EFAULT;
2105 }
2106 return 0;
2107
2108 case FSTSETCONF:
2109
2110 /*
2111 * Most of the settings have been moved to the generic ioctls
2112 * this just covers debug and board ident now
2113 */
2114
2115 if (card->state != FST_RUNNING) {
2116 printk_err
2117 ("Attempt to configure card %d in non-running state (%d)\n",
2118 card->card_no, card->state);
2119 return -EIO;
2120 }
2121 if (copy_from_user(&info, ifr->ifr_data, sizeof (info))) {
2122 return -EFAULT;
2123 }
2124
2125 return set_conf_from_info(card, port, &info);
2126
2127 case SIOCWANDEV:
2128 switch (ifr->ifr_settings.type) {
2129 case IF_GET_IFACE:
2130 return fst_get_iface(card, port, ifr);
2131
2132 case IF_IFACE_SYNC_SERIAL:
2133 case IF_IFACE_V35:
2134 case IF_IFACE_V24:
2135 case IF_IFACE_X21:
2136 case IF_IFACE_X21D:
2137 case IF_IFACE_T1:
2138 case IF_IFACE_E1:
2139 return fst_set_iface(card, port, ifr);
2140
2141 case IF_PROTO_RAW:
2142 port->mode = FST_RAW;
2143 return 0;
2144
2145 case IF_GET_PROTO:
2146 if (port->mode == FST_RAW) {
2147 ifr->ifr_settings.type = IF_PROTO_RAW;
2148 return 0;
2149 }
2150 return hdlc_ioctl(dev, ifr, cmd);
2151
2152 default:
2153 port->mode = FST_GEN_HDLC;
2154 dbg(DBG_IOCTL, "Passing this type to hdlc %x\n",
2155 ifr->ifr_settings.type);
2156 return hdlc_ioctl(dev, ifr, cmd);
2157 }
2158
2159 default:
2160 /* Not one of ours. Pass through to HDLC package */
2161 return hdlc_ioctl(dev, ifr, cmd);
2162 }
2163 }
2164
2165 static void
fst_openport(struct fst_port_info * port)2166 fst_openport(struct fst_port_info *port)
2167 {
2168 int signals;
2169 int txq_length;
2170
2171 /* Only init things if card is actually running. This allows open to
2172 * succeed for downloads etc.
2173 */
2174 if (port->card->state == FST_RUNNING) {
2175 if (port->run) {
2176 dbg(DBG_OPEN, "open: found port already running\n");
2177
2178 fst_issue_cmd(port, STOPPORT);
2179 port->run = 0;
2180 }
2181
2182 fst_rx_config(port);
2183 fst_tx_config(port);
2184 fst_op_raise(port, OPSTS_RTS | OPSTS_DTR);
2185
2186 fst_issue_cmd(port, STARTPORT);
2187 port->run = 1;
2188
2189 signals = FST_RDL(port->card, v24DebouncedSts[port->index]);
2190 if (signals & (((port->hwif == X21) || (port->hwif == X21D))
2191 ? IPSTS_INDICATE : IPSTS_DCD))
2192 netif_carrier_on(port_to_dev(port));
2193 else
2194 netif_carrier_off(port_to_dev(port));
2195
2196 txq_length = port->txqe - port->txqs;
2197 port->txqe = 0;
2198 port->txqs = 0;
2199 }
2200
2201 }
2202
2203 static void
fst_closeport(struct fst_port_info * port)2204 fst_closeport(struct fst_port_info *port)
2205 {
2206 if (port->card->state == FST_RUNNING) {
2207 if (port->run) {
2208 port->run = 0;
2209 fst_op_lower(port, OPSTS_RTS | OPSTS_DTR);
2210
2211 fst_issue_cmd(port, STOPPORT);
2212 } else {
2213 dbg(DBG_OPEN, "close: port not running\n");
2214 }
2215 }
2216 }
2217
2218 static int
fst_open(struct net_device * dev)2219 fst_open(struct net_device *dev)
2220 {
2221 int err;
2222 struct fst_port_info *port;
2223
2224 port = dev_to_port(dev);
2225 MOD_INC_USE_COUNT;
2226 if (port->mode != FST_RAW) {
2227 err = hdlc_open(dev_to_hdlc(dev));
2228 if (err)
2229 return err;
2230 }
2231
2232 fst_openport(port);
2233 netif_wake_queue(dev);
2234 return 0;
2235 }
2236
2237 static int
fst_close(struct net_device * dev)2238 fst_close(struct net_device *dev)
2239 {
2240 struct fst_port_info *port;
2241 struct fst_card_info *card;
2242 unsigned char tx_dma_done;
2243 unsigned char rx_dma_done;
2244
2245 port = dev_to_port(dev);
2246 card = port->card;
2247
2248 tx_dma_done = inb(card->pci_conf + DMACSR1);
2249 rx_dma_done = inb(card->pci_conf + DMACSR0);
2250 dbg(DBG_OPEN,
2251 "Port Close: tx_dma_in_progress = %d (%x) rx_dma_in_progress = %d (%x)\n",
2252 card->dmatx_in_progress, tx_dma_done, card->dmarx_in_progress,
2253 rx_dma_done);
2254
2255 netif_stop_queue(dev);
2256 fst_closeport(dev_to_port(dev));
2257 if (port->mode != FST_RAW) {
2258 hdlc_close(dev_to_hdlc(dev));
2259 }
2260 MOD_DEC_USE_COUNT;
2261 return 0;
2262 }
2263
2264 static int
fst_attach(hdlc_device * hdlc,unsigned short encoding,unsigned short parity)2265 fst_attach(hdlc_device * hdlc, unsigned short encoding, unsigned short parity)
2266 {
2267 /*
2268 * Setting currently fixed in FarSync card so we check and forget
2269 */
2270 if (encoding != ENCODING_NRZ || parity != PARITY_CRC16_PR1_CCITT)
2271 return -EINVAL;
2272 return 0;
2273 }
2274
2275 static void
fst_tx_timeout(struct net_device * dev)2276 fst_tx_timeout(struct net_device *dev)
2277 {
2278 struct fst_port_info *port;
2279 struct fst_card_info *card;
2280
2281 port = dev_to_port(dev);
2282 card = port->card;
2283
2284 port->hdlc.stats.tx_errors++;
2285 port->hdlc.stats.tx_aborted_errors++;
2286 dbg(DBG_ASS, "Tx timeout card %d port %d\n",
2287 card->card_no, port->index);
2288 fst_issue_cmd(port, ABORTTX);
2289
2290 dev->trans_start = jiffies;
2291 netif_wake_queue(dev);
2292 port->start = 0;
2293 }
2294
2295 static int
fst_start_xmit(struct sk_buff * skb,struct net_device * dev)2296 fst_start_xmit(struct sk_buff *skb, struct net_device *dev)
2297 {
2298 struct fst_card_info *card;
2299 struct fst_port_info *port;
2300 unsigned long flags;
2301 int txq_length;
2302
2303 port = dev_to_port(dev);
2304 card = port->card;
2305 dbg(DBG_TX, "fst_start_xmit: length = %d\n", skb->len);
2306
2307 /* Drop packet with error if we don't have carrier */
2308 if (!netif_carrier_ok(dev)) {
2309 dev_kfree_skb(skb);
2310 port->hdlc.stats.tx_errors++;
2311 port->hdlc.stats.tx_carrier_errors++;
2312 dbg(DBG_ASS,
2313 "Tried to transmit but no carrier on card %d port %d\n",
2314 card->card_no, port->index);
2315 return 0;
2316 }
2317
2318 /* Drop it if it's too big! MTU failure ? */
2319 if (skb->len > LEN_TX_BUFFER) {
2320 dbg(DBG_ASS, "Packet too large %d vs %d\n", skb->len,
2321 LEN_TX_BUFFER);
2322 dev_kfree_skb(skb);
2323 port->hdlc.stats.tx_errors++;
2324 return 0;
2325 }
2326
2327 /*
2328 * We are always going to queue the packet
2329 * so that the bottom half is the only place we tx from
2330 * Check there is room in the port txq
2331 */
2332 spin_lock_irqsave(&card->card_lock, flags);
2333 if ((txq_length = port->txqe - port->txqs) < 0) {
2334 /*
2335 * This is the case where the next free has wrapped but the
2336 * last used hasn't
2337 */
2338 txq_length = txq_length + FST_TXQ_DEPTH;
2339 }
2340 spin_unlock_irqrestore(&card->card_lock, flags);
2341 if (txq_length > fst_txq_high) {
2342 /*
2343 * We have got enough buffers in the pipeline. Ask the network
2344 * layer to stop sending frames down
2345 */
2346 netif_stop_queue(dev);
2347 port->start = 1; /* I'm using this to signal stop sent up */
2348 }
2349
2350 if (txq_length == FST_TXQ_DEPTH - 1) {
2351 /*
2352 * This shouldn't have happened but such is life
2353 */
2354 dev_kfree_skb(skb);
2355 port->hdlc.stats.tx_errors++;
2356 dbg(DBG_ASS, "Tx queue overflow card %d port %d\n",
2357 card->card_no, port->index);
2358 return 0;
2359 }
2360
2361 /*
2362 * queue the buffer
2363 */
2364 spin_lock_irqsave(&card->card_lock, flags);
2365 port->txq[port->txqe] = skb;
2366 port->txqe++;
2367 if (port->txqe == FST_TXQ_DEPTH)
2368 port->txqe = 0;
2369 spin_unlock_irqrestore(&card->card_lock, flags);
2370
2371 /* Scehdule the bottom half which now does transmit processing */
2372 fst_q_work_item(&fst_work_txq, card->card_no);
2373 tasklet_schedule(&fst_tx_task);
2374
2375 return 0;
2376 }
2377
2378 /*
2379 * Card setup having checked hardware resources.
2380 * Should be pretty bizarre if we get an error here (kernel memory
2381 * exhaustion is one possibility). If we do see a problem we report it
2382 * via a printk and leave the corresponding interface and all that follow
2383 * disabled.
2384 */
2385 static char *type_strings[] __devinitdata = {
2386 "no hardware", /* Should never be seen */
2387 "FarSync T2P",
2388 "FarSync T4P",
2389 "FarSync T1U",
2390 "FarSync T2U",
2391 "FarSync T4U",
2392 "FarSync TE1"
2393 };
2394
2395 static void __devinit
fst_init_card(struct fst_card_info * card)2396 fst_init_card(struct fst_card_info *card)
2397 {
2398 int i;
2399 int err;
2400 struct net_device *dev;
2401
2402 /* We're working on a number of ports based on the card ID. If the
2403 * firmware detects something different later (should never happen)
2404 * we'll have to revise it in some way then.
2405 */
2406 for (i = 0; i < card->nports; i++) {
2407 card->ports[i].card = card;
2408 card->ports[i].index = i;
2409 card->ports[i].run = 0;
2410 card->ports[i].mode = FST_GEN_HDLC;
2411
2412 dev = hdlc_to_dev(&card->ports[i].hdlc);
2413
2414 /* Fill in the net device info
2415 * Since this is a PCI setup this is purely
2416 * informational. Give them the buffer addresses
2417 * and basic card I/O.
2418 */
2419 dev->mem_start = card->phys_mem + BUF_OFFSET(txBuffer[i][0][0]);
2420 dev->mem_end = card->phys_mem
2421 + BUF_OFFSET(txBuffer[i][NUM_TX_BUFFER][0]);
2422 dev->base_addr = card->pci_conf;
2423 dev->irq = card->irq;
2424
2425 dev->tx_queue_len = FST_TX_QUEUE_LEN;
2426 dev->open = fst_open;
2427 dev->stop = fst_close;
2428 dev->do_ioctl = fst_ioctl;
2429 dev->watchdog_timeo = FST_TX_TIMEOUT;
2430 dev->tx_timeout = fst_tx_timeout;
2431 card->ports[i].hdlc.attach = fst_attach;
2432 card->ports[i].hdlc.xmit = fst_start_xmit;
2433
2434 if ((err = register_hdlc_device(&card->ports[i].hdlc)) < 0) {
2435 printk_err("Cannot register HDLC device for port %d"
2436 " (errno %d)\n", i, -err);
2437 card->nports = i;
2438 break;
2439 }
2440 }
2441
2442 spin_lock_init(&card->card_lock);
2443
2444 printk_info("%s-%s: %s IRQ%d, %d ports\n",
2445 hdlc_to_dev(&card->ports[0].hdlc)->name,
2446 hdlc_to_dev(&card->ports[card->nports - 1].hdlc)->name,
2447 type_strings[card->type], card->irq, card->nports);
2448 }
2449
2450 /*
2451 * Initialise card when detected.
2452 * Returns 0 to indicate success, or errno otherwise.
2453 */
2454 static int __devinit
fst_add_one(struct pci_dev * pdev,const struct pci_device_id * ent)2455 fst_add_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2456 {
2457 static int firsttime_done = 0;
2458 static int no_of_cards_added = 0;
2459 struct fst_card_info *card;
2460 int err = 0;
2461 int i;
2462
2463 if (!firsttime_done) {
2464 printk_info("FarSync WAN driver " FST_USER_VERSION
2465 " (c) 2001-2004 FarSite Communications Ltd.\n");
2466 firsttime_done = 1;
2467 dbg(DBG_ASS, "The value of debug mask is %x\n", fst_debug_mask);
2468 }
2469
2470 /*
2471 * We are going to be clever and allow certain cards not to be
2472 * configured. An exclude list can be provided in /etc/modules.conf
2473 */
2474 if (fst_excluded_cards != 0) {
2475 /*
2476 * There are cards to exclude
2477 *
2478 */
2479 for (i = 0; i < fst_excluded_cards; i++) {
2480 if ((pdev->devfn) >> 3 == fst_excluded_list[i]) {
2481 printk_info("FarSync PCI device %d not assigned\n",
2482 (pdev->devfn) >> 3);
2483 return -EBUSY;
2484 }
2485 }
2486 }
2487
2488 /* Allocate driver private data */
2489 card = kmalloc(sizeof (struct fst_card_info), GFP_KERNEL);
2490 if (card == NULL) {
2491 printk_err("FarSync card found but insufficient memory for"
2492 " driver storage\n");
2493 return -ENOMEM;
2494 }
2495 memset(card, 0, sizeof (struct fst_card_info));
2496
2497 /* Try to enable the device */
2498 if ((err = pci_enable_device(pdev)) != 0) {
2499 printk_err("Failed to enable card. Err %d\n", -err);
2500 kfree(card);
2501 return err;
2502 }
2503
2504 if ((err = pci_request_regions(pdev, "FarSync")) !=0) {
2505 printk_err("Failed to allocate regions. Err %d\n", -err);
2506 pci_disable_device(pdev);
2507 kfree(card);
2508 return err;
2509 }
2510
2511 /* Get virtual addresses of memory regions */
2512 card->pci_conf = pci_resource_start(pdev, 1);
2513 card->phys_mem = pci_resource_start(pdev, 2);
2514 card->phys_ctlmem = pci_resource_start(pdev, 3);
2515 if ((card->mem = ioremap(card->phys_mem, FST_MEMSIZE)) == NULL) {
2516 printk_err("Physical memory remap failed\n");
2517 pci_release_regions(pdev);
2518 pci_disable_device(pdev);
2519 kfree(card);
2520 return -ENODEV;
2521 }
2522 if ((card->ctlmem = ioremap(card->phys_ctlmem, 0x10)) == NULL) {
2523 printk_err("Control memory remap failed\n");
2524 pci_release_regions(pdev);
2525 pci_disable_device(pdev);
2526 kfree(card);
2527 return -ENODEV;
2528 }
2529 dbg(DBG_PCI, "kernel mem %p, ctlmem %p\n", card->mem, card->ctlmem);
2530
2531 /* Register the interrupt handler */
2532 if (request_irq(pdev->irq, fst_intr, SA_SHIRQ, FST_DEV_NAME, card)) {
2533 printk_err("Unable to register interrupt %d\n", card->irq);
2534 pci_release_regions(pdev);
2535 pci_disable_device(pdev);
2536 iounmap(card->ctlmem);
2537 iounmap(card->mem);
2538 kfree(card);
2539 return -ENODEV;
2540 }
2541
2542 /* Record info we need */
2543 card->irq = pdev->irq;
2544 card->type = ent->driver_data;
2545 card->family = ((ent->driver_data == FST_TYPE_T2P) ||
2546 (ent->driver_data == FST_TYPE_T4P))
2547 ? FST_FAMILY_TXP : FST_FAMILY_TXU;
2548 if ((ent->driver_data == FST_TYPE_T1U) ||
2549 (ent->driver_data == FST_TYPE_TE1))
2550 card->nports = 1;
2551 else
2552 card->nports = ((ent->driver_data == FST_TYPE_T2P) ||
2553 (ent->driver_data == FST_TYPE_T2U)) ? 2 : 4;
2554
2555 card->state = FST_UNINIT;
2556 card->device = pdev;
2557
2558 dbg(DBG_PCI, "type %d nports %d irq %d\n", card->type,
2559 card->nports, card->irq);
2560 dbg(DBG_PCI, "conf %04x mem %08x ctlmem %08x\n",
2561 card->pci_conf, card->phys_mem, card->phys_ctlmem);
2562
2563 /* Reset the card's processor */
2564 fst_cpureset(card);
2565 card->state = FST_RESET;
2566
2567 /* Initialise DMA (if required) */
2568 fst_init_dma(card);
2569
2570 /* Record driver data for later use */
2571 pci_set_drvdata(pdev, card);
2572
2573 /* Remainder of card setup */
2574 fst_card_array[no_of_cards_added] = card;
2575 card->card_no = no_of_cards_added++; /* Record instance and bump it */
2576 fst_init_card(card);
2577 if (card->family == FST_FAMILY_TXU) {
2578 /*
2579 * Allocate a dma buffer for transmit and receives
2580 */
2581 card->rx_dma_handle_host =
2582 pci_alloc_consistent(card->device, FST_MAX_MTU,
2583 &card->rx_dma_handle_card);
2584 if (card->rx_dma_handle_host == NULL) {
2585 printk_err("Could not allocate rx dma buffer\n");
2586 fst_disable_intr(card);
2587 pci_release_regions(pdev);
2588 pci_disable_device(pdev);
2589 iounmap(card->ctlmem);
2590 iounmap(card->mem);
2591 kfree(card);
2592 return -ENOMEM;
2593 }
2594 card->tx_dma_handle_host =
2595 pci_alloc_consistent(card->device, FST_MAX_MTU,
2596 &card->tx_dma_handle_card);
2597 if (card->tx_dma_handle_host == NULL) {
2598 printk_err("Could not allocate tx dma buffer\n");
2599 fst_disable_intr(card);
2600 pci_release_regions(pdev);
2601 pci_disable_device(pdev);
2602 iounmap(card->ctlmem);
2603 iounmap(card->mem);
2604 kfree(card);
2605 return -ENOMEM;
2606 }
2607 }
2608 return 0; /* Success */
2609 }
2610
2611 /*
2612 * Cleanup and close down a card
2613 */
2614 static void __devexit
fst_remove_one(struct pci_dev * pdev)2615 fst_remove_one(struct pci_dev *pdev)
2616 {
2617 struct fst_card_info *card;
2618 int i;
2619
2620 card = pci_get_drvdata(pdev);
2621
2622 for (i = 0; i < card->nports; i++) {
2623 unregister_hdlc_device(&card->ports[i].hdlc);
2624 }
2625
2626 fst_disable_intr(card);
2627 free_irq(card->irq, card);
2628
2629 iounmap(card->ctlmem);
2630 iounmap(card->mem);
2631
2632 pci_release_regions(pdev);
2633 #if 0
2634 release_mem_region(card->phys_ctlmem, 0x10);
2635 release_mem_region(card->phys_mem, FST_MEMSIZE);
2636 if (card->family == FST_FAMILY_TXU) {
2637 release_region(card->pci_conf, 0x100);
2638 } else {
2639 release_region(card->pci_conf, 0x80);
2640 }
2641 #endif
2642 if (card->family == FST_FAMILY_TXU) {
2643 /*
2644 * Free dma buffers
2645 */
2646 pci_free_consistent(card->device, FST_MAX_MTU,
2647 card->rx_dma_handle_host,
2648 card->rx_dma_handle_card);
2649 pci_free_consistent(card->device, FST_MAX_MTU,
2650 card->tx_dma_handle_host,
2651 card->tx_dma_handle_card);
2652 }
2653 fst_card_array[card->card_no] = NULL;
2654 }
2655
2656 static struct pci_driver fst_driver = {
2657 name:FST_NAME,
2658 id_table:fst_pci_dev_id,
2659 probe:fst_add_one,
2660 remove:__devexit_p(fst_remove_one),
2661 suspend:NULL,
2662 resume:NULL,
2663 };
2664
2665 static int __init
fst_init(void)2666 fst_init(void)
2667 {
2668 int i;
2669
2670 for (i = 0; i < FST_MAX_CARDS; i++)
2671 fst_card_array[i] = NULL;
2672 spin_lock_init(&fst_work_q_lock);
2673 return pci_module_init(&fst_driver);
2674 }
2675
2676 static void __exit
fst_cleanup_module(void)2677 fst_cleanup_module(void)
2678 {
2679 printk_info("FarSync WAN driver unloading\n");
2680 pci_unregister_driver(&fst_driver);
2681 }
2682
2683 module_init(fst_init);
2684 module_exit(fst_cleanup_module);
2685