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Searched refs:pciio_slot (Results 1 – 4 of 4) sorted by relevance

/linux-2.4.37.9/arch/ia64/sn/io/sn2/pcibr/
Dpcibr_rrb.c400 pciio_slot_t pciio_slot = PCIBR_INFO_SLOT_GET_INT(pciio_info); in pcibr_wrb_flush() local
405 wrb_flush = &(bridge->b_wr_req_buf[pciio_slot].reg); in pcibr_wrb_flush()
430 pciio_slot_t pciio_slot = PCIBR_INFO_SLOT_GET_INT(pciio_info); in pcibr_rrb_alloc() local
465 if (pcibr_soft->bs_rrb_valid_dflt[pciio_slot][VCHAN0] < 0) { in pcibr_rrb_alloc()
467 pcibr_soft->bs_rrb_valid_dflt[pciio_slot][vchan] = in pcibr_rrb_alloc()
468 pcibr_soft->bs_rrb_valid[pciio_slot][vchan]; in pcibr_rrb_alloc()
469 pcibr_soft->bs_rrb_res_dflt[pciio_slot] = in pcibr_rrb_alloc()
470 pcibr_soft->bs_rrb_res[pciio_slot]; in pcibr_rrb_alloc()
475 orig_vchan0 = pcibr_soft->bs_rrb_valid[pciio_slot][VCHAN0]; in pcibr_rrb_alloc()
476 orig_vchan1 = pcibr_soft->bs_rrb_valid[pciio_slot][VCHAN1]; in pcibr_rrb_alloc()
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Dpcibr_config.c153 pciio_slot_t pciio_slot; in pcibr_config_addr() local
173 pciio_slot = PCI_TYPE1_SLOT(reg); in pcibr_config_addr()
186 pciio_slot = PCIBR_INFO_SLOT_GET_INT(pcibr_info); in pcibr_config_addr()
187 if (pciio_slot == PCIIO_SLOT_NONE) in pcibr_config_addr()
188 pciio_slot = PCI_TYPE1_SLOT(reg); in pcibr_config_addr()
200 pciio_bus, pciio_slot, pciio_func, 0); in pcibr_config_addr()
Dpcibr_dvr.c2380 pciio_slot_t pciio_slot = PCIBR_INFO_SLOT_GET_INT(pciio_info); in pcibr_piomap_alloc() local
2403 xio_addr = pcibr_addr_pci_to_xio(pconn_vhdl, pciio_slot, space, pci_addr, req_size, flags); in pcibr_piomap_alloc()
2433 pcibr_piomap->bp_slot = PCIBR_DEVICE_TO_SLOT(pcibr_soft, pciio_slot); in pcibr_piomap_alloc()
2520 pciio_slot_t pciio_slot = PCIBR_INFO_SLOT_GET_INT(pciio_info); in pcibr_piotrans_addr() local
2527 xio_addr = pcibr_addr_pci_to_xio(pconn_vhdl, pciio_slot, space, pci_addr, req_size, flags); in pcibr_piotrans_addr()
3355 pciio_slot_t pciio_slot = PCIBR_INFO_SLOT_GET_INT(pciio_info);
3356 pcibr_soft_slot_t slotp = &pcibr_soft->bs_slot[pciio_slot];
3436 if (!pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D64_BITS)) {
3446 !(pcibr_soft->bs_rrb_fixed & (1 << pciio_slot))) {
3449 have_rrbs = pcibr_soft->bs_rrb_valid[pciio_slot][vchan];
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Dpcibr_intr.c301 pciio_slot_t pciio_slot = PCIBR_INFO_SLOT_GET_INT(pcibr_info); in pcibr_intr_alloc() local
422 int_dev |= pciio_slot << BRIDGE_INT_DEV_SHFT(pcibr_int_bit); in pcibr_intr_alloc()
456 intr_entry->il_wrbf = &(bridge->b_wr_req_buf[pciio_slot].reg); in pcibr_intr_alloc()