1 /*
2 *
3 * This file is subject to the terms and conditions of the GNU General Public
4 * License. See the file "COPYING" in the main directory of this archive
5 * for more details.
6 *
7 * Copyright (C) 2001-2003 Silicon Graphics, Inc. All rights reserved.
8 */
9
10 #include <linux/types.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/pci.h>
14 #include <asm/sn/sgi.h>
15 #include <asm/uaccess.h>
16 #include <asm/sn/sn_cpuid.h>
17 #include <asm/sn/addrs.h>
18 #include <asm/sn/arch.h>
19 #include <asm/sn/iograph.h>
20 #include <asm/sn/invent.h>
21 #include <asm/sn/hcl.h>
22 #include <asm/sn/labelcl.h>
23 #include <asm/sn/xtalk/xwidget.h>
24 #include <asm/sn/pci/bridge.h>
25 #include <asm/sn/pci/pciio.h>
26 #include <asm/sn/pci/pcibr.h>
27 #include <asm/sn/pci/pcibr_private.h>
28 #include <asm/sn/pci/pci_defs.h>
29 #include <asm/sn/prio.h>
30 #include <asm/sn/xtalk/xbow.h>
31 #include <asm/sn/ioc3.h>
32 #include <asm/sn/io.h>
33 #include <asm/sn/sn_private.h>
34
35 extern pcibr_info_t pcibr_info_get(vertex_hdl_t);
36 extern int pcibr_widget_to_bus(vertex_hdl_t pcibr_vhdl);
37 extern pcibr_info_t pcibr_device_info_new(pcibr_soft_t, pciio_slot_t, pciio_function_t, pciio_vendor_id_t, pciio_device_id_t);
38 extern int pcibr_slot_initial_rrb_alloc(vertex_hdl_t,pciio_slot_t);
39 extern int pcibr_pcix_rbars_calc(pcibr_soft_t);
40
41 int pcibr_slot_info_init(vertex_hdl_t pcibr_vhdl, pciio_slot_t slot);
42 int pcibr_slot_info_free(vertex_hdl_t pcibr_vhdl, pciio_slot_t slot);
43 int pcibr_slot_addr_space_init(vertex_hdl_t pcibr_vhdl, pciio_slot_t slot);
44 int pcibr_slot_pcix_rbar_init(pcibr_soft_t pcibr_soft, pciio_slot_t slot);
45 int pcibr_slot_device_init(vertex_hdl_t pcibr_vhdl, pciio_slot_t slot);
46 int pcibr_slot_guest_info_init(vertex_hdl_t pcibr_vhdl, pciio_slot_t slot);
47 int pcibr_slot_call_device_attach(vertex_hdl_t pcibr_vhdl,
48 pciio_slot_t slot, int drv_flags);
49 int pcibr_slot_call_device_detach(vertex_hdl_t pcibr_vhdl,
50 pciio_slot_t slot, int drv_flags);
51 int pcibr_slot_detach(vertex_hdl_t pcibr_vhdl, pciio_slot_t slot,
52 int drv_flags, char *l1_msg, int *sub_errorp);
53 static int pcibr_probe_slot(bridge_t *, cfg_p, unsigned int *);
54 void pcibr_device_info_free(vertex_hdl_t, pciio_slot_t);
55 iopaddr_t pcibr_bus_addr_alloc(pcibr_soft_t, pciio_win_info_t,
56 pciio_space_t, int, int, int);
57 void pciibr_bus_addr_free(pcibr_soft_t, pciio_win_info_t);
58 cfg_p pcibr_find_capability(cfg_p, unsigned);
59 extern uint64_t do_pcibr_config_get(cfg_p, unsigned, unsigned);
60 void do_pcibr_config_set(cfg_p, unsigned, unsigned, uint64_t);
61
62 int pcibr_slot_attach(vertex_hdl_t pcibr_vhdl, pciio_slot_t slot,
63 int drv_flags, char *l1_msg, int *sub_errorp);
64
65 int pcibr_slot_info_return(pcibr_soft_t pcibr_soft, pciio_slot_t slot,
66 pcibr_slot_info_resp_t respp);
67
68 extern vertex_hdl_t baseio_pci_vhdl;
69 int scsi_ctlr_nums_add(vertex_hdl_t, vertex_hdl_t);
70
71
72 /* For now .... */
73 /*
74 * PCI Hot-Plug Capability Flags
75
76 */
77 #define D_PCI_HOT_PLUG_ATTACH 0x200 /* Driver supports PCI hot-plug attach */
78 #define D_PCI_HOT_PLUG_DETACH 0x400 /* Driver supports PCI hot-plug detach */
79
80
81 /*
82 * PCI-X Max Outstanding Split Transactions translation array and Max Memory
83 * Read Byte Count translation array, as defined in the PCI-X Specification.
84 * Section 7.2.3 & 7.2.4 of PCI-X Specification - rev 1.0
85 */
86 #define MAX_SPLIT_TABLE 8
87 #define MAX_READCNT_TABLE 4
88 int max_splittrans_to_numbuf[MAX_SPLIT_TABLE] = {1, 2, 3, 4, 8, 12, 16, 32};
89 int max_readcount_to_bufsize[MAX_READCNT_TABLE] = {512, 1024, 2048, 4096 };
90
91
92 #define COPYOUT(a, b, c) copy_to_user(b,a,c)
93
94 /*==========================================================================
95 * BRIDGE PCI SLOT RELATED IOCTLs
96 */
97
98 /*
99 * pcibr_slot_startup
100 * Software start-up the PCI slot.
101 */
102
103 #ifdef PIC_LATER
104
105 int
pcibr_slot_startup(vertex_hdl_t pcibr_vhdl,pcibr_slot_req_t reqp)106 pcibr_slot_startup(vertex_hdl_t pcibr_vhdl, pcibr_slot_req_t reqp)
107 {
108 pcibr_soft_t pcibr_soft = pcibr_soft_get(pcibr_vhdl);
109 pciio_slot_t slot;
110 int error = 0;
111 char l1_msg[BRL1_QSIZE+1];
112 struct pcibr_slot_up_resp_s tmp_up_resp;
113
114 /* Make sure that we are dealing with a bridge device vertex */
115 if (!pcibr_soft) {
116 return(PCI_NOT_A_BRIDGE);
117 }
118
119 /* req_slot is the 'external' slot number, convert for internal use */
120 slot = PCIBR_SLOT_TO_DEVICE(pcibr_soft, reqp->req_slot);
121
122 /* Check for the valid slot */
123 if (!PCIBR_VALID_SLOT(pcibr_soft, slot))
124 return(PCI_NOT_A_SLOT);
125
126 #ifdef PIC_LATER
127 /* Acquire update access to the bus */
128 mrlock(pcibr_soft->bs_bus_lock, MR_UPDATE, PZERO);
129 #endif
130
131 if (pcibr_soft->bs_slot[slot].slot_status & SLOT_STARTUP_CMPLT) {
132 error = PCI_SLOT_ALREADY_UP;
133 goto startup_unlock;
134 }
135
136 error = pcibr_slot_attach(pcibr_vhdl, slot, D_PCI_HOT_PLUG_ATTACH,
137 l1_msg, &tmp_up_resp.resp_sub_errno);
138
139 strncpy(tmp_up_resp.resp_l1_msg, l1_msg, L1_QSIZE);
140 tmp_up_resp.resp_l1_msg[L1_QSIZE] = '\0';
141
142 if (COPYOUT(&tmp_up_resp, reqp->req_respp.up, reqp->req_size)) {
143 return(EFAULT);
144 }
145
146 startup_unlock:
147
148 #ifdef PIC_LATER
149 /* Release the bus lock */
150 mrunlock(pcibr_soft->bs_bus_lock);
151 #endif
152 return(error);
153 }
154
155 /*
156 * pcibr_slot_shutdown
157 * Software shut-down the PCI slot
158 */
159 int
pcibr_slot_shutdown(vertex_hdl_t pcibr_vhdl,pcibr_slot_req_t reqp)160 pcibr_slot_shutdown(vertex_hdl_t pcibr_vhdl, pcibr_slot_req_t reqp)
161 {
162 pcibr_soft_t pcibr_soft = pcibr_soft_get(pcibr_vhdl);
163 bridge_t *bridge;
164 pciio_slot_t slot;
165 int error = 0;
166 char l1_msg[BRL1_QSIZE+1];
167 struct pcibr_slot_down_resp_s tmp_down_resp;
168 pciio_slot_t tmp_slot;
169
170 /* Make sure that we are dealing with a bridge device vertex */
171 if (!pcibr_soft) {
172 return(PCI_NOT_A_BRIDGE);
173 }
174
175 /* req_slot is the 'external' slot number, convert for internal use */
176 slot = PCIBR_SLOT_TO_DEVICE(pcibr_soft, reqp->req_slot);
177
178 bridge = pcibr_soft->bs_base;
179
180 /* Check for valid slot */
181 if (!PCIBR_VALID_SLOT(pcibr_soft, slot))
182 return(PCI_NOT_A_SLOT);
183
184 #ifdef PIC_LATER
185 /* Acquire update access to the bus */
186 mrlock(pcibr_soft->bs_bus_lock, MR_UPDATE, PZERO);
187 #endif
188
189 if ((pcibr_soft->bs_slot[slot].slot_status & SLOT_SHUTDOWN_CMPLT) ||
190 ((pcibr_soft->bs_slot[slot].slot_status & SLOT_STATUS_MASK) == 0)) {
191 error = PCI_SLOT_ALREADY_DOWN;
192 /*
193 * RJR - Should we invoke an L1 slot power-down command just in case
194 * a previous shut-down failed to power-down the slot?
195 */
196 goto shutdown_unlock;
197 }
198
199 /* Do not allow a multi-function card to be hot-plug removed */
200 if (pcibr_soft->bs_slot[slot].bss_ninfo > 1) {
201 tmp_down_resp.resp_sub_errno = EPERM;
202 error = PCI_MULTI_FUNC_ERR;
203 goto shutdown_copyout;
204 }
205
206 /* Do not allow the last 33 MHz card to be removed */
207 if ((bridge->b_wid_control & BRIDGE_CTRL_BUS_SPEED_MASK) ==
208 BRIDGE_CTRL_BUS_SPEED_33) {
209 for (tmp_slot = pcibr_soft->bs_first_slot;
210 tmp_slot <= pcibr_soft->bs_last_slot; tmp_slot++)
211 if (tmp_slot != slot)
212 if (pcibr_soft->bs_slot[tmp_slot].slot_status & SLOT_POWER_UP) {
213 error++;
214 break;
215 }
216 if (!error) {
217 error = PCI_EMPTY_33MHZ;
218 goto shutdown_unlock;
219 }
220 }
221
222 error = pcibr_slot_detach(pcibr_vhdl, slot, D_PCI_HOT_PLUG_DETACH,
223 l1_msg, &tmp_down_resp.resp_sub_errno);
224
225 strncpy(tmp_down_resp.resp_l1_msg, l1_msg, L1_QSIZE);
226 tmp_down_resp.resp_l1_msg[L1_QSIZE] = '\0';
227
228 shutdown_copyout:
229
230 if (COPYOUT(&tmp_down_resp, reqp->req_respp.down, reqp->req_size)) {
231 return(EFAULT);
232 }
233
234 shutdown_unlock:
235
236 #ifdef PIC_LATER
237 /* Release the bus lock */
238 mrunlock(pcibr_soft->bs_bus_lock);
239 #endif
240
241 return(error);
242 }
243 #endif /* PIC_LATER */
244
245 char *pci_space_name[] = {"NONE",
246 "ROM",
247 "IO",
248 "",
249 "MEM",
250 "MEM32",
251 "MEM64",
252 "CFG",
253 "WIN0",
254 "WIN1",
255 "WIN2",
256 "WIN3",
257 "WIN4",
258 "WIN5",
259 "",
260 "BAD"};
261
262 void
pcibr_slot_func_info_return(pcibr_info_h pcibr_infoh,int func,pcibr_slot_func_info_resp_t funcp)263 pcibr_slot_func_info_return(pcibr_info_h pcibr_infoh,
264 int func,
265 pcibr_slot_func_info_resp_t funcp)
266 {
267 pcibr_info_t pcibr_info = pcibr_infoh[func];
268 int win;
269
270 funcp->resp_f_status = 0;
271
272 if (!pcibr_info) {
273 return;
274 }
275
276 funcp->resp_f_status |= FUNC_IS_VALID;
277 #if defined(SUPPORT_PRINTING_V_FORMAT)
278 sprintf(funcp->resp_f_slot_name, "%v", pcibr_info->f_vertex);
279 #endif
280
281 funcp->resp_f_bus = pcibr_info->f_bus;
282 funcp->resp_f_slot = PCIBR_INFO_SLOT_GET_EXT(pcibr_info);
283 funcp->resp_f_func = pcibr_info->f_func;
284 #if defined(SUPPORT_PRINTING_V_FORMAT)
285 sprintf(funcp->resp_f_master_name, "%v", pcibr_info->f_master);
286 #endif
287 funcp->resp_f_pops = pcibr_info->f_pops;
288 funcp->resp_f_efunc = pcibr_info->f_efunc;
289 funcp->resp_f_einfo = pcibr_info->f_einfo;
290
291 funcp->resp_f_vendor = pcibr_info->f_vendor;
292 funcp->resp_f_device = pcibr_info->f_device;
293
294 for(win = 0 ; win < 6 ; win++) {
295 funcp->resp_f_window[win].resp_w_base =
296 pcibr_info->f_window[win].w_base;
297 funcp->resp_f_window[win].resp_w_size =
298 pcibr_info->f_window[win].w_size;
299 sprintf(funcp->resp_f_window[win].resp_w_space,
300 "%s",
301 pci_space_name[pcibr_info->f_window[win].w_space]);
302 }
303
304 funcp->resp_f_rbase = pcibr_info->f_rbase;
305 funcp->resp_f_rsize = pcibr_info->f_rsize;
306
307 for (win = 0 ; win < 4; win++) {
308 funcp->resp_f_ibit[win] = pcibr_info->f_ibit[win];
309 }
310
311 funcp->resp_f_att_det_error = pcibr_info->f_att_det_error;
312
313 }
314
315 int
pcibr_slot_info_return(pcibr_soft_t pcibr_soft,pciio_slot_t slot,pcibr_slot_info_resp_t respp)316 pcibr_slot_info_return(pcibr_soft_t pcibr_soft,
317 pciio_slot_t slot,
318 pcibr_slot_info_resp_t respp)
319 {
320 pcibr_soft_slot_t pss;
321 int func;
322 bridge_t *bridge = pcibr_soft->bs_base;
323 reg_p b_respp;
324 pcibr_slot_info_resp_t slotp;
325 pcibr_slot_func_info_resp_t funcp;
326
327 slotp = snia_kmem_zalloc(sizeof(*slotp));
328 if (slotp == NULL) {
329 return(ENOMEM);
330 }
331
332 pss = &pcibr_soft->bs_slot[slot];
333
334 slotp->resp_bs_bridge_mode = pcibr_soft->bs_bridge_mode;
335 slotp->resp_bs_bridge_type = pcibr_soft->bs_bridge_type;
336
337 slotp->resp_has_host = pss->has_host;
338 slotp->resp_host_slot = pss->host_slot;
339 #if defined(SUPPORT_PRINTING_V_FORMAT)
340 sprintf(slotp->resp_slot_conn_name, "%v", pss->slot_conn);
341 #else
342 sprintf(slotp->resp_slot_conn_name, "%p", (void *)pss->slot_conn);
343 #endif
344 slotp->resp_slot_status = pss->slot_status;
345
346 slotp->resp_l1_bus_num = pcibr_widget_to_bus(pcibr_soft->bs_vhdl);
347 slotp->resp_bss_ninfo = pss->bss_ninfo;
348
349 for (func = 0; func < pss->bss_ninfo; func++) {
350 funcp = &(slotp->resp_func[func]);
351 pcibr_slot_func_info_return(pss->bss_infos, func, funcp);
352 }
353
354 sprintf(slotp->resp_bss_devio_bssd_space, "%s",
355 pci_space_name[pss->bss_devio.bssd_space]);
356 slotp->resp_bss_devio_bssd_base = pss->bss_devio.bssd_base;
357 slotp->resp_bss_device = pss->bss_device;
358
359 slotp->resp_bss_pmu_uctr = pss->bss_pmu_uctr;
360 slotp->resp_bss_d32_uctr = pss->bss_d32_uctr;
361 slotp->resp_bss_d64_uctr = pss->bss_d64_uctr;
362
363 slotp->resp_bss_d64_base = pss->bss_d64_base;
364 slotp->resp_bss_d64_flags = pss->bss_d64_flags;
365 slotp->resp_bss_d32_base = pss->bss_d32_base;
366 slotp->resp_bss_d32_flags = pss->bss_d32_flags;
367
368 slotp->resp_bss_ext_ates_active = pss->bss_ext_ates_active;
369
370 slotp->resp_bss_cmd_pointer = pss->bss_cmd_pointer;
371 slotp->resp_bss_cmd_shadow = pss->bss_cmd_shadow;
372
373 slotp->resp_bs_rrb_valid = pcibr_soft->bs_rrb_valid[slot][VCHAN0];
374 slotp->resp_bs_rrb_valid_v1 = pcibr_soft->bs_rrb_valid[slot][VCHAN1];
375 slotp->resp_bs_rrb_valid_v2 = pcibr_soft->bs_rrb_valid[slot][VCHAN2];
376 slotp->resp_bs_rrb_valid_v3 = pcibr_soft->bs_rrb_valid[slot][VCHAN3];
377 slotp->resp_bs_rrb_res = pcibr_soft->bs_rrb_res[slot];
378
379 if (slot & 1) {
380 b_respp = &bridge->b_odd_resp;
381 } else {
382 b_respp = &bridge->b_even_resp;
383 }
384
385 slotp->resp_b_resp = *b_respp;
386
387 slotp->resp_b_int_device = bridge->b_int_device;
388
389 if (IS_PIC_SOFT(pcibr_soft)) {
390 slotp->resp_p_int_enable = bridge->p_int_enable_64;
391 slotp->resp_p_int_host = bridge->p_int_addr_64[slot];
392 } else {
393 slotp->resp_b_int_enable = bridge->b_int_enable;
394 slotp->resp_b_int_host = bridge->b_int_addr[slot].addr;
395 }
396
397 if (COPYOUT(slotp, respp, sizeof(*respp))) {
398 return(EFAULT);
399 }
400
401 snia_kmem_free(slotp, sizeof(*slotp));
402
403 return(0);
404 }
405
406 /*
407 * pcibr_slot_query
408 * Return information about the PCI slot maintained by the infrastructure.
409 * Information is requested in the request structure.
410 *
411 * Information returned in the response structure:
412 * Slot hwgraph name
413 * Vendor/Device info
414 * Base register info
415 * Interrupt mapping from device pins to the bridge pins
416 * Devio register
417 * Software RRB info
418 * RRB register info
419 * Host/Gues info
420 * PCI Bus #,slot #, function #
421 * Slot provider hwgraph name
422 * Provider Functions
423 * Error handler
424 * DMA mapping usage counters
425 * DMA direct translation info
426 * External SSRAM workaround info
427 */
428 int
pcibr_slot_query(vertex_hdl_t pcibr_vhdl,pcibr_slot_req_t reqp)429 pcibr_slot_query(vertex_hdl_t pcibr_vhdl, pcibr_slot_req_t reqp)
430 {
431 pcibr_soft_t pcibr_soft = pcibr_soft_get(pcibr_vhdl);
432 pciio_slot_t slot;
433 pciio_slot_t tmp_slot;
434 pcibr_slot_info_resp_t respp = reqp->req_respp.query;
435 int size = reqp->req_size;
436 int error = 0;
437
438 /* Make sure that we are dealing with a bridge device vertex */
439 if (!pcibr_soft) {
440 return(PCI_NOT_A_BRIDGE);
441 }
442
443 /* req_slot is the 'external' slot number, convert for internal use */
444 slot = PCIBR_SLOT_TO_DEVICE(pcibr_soft, reqp->req_slot);
445
446 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_HOTPLUG, pcibr_vhdl,
447 "pcibr_slot_query: pcibr_soft=0x%x, slot=%d, reqp=0x%x\n",
448 pcibr_soft, slot, reqp));
449
450 /* Make sure that we have a valid PCI slot number or PCIIO_SLOT_NONE */
451 if ((!PCIBR_VALID_SLOT(pcibr_soft, slot)) && (slot != PCIIO_SLOT_NONE)) {
452 return(PCI_NOT_A_SLOT);
453 }
454
455 /* Return information for the requested PCI slot */
456 if (slot != PCIIO_SLOT_NONE) {
457 if (size < sizeof(*respp)) {
458 return(PCI_RESP_AREA_TOO_SMALL);
459 }
460
461 #ifdef PIC_LATER
462 /* Acquire read access to the bus */
463 mrlock(pcibr_soft->bs_bus_lock, MR_ACCESS, PZERO);
464 #endif
465 error = pcibr_slot_info_return(pcibr_soft, slot, respp);
466
467 #ifdef PIC_LATER
468 /* Release the bus lock */
469 mrunlock(pcibr_soft->bs_bus_lock);
470 #endif
471 return(error);
472 }
473
474 /* Return information for all the slots */
475 for (tmp_slot = pcibr_soft->bs_min_slot;
476 tmp_slot < PCIBR_NUM_SLOTS(pcibr_soft); tmp_slot++) {
477
478 if (size < sizeof(*respp)) {
479 return(PCI_RESP_AREA_TOO_SMALL);
480 }
481
482 #ifdef PIC_LATER
483 /* Acquire read access to the bus */
484 mrlock(pcibr_soft->bs_bus_lock, MR_ACCESS, PZERO);
485 #endif
486 error = pcibr_slot_info_return(pcibr_soft, tmp_slot, respp);
487
488 #ifdef PCI_LATER
489 /* Release the bus lock */
490 mrunlock(pcibr_soft->bs_bus_lock);
491 #endif
492 if (error) {
493 return(error);
494 }
495
496 ++respp;
497 size -= sizeof(*respp);
498 }
499
500 return(error);
501 }
502
503 #define PROBE_LOCK 0 /* FIXME: we're attempting to lock around accesses
504 * to b_int_enable. This hangs pcibr_probe_slot()
505 */
506
507 /*
508 * pcibr_slot_info_init
509 * Probe for this slot and see if it is populated.
510 * If it is populated initialize the generic PCI infrastructural
511 * information associated with this particular PCI device.
512 */
513 int
pcibr_slot_info_init(vertex_hdl_t pcibr_vhdl,pciio_slot_t slot)514 pcibr_slot_info_init(vertex_hdl_t pcibr_vhdl,
515 pciio_slot_t slot)
516 {
517 pcibr_soft_t pcibr_soft;
518 pcibr_info_h pcibr_infoh;
519 pcibr_info_t pcibr_info;
520 bridge_t *bridge;
521 cfg_p cfgw;
522 unsigned idword;
523 unsigned pfail;
524 unsigned idwords[8];
525 pciio_vendor_id_t vendor;
526 pciio_device_id_t device;
527 unsigned htype;
528 unsigned lt_time;
529 int nbars;
530 cfg_p wptr;
531 cfg_p pcix_cap;
532 int win;
533 pciio_space_t space;
534 int nfunc;
535 pciio_function_t rfunc;
536 int func;
537 vertex_hdl_t conn_vhdl;
538 pcibr_soft_slot_t slotp;
539
540 /* Get the basic software information required to proceed */
541 pcibr_soft = pcibr_soft_get(pcibr_vhdl);
542 if (!pcibr_soft)
543 return(EINVAL);
544
545 bridge = pcibr_soft->bs_base;
546 if (!PCIBR_VALID_SLOT(pcibr_soft, slot))
547 return(EINVAL);
548
549 /* If we have a host slot (eg:- IOC3 has 2 PCI slots and the initialization
550 * is done by the host slot then we are done.
551 */
552 if (pcibr_soft->bs_slot[slot].has_host) {
553 return(0);
554 }
555
556 /* Try to read the device-id/vendor-id from the config space */
557 cfgw = pcibr_slot_config_addr(bridge, slot, 0);
558
559 #if PROBE_LOCK
560 s = pcibr_lock(pcibr_soft);
561 #endif
562 if (pcibr_probe_slot(bridge, cfgw, &idword))
563 return(ENODEV);
564 #if PROBE_LOCK
565 pcibr_unlock(pcibr_soft, s);
566 #endif
567
568 slotp = &pcibr_soft->bs_slot[slot];
569 slotp->slot_status |= SLOT_POWER_UP;
570
571 vendor = 0xFFFF & idword;
572 device = 0xFFFF & (idword >> 16);
573
574 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_PROBE, pcibr_vhdl,
575 "pcibr_slot_info_init: slot=%d, vendor=0x%x, device=0x%x\n",
576 PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), vendor, device));
577
578 /* If the vendor id is not valid then the slot is not populated
579 * and we are done.
580 */
581 if (vendor == 0xFFFF)
582 return(ENODEV);
583
584 htype = do_pcibr_config_get(cfgw, PCI_CFG_HEADER_TYPE, 1);
585 nfunc = 1;
586 rfunc = PCIIO_FUNC_NONE;
587 pfail = 0;
588
589 /* NOTE: if a card claims to be multifunction
590 * but only responds to config space 0, treat
591 * it as a unifunction card.
592 */
593
594 if (htype & 0x80) { /* MULTIFUNCTION */
595 for (func = 1; func < 8; ++func) {
596 cfgw = pcibr_func_config_addr(bridge, 0, slot, func, 0);
597 #if PROBE_LOCK
598 s = pcibr_lock(pcibr_soft);
599 #endif
600 if (pcibr_probe_slot(bridge, cfgw, &idwords[func])) {
601 pfail |= 1 << func;
602 continue;
603 }
604 #if PROBE_LOCK
605 pcibr_unlock(pcibr_soft, s);
606 #endif
607 vendor = 0xFFFF & idwords[func];
608 if (vendor == 0xFFFF) {
609 pfail |= 1 << func;
610 continue;
611 }
612 nfunc = func + 1;
613 rfunc = 0;
614 }
615 cfgw = pcibr_slot_config_addr(bridge, slot, 0);
616 }
617 NEWA(pcibr_infoh, nfunc);
618
619 pcibr_soft->bs_slot[slot].bss_ninfo = nfunc;
620 pcibr_soft->bs_slot[slot].bss_infos = pcibr_infoh;
621
622 for (func = 0; func < nfunc; ++func) {
623 unsigned cmd_reg;
624
625 if (func) {
626 if (pfail & (1 << func))
627 continue;
628
629 idword = idwords[func];
630 cfgw = pcibr_func_config_addr(bridge, 0, slot, func, 0);
631
632 device = 0xFFFF & (idword >> 16);
633 htype = do_pcibr_config_get(cfgw, PCI_CFG_HEADER_TYPE, 1);
634 rfunc = func;
635 }
636 htype &= 0x7f;
637 if (htype != 0x00) {
638 printk(KERN_WARNING
639 "%s pcibr: pci slot %d func %d has strange header type 0x%x\n",
640 pcibr_soft->bs_name, slot, func, htype);
641 nbars = 2;
642 } else {
643 nbars = PCI_CFG_BASE_ADDRS;
644 }
645
646 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_CONFIG, pcibr_vhdl,
647 "pcibr_slot_info_init: slot=%d, func=%d, cfgw=0x%x\n",
648 PCIBR_DEVICE_TO_SLOT(pcibr_soft,slot), func, cfgw));
649
650 #ifdef PIC_LATER
651 /*
652 * Check for a Quad ATM PCI "card" and return all the PCI bus
653 * memory and I/O space. This will work-around an apparent
654 * hardware problem with the Quad ATM XIO card handling large
655 * PIO addresses. Releasing all the space for use by the card
656 * will lower the PIO addresses with the PCI bus address space.
657 * This is OK since the PROM did not assign any BAR addresses.
658 *
659 * Only release all the PCI bus addresses once.
660 *
661 */
662 if ((vendor == LINC_VENDOR_ID_NUM) && (device == LINC_DEVICE_ID_NUM)) {
663 iopaddr_t prom_base_addr = pcibr_soft->bs_xid << 24;
664 int prom_base_size = 0x1000000;
665
666 if (!(pcibr_soft->bs_bus_addr_status & PCIBR_BUS_ADDR_MEM_FREED)) {
667 pciio_device_win_populate(&pcibr_soft->bs_mem_win_map,
668 prom_base_addr, prom_base_size);
669 pcibr_soft->bs_bus_addr_status |= PCIBR_BUS_ADDR_MEM_FREED;
670 }
671
672 if (!(pcibr_soft->bs_bus_addr_status & PCIBR_BUS_ADDR_IO_FREED)) {
673 pciio_device_win_populate(&pcibr_soft->bs_io_win_map,
674 prom_base_addr, prom_base_size);
675 pcibr_soft->bs_bus_addr_status |= PCIBR_BUS_ADDR_IO_FREED;
676 }
677 }
678 #endif /* PIC_LATER */
679
680 /*
681 * If the latency timer has already been set, by prom or by the
682 * card itself, use that value. Otherwise look at the device's
683 * 'min_gnt' and attempt to calculate a latency time.
684 *
685 * NOTE: For now if the device is on the 'real time' arbitration
686 * ring we don't set the latency timer.
687 *
688 * WAR: SGI's IOC3 and RAD devices target abort if you write a
689 * single byte into their config space. So don't set the Latency
690 * Timer for these devices
691 */
692
693 lt_time = do_pcibr_config_get(cfgw, PCI_CFG_LATENCY_TIMER, 1);
694
695 if ((lt_time == 0) && !(bridge->b_device[slot].reg & BRIDGE_DEV_RT) &&
696 (device == 0x5 /* RAD_DEV */)) {
697 unsigned min_gnt;
698 unsigned min_gnt_mult;
699
700 /* 'min_gnt' indicates how long of a burst period a device
701 * needs in increments of 250ns. But latency timer is in
702 * PCI clock cycles, so a conversion is needed.
703 */
704 min_gnt = do_pcibr_config_get(cfgw, PCI_MIN_GNT, 1);
705
706 if (IS_133MHZ(pcibr_soft))
707 min_gnt_mult = 32; /* 250ns @ 133MHz in clocks */
708 else if (IS_100MHZ(pcibr_soft))
709 min_gnt_mult = 24; /* 250ns @ 100MHz in clocks */
710 else if (IS_66MHZ(pcibr_soft))
711 min_gnt_mult = 16; /* 250ns @ 66MHz, in clocks */
712 else
713 min_gnt_mult = 8; /* 250ns @ 33MHz, in clocks */
714
715 if ((min_gnt != 0) && ((min_gnt * min_gnt_mult) < 256))
716 lt_time = (min_gnt * min_gnt_mult);
717 else
718 lt_time = 4 * min_gnt_mult; /* 1 micro second */
719
720 do_pcibr_config_set(cfgw, PCI_CFG_LATENCY_TIMER, 1, lt_time);
721
722 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_CONFIG, pcibr_vhdl,
723 "pcibr_slot_info_init: set Latency Timer for slot=%d, "
724 "func=%d, to 0x%x\n",
725 PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), func, lt_time));
726 }
727
728
729 /* In our architecture the setting of the cacheline size isn't
730 * beneficial for cards in PCI mode, but in PCI-X mode devices
731 * can optionally use the cacheline size value for internal
732 * device optimizations (See 7.1.5 of the PCI-X v1.0 spec).
733 * NOTE: cachline size is in doubleword increments
734 */
735 if (IS_PCIX(pcibr_soft)) {
736 if (!do_pcibr_config_get(cfgw, PCI_CFG_CACHE_LINE, 1)) {
737 do_pcibr_config_set(cfgw, PCI_CFG_CACHE_LINE, 1, 0x20);
738 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_CONFIG, pcibr_vhdl,
739 "pcibr_slot_info_init: set CacheLine for slot=%d, "
740 "func=%d, to 0x20\n",
741 PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), func));
742 }
743
744 /* Get the PCI-X capability if running in PCI-X mode. If the func
745 * doesnt have a pcix capability, allocate a PCIIO_VENDOR_ID_NONE
746 * pcibr_info struct so the device driver for that function is not
747 * called.
748 */
749 if (!(pcix_cap = pcibr_find_capability(cfgw, PCI_CAP_PCIX))) {
750 printk(KERN_WARNING
751 #if defined(SUPPORT_PRINTING_V_FORMAT)
752 "%v: Bus running in PCI-X mode, But card in slot %d, "
753 "func %d not PCI-X capable\n", pcibr_vhdl, slot, func);
754 #else
755 "0x%lx: Bus running in PCI-X mode, But card in slot %d, "
756 "func %d not PCI-X capable\n", (unsigned long)pcibr_vhdl, slot, func);
757 #endif
758 pcibr_device_info_new(pcibr_soft, slot, PCIIO_FUNC_NONE,
759 PCIIO_VENDOR_ID_NONE, PCIIO_DEVICE_ID_NONE);
760 continue;
761 }
762 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_CONFIG, pcibr_vhdl,
763 "pcibr_slot_info_init: PCI-X capability at 0x%x for "
764 "slot=%d, func=%d\n",
765 pcix_cap, PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), func));
766 } else {
767 pcix_cap = NULL;
768 }
769
770 pcibr_info = pcibr_device_info_new
771 (pcibr_soft, slot, rfunc, vendor, device);
772
773 /* Keep a running total of the number of PIC-X functions on the bus
774 * and the number of max outstanding split trasnactions that they
775 * have requested. NOTE: "pcix_cap != NULL" implies IS_PCIX()
776 */
777 pcibr_info->f_pcix_cap = (cap_pcix_type0_t *)pcix_cap;
778 if (pcibr_info->f_pcix_cap) {
779 int max_out; /* max outstanding splittrans from status reg */
780
781 pcibr_soft->bs_pcix_num_funcs++;
782 max_out = pcibr_info->f_pcix_cap->pcix_type0_status.max_out_split;
783 pcibr_soft->bs_pcix_split_tot += max_splittrans_to_numbuf[max_out];
784 }
785
786 conn_vhdl = pciio_device_info_register(pcibr_vhdl, &pcibr_info->f_c);
787 if (func == 0)
788 slotp->slot_conn = conn_vhdl;
789
790 cmd_reg = do_pcibr_config_get(cfgw, PCI_CFG_COMMAND, 4);
791
792 wptr = cfgw + PCI_CFG_BASE_ADDR_0 / 4;
793
794 for (win = 0; win < nbars; ++win) {
795 iopaddr_t base, mask, code;
796 size_t size;
797
798 /*
799 * GET THE BASE & SIZE OF THIS WINDOW:
800 *
801 * The low two or four bits of the BASE register
802 * determines which address space we are in; the
803 * rest is a base address. BASE registers
804 * determine windows that are power-of-two sized
805 * and naturally aligned, so we can get the size
806 * of a window by writing all-ones to the
807 * register, reading it back, and seeing which
808 * bits are used for decode; the least
809 * significant nonzero bit is also the size of
810 * the window.
811 *
812 * WARNING: someone may already have allocated
813 * some PCI space to this window, and in fact
814 * PIO may be in process at this very moment
815 * from another processor (or even from this
816 * one, if we get interrupted)! So, if the BASE
817 * already has a nonzero address, be generous
818 * and use the LSBit of that address as the
819 * size; this could overstate the window size.
820 * Usually, when one card is set up, all are set
821 * up; so, since we don't bitch about
822 * overlapping windows, we are ok.
823 *
824 * UNFORTUNATELY, some cards do not clear their
825 * BASE registers on reset. I have two heuristics
826 * that can detect such cards: first, if the
827 * decode enable is turned off for the space
828 * that the window uses, we can disregard the
829 * initial value. second, if the address is
830 * outside the range that we use, we can disregard
831 * it as well.
832 *
833 * This is looking very PCI generic. Except for
834 * knowing how many slots and where their config
835 * spaces are, this window loop and the next one
836 * could probably be shared with other PCI host
837 * adapters. It would be interesting to see if
838 * this could be pushed up into pciio, when we
839 * start supporting more PCI providers.
840 */
841 base = do_pcibr_config_get(wptr, (win * 4), 4);
842
843 if (base & PCI_BA_IO_SPACE) {
844 /* BASE is in I/O space. */
845 space = PCIIO_SPACE_IO;
846 mask = -4;
847 code = base & 3;
848 base = base & mask;
849 if (base == 0) {
850 ; /* not assigned */
851 } else if (!(cmd_reg & PCI_CMD_IO_SPACE)) {
852 base = 0; /* decode not enabled */
853 }
854 } else {
855 /* BASE is in MEM space. */
856 space = PCIIO_SPACE_MEM;
857 mask = -16;
858 code = base & PCI_BA_MEM_LOCATION; /* extract BAR type */
859 base = base & mask;
860 if (base == 0) {
861 ; /* not assigned */
862 } else if (!(cmd_reg & PCI_CMD_MEM_SPACE)) {
863 base = 0; /* decode not enabled */
864 } else if (base & 0xC0000000) {
865 base = 0; /* outside permissable range */
866 } else if ((code == PCI_BA_MEM_64BIT) &&
867 (do_pcibr_config_get(wptr, ((win + 1)*4), 4) != 0)) {
868 base = 0; /* outside permissable range */
869 }
870 }
871
872 if (base != 0) { /* estimate size */
873 size = base & -base;
874 } else { /* calculate size */
875 do_pcibr_config_set(wptr, (win * 4), 4, ~0); /* write 1's */
876 size = do_pcibr_config_get(wptr, (win * 4), 4); /* read back */
877 size &= mask; /* keep addr */
878 size &= -size; /* keep lsbit */
879 if (size == 0)
880 continue;
881 }
882
883 pcibr_info->f_window[win].w_space = space;
884 pcibr_info->f_window[win].w_base = base;
885 pcibr_info->f_window[win].w_size = size;
886
887 if (code == PCI_BA_MEM_64BIT) {
888 win++; /* skip upper half */
889 do_pcibr_config_set(wptr, (win * 4), 4, 0); /* must be zero */
890 }
891 } /* next win */
892 } /* next func */
893
894 return(0);
895 }
896
897 /*
898 * pcibr_find_capability
899 * Walk the list of capabilities (if it exists) looking for
900 * the requested capability. Return a cfg_p pointer to the
901 * capability if found, else return NULL
902 */
903 cfg_p
pcibr_find_capability(cfg_p cfgw,unsigned capability)904 pcibr_find_capability(cfg_p cfgw,
905 unsigned capability)
906 {
907 unsigned cap_nxt;
908 unsigned cap_id;
909 int defend_against_circular_linkedlist = 0;
910
911 /* Check to see if there is a capabilities pointer in the cfg header */
912 if (!(do_pcibr_config_get(cfgw, PCI_CFG_STATUS, 2) & PCI_STAT_CAP_LIST)) {
913 return (NULL);
914 }
915
916 /*
917 * Read up the capabilities head pointer from the configuration header.
918 * Capabilities are stored as a linked list in the lower 48 dwords of
919 * config space and are dword aligned. (Note: spec states the least two
920 * significant bits of the next pointer must be ignored, so we mask
921 * with 0xfc).
922 */
923 cap_nxt = (do_pcibr_config_get(cfgw, PCI_CAPABILITIES_PTR, 1) & 0xfc);
924
925 while (cap_nxt && (defend_against_circular_linkedlist <= 48)) {
926 cap_id = do_pcibr_config_get(cfgw, cap_nxt, 1);
927 if (cap_id == capability) {
928 return ((cfg_p)((char *)cfgw + cap_nxt));
929 }
930 cap_nxt = (do_pcibr_config_get(cfgw, cap_nxt+1, 1) & 0xfc);
931 defend_against_circular_linkedlist++;
932 }
933
934 return (NULL);
935 }
936
937 /*
938 * pcibr_slot_info_free
939 * Remove all the PCI infrastructural information associated
940 * with a particular PCI device.
941 */
942 int
pcibr_slot_info_free(vertex_hdl_t pcibr_vhdl,pciio_slot_t slot)943 pcibr_slot_info_free(vertex_hdl_t pcibr_vhdl,
944 pciio_slot_t slot)
945 {
946 pcibr_soft_t pcibr_soft;
947 pcibr_info_h pcibr_infoh;
948 int nfunc;
949
950 pcibr_soft = pcibr_soft_get(pcibr_vhdl);
951
952 if (!pcibr_soft)
953 return(EINVAL);
954
955 if (!PCIBR_VALID_SLOT(pcibr_soft, slot))
956 return(EINVAL);
957
958 nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
959
960 pcibr_device_info_free(pcibr_vhdl, slot);
961
962 pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
963 DELA(pcibr_infoh,nfunc);
964 pcibr_soft->bs_slot[slot].bss_ninfo = 0;
965
966 return(0);
967 }
968
969 /*
970 * pcibr_slot_pcix_rbar_init
971 * Allocate RBARs to the PCI-X functions on a given device
972 */
973 int
pcibr_slot_pcix_rbar_init(pcibr_soft_t pcibr_soft,pciio_slot_t slot)974 pcibr_slot_pcix_rbar_init(pcibr_soft_t pcibr_soft,
975 pciio_slot_t slot)
976 {
977 pcibr_info_h pcibr_infoh;
978 pcibr_info_t pcibr_info;
979 char tmp_str[256];
980 int nfunc;
981 int func;
982
983 if (!PCIBR_VALID_SLOT(pcibr_soft, slot))
984 return(EINVAL);
985
986 if ((nfunc = pcibr_soft->bs_slot[slot].bss_ninfo) < 1)
987 return(EINVAL);
988
989 if (!(pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos))
990 return(EINVAL);
991
992 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_RBAR, pcibr_soft->bs_vhdl,
993 "pcibr_slot_pcix_rbar_init for slot %d\n",
994 PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot)));
995 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_RBAR, pcibr_soft->bs_vhdl,
996 "\tslot/func\trequested\tgiven\tinuse\tavail\n"));
997
998 for (func = 0; func < nfunc; ++func) {
999 cap_pcix_type0_t *pcix_cap_p;
1000 cap_pcix_stat_reg_t *pcix_statreg_p;
1001 cap_pcix_cmd_reg_t *pcix_cmdreg_p;
1002 int num_rbar;
1003
1004 if (!(pcibr_info = pcibr_infoh[func]))
1005 continue;
1006
1007 if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
1008 continue;
1009
1010 if (!(pcix_cap_p = pcibr_info->f_pcix_cap))
1011 continue;
1012
1013 pcix_statreg_p = &pcix_cap_p->pcix_type0_status;
1014 pcix_cmdreg_p = &pcix_cap_p->pcix_type0_command;
1015
1016 /* If there are enough RBARs to satify the number of "max outstanding
1017 * transactions" each function requested (bs_pcix_rbar_percent_allowed
1018 * is 100%), then give each function what it requested, otherwise give
1019 * the functions a "percentage of what they requested".
1020 */
1021 if (pcibr_soft->bs_pcix_rbar_percent_allowed >= 100) {
1022 pcix_cmdreg_p->max_split = pcix_statreg_p->max_out_split;
1023 num_rbar = max_splittrans_to_numbuf[pcix_cmdreg_p->max_split];
1024 pcibr_soft->bs_pcix_rbar_inuse += num_rbar;
1025 pcibr_soft->bs_pcix_rbar_avail -= num_rbar;
1026 pcix_cmdreg_p->max_mem_read_cnt = pcix_statreg_p->max_mem_read_cnt;
1027 } else {
1028 int index; /* index into max_splittrans_to_numbuf table */
1029 int max_out; /* max outstanding transactions given to func */
1030
1031 /* Calculate the percentage of RBARs this function can have.
1032 * NOTE: Every function gets at least 1 RBAR (thus the "+1").
1033 * bs_pcix_rbar_percent_allowed is the percentage of what was
1034 * requested less this 1 RBAR that all functions automatically
1035 * gets
1036 */
1037 max_out = ((max_splittrans_to_numbuf[pcix_statreg_p->max_out_split]
1038 * pcibr_soft->bs_pcix_rbar_percent_allowed) / 100) + 1;
1039
1040 /* round down the newly caclulated max_out to a valid number in
1041 * max_splittrans_to_numbuf[]
1042 */
1043 for (index = 0; index < MAX_SPLIT_TABLE-1; index++)
1044 if (max_splittrans_to_numbuf[index + 1] > max_out)
1045 break;
1046
1047 pcix_cmdreg_p->max_split = index;
1048 num_rbar = max_splittrans_to_numbuf[pcix_cmdreg_p->max_split];
1049 pcibr_soft->bs_pcix_rbar_inuse += num_rbar;
1050 pcibr_soft->bs_pcix_rbar_avail -= num_rbar;
1051 pcix_cmdreg_p->max_mem_read_cnt = pcix_statreg_p->max_mem_read_cnt;
1052 }
1053 /*
1054 * The kernel only allows functions to have so many variable args,
1055 * attempting to call PCIBR_DEBUG_ALWAYS() with more than 5 printf
1056 * arguments fails so sprintf() it into a temporary string.
1057 */
1058 if (pcibr_debug_mask & PCIBR_DEBUG_RBAR) {
1059 sprintf(tmp_str,"\t %d/%d \t %d \t %d \t %d \t %d\n",
1060 PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), func,
1061 max_splittrans_to_numbuf[pcix_statreg_p->max_out_split],
1062 max_splittrans_to_numbuf[pcix_cmdreg_p->max_split],
1063 pcibr_soft->bs_pcix_rbar_inuse,
1064 pcibr_soft->bs_pcix_rbar_avail);
1065 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_RBAR, pcibr_soft->bs_vhdl,
1066 "%s", tmp_str));
1067 }
1068 }
1069 return(0);
1070 }
1071
1072 int as_debug = 0;
1073 /*
1074 * pcibr_slot_addr_space_init
1075 * Reserve chunks of PCI address space as required by
1076 * the base registers in the card.
1077 */
1078 int
pcibr_slot_addr_space_init(vertex_hdl_t pcibr_vhdl,pciio_slot_t slot)1079 pcibr_slot_addr_space_init(vertex_hdl_t pcibr_vhdl,
1080 pciio_slot_t slot)
1081 {
1082 pcibr_soft_t pcibr_soft;
1083 pcibr_info_h pcibr_infoh;
1084 pcibr_info_t pcibr_info;
1085 bridge_t *bridge;
1086 iopaddr_t mask;
1087 int nbars;
1088 int nfunc;
1089 int func;
1090 int win;
1091 int rc = 0;
1092 int align;
1093 int align_slot;
1094
1095 pcibr_soft = pcibr_soft_get(pcibr_vhdl);
1096
1097 if (!pcibr_soft)
1098 return(EINVAL);
1099
1100 if (!PCIBR_VALID_SLOT(pcibr_soft, slot))
1101 return(EINVAL);
1102
1103 bridge = pcibr_soft->bs_base;
1104
1105 /* allocate address space,
1106 * for windows that have not been
1107 * previously assigned.
1108 */
1109 if (pcibr_soft->bs_slot[slot].has_host) {
1110 return(0);
1111 }
1112
1113 nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
1114 if (nfunc < 1)
1115 return(EINVAL);
1116
1117 pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
1118 if (!pcibr_infoh)
1119 return(EINVAL);
1120
1121 /*
1122 * Try to make the DevIO windows not
1123 * overlap by pushing the "io" and "hi"
1124 * allocation areas up to the next one
1125 * or two megabyte bound. This also
1126 * keeps them from being zero.
1127 *
1128 * DO NOT do this with "pci_lo" since
1129 * the entire "lo" area is only a
1130 * megabyte, total ...
1131 */
1132 align_slot = 0x100000;
1133 align = align_slot;
1134
1135 for (func = 0; func < nfunc; ++func) {
1136 cfg_p cfgw;
1137 cfg_p wptr;
1138 pciio_space_t space;
1139 iopaddr_t base;
1140 size_t size;
1141 #ifdef PCI_LATER
1142 char tmp_str[256];
1143 #endif
1144 unsigned pci_cfg_cmd_reg;
1145 unsigned pci_cfg_cmd_reg_add = 0;
1146
1147 pcibr_info = pcibr_infoh[func];
1148
1149 if (!pcibr_info)
1150 continue;
1151
1152 if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
1153 continue;
1154
1155 cfgw = pcibr_func_config_addr(bridge, 0, slot, func, 0);
1156 wptr = cfgw + PCI_CFG_BASE_ADDR_0 / 4;
1157
1158 if ((do_pcibr_config_get(cfgw, PCI_CFG_HEADER_TYPE, 1) & 0x7f) != 0)
1159 nbars = 2;
1160 else
1161 nbars = PCI_CFG_BASE_ADDRS;
1162
1163 for (win = 0; win < nbars; ++win) {
1164 space = pcibr_info->f_window[win].w_space;
1165 base = pcibr_info->f_window[win].w_base;
1166 size = pcibr_info->f_window[win].w_size;
1167
1168 if (size < 1)
1169 continue;
1170
1171 if (base >= size) {
1172 /*
1173 * The kernel only allows functions to have so many variable
1174 * args attempting to call PCIBR_DEBUG_ALWAYS() with more than
1175 * 5 printf arguments fails so sprintf() it into a temporary
1176 * string (tmp_str).
1177 */
1178 #if defined(SUPPORT_PRINTING_R_FORMAT)
1179 if (pcibr_debug_mask & PCIBR_DEBUG_BAR) {
1180 sprintf(tmp_str, "pcibr_slot_addr_space_init: slot=%d, "
1181 "func=%d win %d is in %r [0x%x..0x%x], allocated by "
1182 "prom\n", PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot),
1183 func, win, space, space_desc, base, base + size - 1);
1184 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_BAR, pcibr_vhdl,
1185 "%s",tmp_str));
1186 }
1187 #endif /* SUPPORT_PRINTING_R_FORMAT */
1188 continue; /* already allocated */
1189 }
1190
1191 align = (win) ? size : align_slot;
1192
1193 if (align < PAGE_SIZE)
1194 align = PAGE_SIZE; /* ie. 0x00004000 */
1195
1196 switch (space) {
1197 case PCIIO_SPACE_IO:
1198 base = pcibr_bus_addr_alloc(pcibr_soft,
1199 &pcibr_info->f_window[win],
1200 PCIIO_SPACE_IO,
1201 0, size, align);
1202 if (!base)
1203 rc = ENOSPC;
1204 break;
1205
1206 case PCIIO_SPACE_MEM:
1207 if ((do_pcibr_config_get(wptr, (win * 4), 4) &
1208 PCI_BA_MEM_LOCATION) == PCI_BA_MEM_1MEG) {
1209
1210 /* allocate from 20-bit PCI space */
1211 base = pcibr_bus_addr_alloc(pcibr_soft,
1212 &pcibr_info->f_window[win],
1213 PCIIO_SPACE_MEM,
1214 0, size, align);
1215 if (!base)
1216 rc = ENOSPC;
1217 } else {
1218 /* allocate from 32-bit or 64-bit PCI space */
1219 base = pcibr_bus_addr_alloc(pcibr_soft,
1220 &pcibr_info->f_window[win],
1221 PCIIO_SPACE_MEM32,
1222 0, size, align);
1223 if (!base)
1224 rc = ENOSPC;
1225 }
1226 break;
1227
1228 default:
1229 base = 0;
1230 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_BAR, pcibr_vhdl,
1231 "pcibr_slot_addr_space_init: slot=%d, window %d "
1232 "had bad space code %d\n",
1233 PCIBR_DEVICE_TO_SLOT(pcibr_soft,slot), win, space));
1234 }
1235 pcibr_info->f_window[win].w_base = base;
1236 do_pcibr_config_set(wptr, (win * 4), 4, base);
1237
1238 #if defined(SUPPORT_PRINTING_R_FORMAT)
1239 if (pcibr_debug_mask & PCIBR_DEBUG_BAR) {
1240 if (base >= size) {
1241 sprintf(tmp_str,"pcibr_slot_addr_space_init: slot=%d, func="
1242 "%d, win %d is in %r[0x%x..0x%x], "
1243 "allocated by pcibr\n",
1244 PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot),
1245 func, win, space, space_desc, base,
1246 base + size - 1);
1247 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_BAR, pcibr_vhdl,
1248 "%s",tmp_str));
1249 }
1250 else {
1251 sprintf(tmp_str,"pcibr_slot_addr_space_init: slot=%d, func="
1252 "%d, win %d, unable to alloc 0x%x in %r\n",
1253 PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot),
1254 func, win, size, space, space_desc);
1255 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_BAR, pcibr_vhdl,
1256 "%s",tmp_str));
1257 }
1258 }
1259 #endif /* SUPPORT_PRINTING_R_FORMAT */
1260 } /* next base */
1261
1262 /*
1263 * Allocate space for the EXPANSION ROM
1264 */
1265 base = size = 0;
1266 {
1267 wptr = cfgw + PCI_EXPANSION_ROM / 4;
1268 do_pcibr_config_set(wptr, 0, 4, 0xFFFFF000);
1269 mask = do_pcibr_config_get(wptr, 0, 4);
1270 if (mask & 0xFFFFF000) {
1271 size = mask & -mask;
1272 base = pcibr_bus_addr_alloc(pcibr_soft,
1273 &pcibr_info->f_rwindow,
1274 PCIIO_SPACE_MEM32,
1275 0, size, align);
1276 if (!base)
1277 rc = ENOSPC;
1278 else {
1279 do_pcibr_config_set(wptr, 0, 4, base);
1280 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_BAR, pcibr_vhdl,
1281 "pcibr_slot_addr_space_init: slot=%d, func=%d, "
1282 "ROM in [0x%X..0x%X], allocated by pcibr\n",
1283 PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot),
1284 func, base, base + size - 1));
1285 }
1286 }
1287 }
1288 pcibr_info->f_rbase = base;
1289 pcibr_info->f_rsize = size;
1290
1291 /*
1292 * if necessary, update the board's
1293 * command register to enable decoding
1294 * in the windows we added.
1295 *
1296 * There are some bits we always want to
1297 * be sure are set.
1298 */
1299 pci_cfg_cmd_reg_add |= PCI_CMD_IO_SPACE;
1300
1301 /*
1302 * The Adaptec 1160 FC Controller WAR #767995:
1303 * The part incorrectly ignores the upper 32 bits of a 64 bit
1304 * address when decoding references to its registers so to
1305 * keep it from responding to a bus cycle that it shouldn't
1306 * we only use I/O space to get at it's registers. Don't
1307 * enable memory space accesses on that PCI device.
1308 */
1309 #define FCADP_VENDID 0x9004 /* Adaptec Vendor ID from fcadp.h */
1310 #define FCADP_DEVID 0x1160 /* Adaptec 1160 Device ID from fcadp.h */
1311
1312 if ((pcibr_info->f_vendor != FCADP_VENDID) ||
1313 (pcibr_info->f_device != FCADP_DEVID))
1314 pci_cfg_cmd_reg_add |= PCI_CMD_MEM_SPACE;
1315
1316 pci_cfg_cmd_reg_add |= PCI_CMD_BUS_MASTER;
1317
1318 pci_cfg_cmd_reg = do_pcibr_config_get(cfgw, PCI_CFG_COMMAND, 4);
1319
1320 #if PCI_FBBE /* XXX- check here to see if dev can do fast-back-to-back */
1321 if (!((pci_cfg_cmd_reg >> 16) & PCI_STAT_F_BK_BK_CAP))
1322 fast_back_to_back_enable = 0;
1323 #endif
1324 pci_cfg_cmd_reg &= 0xFFFF;
1325 if (pci_cfg_cmd_reg_add & ~pci_cfg_cmd_reg)
1326 do_pcibr_config_set(cfgw, PCI_CFG_COMMAND, 4,
1327 pci_cfg_cmd_reg | pci_cfg_cmd_reg_add);
1328 } /* next func */
1329 return(rc);
1330 }
1331
1332 /*
1333 * pcibr_slot_device_init
1334 * Setup the device register in the bridge for this PCI slot.
1335 */
1336
1337 int
pcibr_slot_device_init(vertex_hdl_t pcibr_vhdl,pciio_slot_t slot)1338 pcibr_slot_device_init(vertex_hdl_t pcibr_vhdl,
1339 pciio_slot_t slot)
1340 {
1341 pcibr_soft_t pcibr_soft;
1342 bridge_t *bridge;
1343 bridgereg_t devreg;
1344
1345 pcibr_soft = pcibr_soft_get(pcibr_vhdl);
1346
1347 if (!pcibr_soft)
1348 return(EINVAL);
1349
1350 if (!PCIBR_VALID_SLOT(pcibr_soft, slot))
1351 return(EINVAL);
1352
1353 bridge = pcibr_soft->bs_base;
1354
1355 /*
1356 * Adjustments to Device(x)
1357 * and init of bss_device shadow
1358 */
1359 devreg = bridge->b_device[slot].reg;
1360 devreg &= ~BRIDGE_DEV_PAGE_CHK_DIS;
1361
1362 /*
1363 * PIC WAR. PV# 855271
1364 * Don't enable virtual channels in the PIC by default.
1365 * Can cause problems with 32-bit devices. (The bit is only intended
1366 * for 64-bit devices). We set the bit in pcibr_try_set_device()
1367 * if we're 64-bit and requesting virtual channels.
1368 */
1369 if (IS_PIC_SOFT(pcibr_soft) && PCIBR_WAR_ENABLED(PV855271, pcibr_soft))
1370 devreg |= BRIDGE_DEV_COH;
1371 else
1372 devreg |= BRIDGE_DEV_COH | BRIDGE_DEV_VIRTUAL_EN;
1373 pcibr_soft->bs_slot[slot].bss_device = devreg;
1374 bridge->b_device[slot].reg = devreg;
1375
1376 #ifdef PIC_LATER
1377 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_DEVREG, pcibr_vhdl,
1378 "pcibr_slot_device_init: Device(%d): %R\n",
1379 slot, devreg, device_bits));
1380 #endif
1381 return(0);
1382 }
1383
1384 /*
1385 * pcibr_slot_guest_info_init
1386 * Setup the host/guest relations for a PCI slot.
1387 */
1388 int
pcibr_slot_guest_info_init(vertex_hdl_t pcibr_vhdl,pciio_slot_t slot)1389 pcibr_slot_guest_info_init(vertex_hdl_t pcibr_vhdl,
1390 pciio_slot_t slot)
1391 {
1392 pcibr_soft_t pcibr_soft;
1393 pcibr_info_h pcibr_infoh;
1394 pcibr_info_t pcibr_info;
1395 pcibr_soft_slot_t slotp;
1396
1397 pcibr_soft = pcibr_soft_get(pcibr_vhdl);
1398
1399 if (!pcibr_soft)
1400 return(EINVAL);
1401
1402 if (!PCIBR_VALID_SLOT(pcibr_soft, slot))
1403 return(EINVAL);
1404
1405 slotp = &pcibr_soft->bs_slot[slot];
1406
1407 /* create info and verticies for guest slots;
1408 * for compatibilitiy macros, create info
1409 * for even unpopulated slots (but do not
1410 * build verticies for them).
1411 */
1412 if (pcibr_soft->bs_slot[slot].bss_ninfo < 1) {
1413 NEWA(pcibr_infoh, 1);
1414 pcibr_soft->bs_slot[slot].bss_ninfo = 1;
1415 pcibr_soft->bs_slot[slot].bss_infos = pcibr_infoh;
1416
1417 pcibr_info = pcibr_device_info_new
1418 (pcibr_soft, slot, PCIIO_FUNC_NONE,
1419 PCIIO_VENDOR_ID_NONE, PCIIO_DEVICE_ID_NONE);
1420
1421 if (pcibr_soft->bs_slot[slot].has_host) {
1422 slotp->slot_conn = pciio_device_info_register
1423 (pcibr_vhdl, &pcibr_info->f_c);
1424 }
1425 }
1426
1427 /* generate host/guest relations
1428 */
1429 if (pcibr_soft->bs_slot[slot].has_host) {
1430 int host = pcibr_soft->bs_slot[slot].host_slot;
1431 pcibr_soft_slot_t host_slotp = &pcibr_soft->bs_slot[host];
1432
1433 hwgraph_edge_add(slotp->slot_conn,
1434 host_slotp->slot_conn,
1435 EDGE_LBL_HOST);
1436
1437 /* XXX- only gives us one guest edge per
1438 * host. If/when we have a host with more than
1439 * one guest, we will need to figure out how
1440 * the host finds all its guests, and sorts
1441 * out which one is which.
1442 */
1443 hwgraph_edge_add(host_slotp->slot_conn,
1444 slotp->slot_conn,
1445 EDGE_LBL_GUEST);
1446 }
1447
1448 return(0);
1449 }
1450
1451
1452 /*
1453 * pcibr_slot_call_device_attach
1454 * This calls the associated driver attach routine for the PCI
1455 * card in this slot.
1456 */
1457 int
pcibr_slot_call_device_attach(vertex_hdl_t pcibr_vhdl,pciio_slot_t slot,int drv_flags)1458 pcibr_slot_call_device_attach(vertex_hdl_t pcibr_vhdl,
1459 pciio_slot_t slot,
1460 int drv_flags)
1461 {
1462 pcibr_soft_t pcibr_soft;
1463 pcibr_info_h pcibr_infoh;
1464 pcibr_info_t pcibr_info;
1465 int func;
1466 vertex_hdl_t xconn_vhdl, conn_vhdl;
1467 #ifdef PIC_LATER
1468 vertex_hdl_t scsi_vhdl;
1469 #endif
1470 int nfunc;
1471 int error_func;
1472 int error_slot = 0;
1473 int error = ENODEV;
1474 #ifdef PIC_LATER
1475 int hwg_err;
1476 #endif
1477
1478 pcibr_soft = pcibr_soft_get(pcibr_vhdl);
1479
1480 if (!pcibr_soft)
1481 return(EINVAL);
1482
1483 if (!PCIBR_VALID_SLOT(pcibr_soft, slot))
1484 return(EINVAL);
1485
1486 if (pcibr_soft->bs_slot[slot].has_host) {
1487 return(EPERM);
1488 }
1489
1490 xconn_vhdl = pcibr_soft->bs_conn;
1491
1492 nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
1493 pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
1494
1495 for (func = 0; func < nfunc; ++func) {
1496
1497 pcibr_info = pcibr_infoh[func];
1498
1499 if (!pcibr_info)
1500 continue;
1501
1502 if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
1503 continue;
1504
1505 conn_vhdl = pcibr_info->f_vertex;
1506
1507
1508 error_func = pciio_device_attach(conn_vhdl, drv_flags);
1509
1510 #ifdef PIC_LATER
1511 /*
1512 * Try to assign well-known SCSI controller numbers for hot-plug
1513 * insert
1514 */
1515 if (drv_flags) {
1516
1517 hwg_err = hwgraph_path_lookup(conn_vhdl, EDGE_LBL_SCSI_CTLR "/0",
1518 &scsi_vhdl, NULL);
1519
1520 if (hwg_err == GRAPH_SUCCESS)
1521 scsi_ctlr_nums_add(baseio_pci_vhdl, scsi_vhdl);
1522
1523 /* scsi_vhdl will be the final vertex in either the complete path
1524 * on success or a partial path on failure; in either case,
1525 * unreference that vertex.
1526 */
1527 hwgraph_vertex_unref(scsi_vhdl);
1528
1529 hwg_err = hwgraph_path_lookup(conn_vhdl, EDGE_LBL_SCSI_CTLR "/1",
1530 &scsi_vhdl, NULL);
1531
1532 if (hwg_err == GRAPH_SUCCESS)
1533 scsi_ctlr_nums_add(baseio_pci_vhdl, scsi_vhdl);
1534
1535 /* scsi_vhdl will be the final vertex in either the complete path
1536 * on success or a partial path on failure; in either case,
1537 * unreference that vertex.
1538 */
1539 hwgraph_vertex_unref(scsi_vhdl);
1540
1541 }
1542 #endif /* PIC_LATER */
1543
1544 pcibr_info->f_att_det_error = error_func;
1545
1546 if (error_func)
1547 error_slot = error_func;
1548
1549 error = error_slot;
1550
1551 } /* next func */
1552
1553 if (error) {
1554 if ((error != ENODEV) && (error != EUNATCH) && (error != EPERM)) {
1555 pcibr_soft->bs_slot[slot].slot_status &= ~SLOT_STATUS_MASK;
1556 pcibr_soft->bs_slot[slot].slot_status |= SLOT_STARTUP_INCMPLT;
1557 }
1558 } else {
1559 pcibr_soft->bs_slot[slot].slot_status &= ~SLOT_STATUS_MASK;
1560 pcibr_soft->bs_slot[slot].slot_status |= SLOT_STARTUP_CMPLT;
1561 }
1562
1563 return(error);
1564 }
1565
1566 /*
1567 * pcibr_slot_call_device_detach
1568 * This calls the associated driver detach routine for the PCI
1569 * card in this slot.
1570 */
1571 int
pcibr_slot_call_device_detach(vertex_hdl_t pcibr_vhdl,pciio_slot_t slot,int drv_flags)1572 pcibr_slot_call_device_detach(vertex_hdl_t pcibr_vhdl,
1573 pciio_slot_t slot,
1574 int drv_flags)
1575 {
1576 pcibr_soft_t pcibr_soft;
1577 pcibr_info_h pcibr_infoh;
1578 pcibr_info_t pcibr_info;
1579 int func;
1580 vertex_hdl_t conn_vhdl = GRAPH_VERTEX_NONE;
1581 int nfunc;
1582 int error_func;
1583 int error_slot = 0;
1584 int error = ENODEV;
1585
1586 pcibr_soft = pcibr_soft_get(pcibr_vhdl);
1587
1588 if (!pcibr_soft)
1589 return(EINVAL);
1590
1591 if (!PCIBR_VALID_SLOT(pcibr_soft, slot))
1592 return(EINVAL);
1593
1594 if (pcibr_soft->bs_slot[slot].has_host)
1595 return(EPERM);
1596
1597 nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
1598 pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
1599
1600 for (func = 0; func < nfunc; ++func) {
1601
1602 pcibr_info = pcibr_infoh[func];
1603
1604 if (!pcibr_info)
1605 continue;
1606
1607 if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
1608 continue;
1609
1610 if (IS_PCIX(pcibr_soft) && pcibr_info->f_pcix_cap) {
1611 int max_out;
1612
1613 pcibr_soft->bs_pcix_num_funcs--;
1614 max_out = pcibr_info->f_pcix_cap->pcix_type0_status.max_out_split;
1615 pcibr_soft->bs_pcix_split_tot -= max_splittrans_to_numbuf[max_out];
1616 }
1617
1618 conn_vhdl = pcibr_info->f_vertex;
1619
1620 error_func = pciio_device_detach(conn_vhdl, drv_flags);
1621
1622 pcibr_info->f_att_det_error = error_func;
1623
1624 if (error_func)
1625 error_slot = error_func;
1626
1627 error = error_slot;
1628
1629 } /* next func */
1630
1631
1632 if (error) {
1633 if ((error != ENODEV) && (error != EUNATCH) && (error != EPERM)) {
1634 pcibr_soft->bs_slot[slot].slot_status &= ~SLOT_STATUS_MASK;
1635 pcibr_soft->bs_slot[slot].slot_status |= SLOT_SHUTDOWN_INCMPLT;
1636 }
1637 } else {
1638 if (conn_vhdl != GRAPH_VERTEX_NONE)
1639 pcibr_device_unregister(conn_vhdl);
1640 pcibr_soft->bs_slot[slot].slot_status &= ~SLOT_STATUS_MASK;
1641 pcibr_soft->bs_slot[slot].slot_status |= SLOT_SHUTDOWN_CMPLT;
1642 }
1643
1644 return(error);
1645 }
1646
1647 /*
1648 * pcibr_slot_attach
1649 * This is a place holder routine to keep track of all the
1650 * slot-specific initialization that needs to be done.
1651 * This is usually called when we want to initialize a new
1652 * PCI card on the bus.
1653 */
1654 int
pcibr_slot_attach(vertex_hdl_t pcibr_vhdl,pciio_slot_t slot,int drv_flags,char * l1_msg,int * sub_errorp)1655 pcibr_slot_attach(vertex_hdl_t pcibr_vhdl,
1656 pciio_slot_t slot,
1657 int drv_flags,
1658 char *l1_msg,
1659 int *sub_errorp)
1660 {
1661 pcibr_soft_t pcibr_soft = pcibr_soft_get(pcibr_vhdl);
1662 #ifdef PIC_LATER
1663 timespec_t ts;
1664 #endif
1665 int error;
1666
1667 /* Do not allow a multi-function card to be hot-plug inserted */
1668 if (pcibr_soft->bs_slot[slot].bss_ninfo > 1) {
1669 if (sub_errorp)
1670 *sub_errorp = EPERM;
1671 return(PCI_MULTI_FUNC_ERR);
1672 }
1673
1674 /* Call the device attach */
1675 error = pcibr_slot_call_device_attach(pcibr_vhdl, slot, drv_flags);
1676 if (error) {
1677 if (sub_errorp)
1678 *sub_errorp = error;
1679 if (error == EUNATCH)
1680 return(PCI_NO_DRIVER);
1681 else
1682 return(PCI_SLOT_DRV_ATTACH_ERR);
1683 }
1684
1685 return(0);
1686 }
1687
1688 /*
1689 * pcibr_slot_detach
1690 * This is a place holder routine to keep track of all the
1691 * slot-specific freeing that needs to be done.
1692 */
1693 int
pcibr_slot_detach(vertex_hdl_t pcibr_vhdl,pciio_slot_t slot,int drv_flags,char * l1_msg,int * sub_errorp)1694 pcibr_slot_detach(vertex_hdl_t pcibr_vhdl,
1695 pciio_slot_t slot,
1696 int drv_flags,
1697 char *l1_msg,
1698 int *sub_errorp)
1699 {
1700 pcibr_soft_t pcibr_soft = pcibr_soft_get(pcibr_vhdl);
1701 int error;
1702
1703 /* Call the device detach function */
1704 error = (pcibr_slot_call_device_detach(pcibr_vhdl, slot, drv_flags));
1705 if (error) {
1706 if (sub_errorp)
1707 *sub_errorp = error;
1708 return(PCI_SLOT_DRV_DETACH_ERR);
1709 }
1710
1711 /* Recalculate the RBARs for all the devices on the bus since we've
1712 * just freed some up and some of the devices could use them.
1713 */
1714 if (IS_PCIX(pcibr_soft)) {
1715 int tmp_slot;
1716
1717 pcibr_soft->bs_pcix_rbar_inuse = 0;
1718 pcibr_soft->bs_pcix_rbar_avail = NUM_RBAR;
1719 pcibr_soft->bs_pcix_rbar_percent_allowed =
1720 pcibr_pcix_rbars_calc(pcibr_soft);
1721
1722 for (tmp_slot = pcibr_soft->bs_min_slot;
1723 tmp_slot < PCIBR_NUM_SLOTS(pcibr_soft); ++tmp_slot)
1724 (void)pcibr_slot_pcix_rbar_init(pcibr_soft, tmp_slot);
1725 }
1726
1727 return (0);
1728
1729 }
1730
1731 /*
1732 * pcibr_probe_slot_pic: read a config space word
1733 * while trapping any errors; return zero if
1734 * all went OK, or nonzero if there was an error.
1735 * The value read, if any, is passed back
1736 * through the valp parameter.
1737 */
1738 static int
pcibr_probe_slot_pic(bridge_t * bridge,cfg_p cfg,unsigned * valp)1739 pcibr_probe_slot_pic(bridge_t *bridge,
1740 cfg_p cfg,
1741 unsigned *valp)
1742 {
1743 int rv;
1744 picreg_t p_old_enable = (picreg_t)0, p_new_enable;
1745
1746 p_old_enable = bridge->p_int_enable_64;
1747 p_new_enable = p_old_enable & ~(BRIDGE_IMR_PCI_MST_TIMEOUT | PIC_ISR_PCIX_MTOUT);
1748 bridge->p_int_enable_64 = p_new_enable;
1749
1750 if (bridge->p_err_int_view_64 & (BRIDGE_ISR_PCI_MST_TIMEOUT | PIC_ISR_PCIX_MTOUT))
1751 bridge->p_int_rst_stat_64 = BRIDGE_IRR_MULTI_CLR;
1752
1753 if (bridge->p_int_status_64 & (BRIDGE_IRR_PCI_GRP | PIC_PCIX_GRP_CLR)) {
1754 bridge->p_int_rst_stat_64 = (BRIDGE_IRR_PCI_GRP_CLR | PIC_PCIX_GRP_CLR);
1755 (void) bridge->b_wid_tflush; /* flushbus */
1756 }
1757 rv = snia_badaddr_val((void *) cfg, 4, valp);
1758 if (bridge->p_err_int_view_64 & (BRIDGE_ISR_PCI_MST_TIMEOUT | PIC_ISR_PCIX_MTOUT)) {
1759 bridge->p_int_rst_stat_64 = BRIDGE_IRR_MULTI_CLR;
1760 rv = 1; /* unoccupied slot */
1761 }
1762 bridge->p_int_enable_64 = p_old_enable;
1763 bridge->b_wid_tflush; /* wait until Bridge PIO complete */
1764 return(rv);
1765 }
1766
1767 /*
1768 * pcibr_probe_slot: read a config space word
1769 * while trapping any errors; return zero if
1770 * all went OK, or nonzero if there was an error.
1771 * The value read, if any, is passed back
1772 * through the valp parameter.
1773 */
1774 static int
pcibr_probe_slot(bridge_t * bridge,cfg_p cfg,unsigned * valp)1775 pcibr_probe_slot(bridge_t *bridge,
1776 cfg_p cfg,
1777 unsigned *valp)
1778 {
1779 return(pcibr_probe_slot_pic(bridge, cfg, valp));
1780 }
1781
1782
1783 void
pcibr_device_info_free(vertex_hdl_t pcibr_vhdl,pciio_slot_t slot)1784 pcibr_device_info_free(vertex_hdl_t pcibr_vhdl, pciio_slot_t slot)
1785 {
1786 pcibr_soft_t pcibr_soft = pcibr_soft_get(pcibr_vhdl);
1787 pcibr_info_t pcibr_info;
1788 pciio_function_t func;
1789 pcibr_soft_slot_t slotp = &pcibr_soft->bs_slot[slot];
1790 bridge_t *bridge = pcibr_soft->bs_base;
1791 cfg_p cfgw;
1792 int nfunc = slotp->bss_ninfo;
1793 int bar;
1794 int devio_index;
1795 int s;
1796 unsigned cmd_reg;
1797
1798
1799 for (func = 0; func < nfunc; func++) {
1800 pcibr_info = slotp->bss_infos[func];
1801
1802 if (!pcibr_info)
1803 continue;
1804
1805 s = pcibr_lock(pcibr_soft);
1806
1807 /* Disable memory and I/O BARs */
1808 cfgw = pcibr_func_config_addr(bridge, 0, slot, func, 0);
1809 cmd_reg = do_pcibr_config_get(cfgw, PCI_CFG_COMMAND, 4);
1810 cmd_reg &= (PCI_CMD_MEM_SPACE | PCI_CMD_IO_SPACE);
1811 do_pcibr_config_set(cfgw, PCI_CFG_COMMAND, 4, cmd_reg);
1812
1813 for (bar = 0; bar < PCI_CFG_BASE_ADDRS; bar++) {
1814 if (pcibr_info->f_window[bar].w_space == PCIIO_SPACE_NONE)
1815 continue;
1816
1817 /* Free the PCI bus space */
1818 pciibr_bus_addr_free(pcibr_soft, &pcibr_info->f_window[bar]);
1819
1820 /* Get index of the DevIO(x) register used to access this BAR */
1821 devio_index = pcibr_info->f_window[bar].w_devio_index;
1822
1823
1824 /* On last use, clear the DevIO(x) used to access this BAR */
1825 if (! --pcibr_soft->bs_slot[devio_index].bss_devio.bssd_ref_cnt) {
1826 pcibr_soft->bs_slot[devio_index].bss_devio.bssd_space =
1827 PCIIO_SPACE_NONE;
1828 pcibr_soft->bs_slot[devio_index].bss_devio.bssd_base =
1829 PCIBR_D32_BASE_UNSET;
1830 pcibr_soft->bs_slot[devio_index].bss_device = 0;
1831 }
1832 }
1833
1834 /* Free the Expansion ROM PCI bus space */
1835 if(pcibr_info->f_rbase && pcibr_info->f_rsize) {
1836 pciibr_bus_addr_free(pcibr_soft, &pcibr_info->f_rwindow);
1837 }
1838
1839 pcibr_unlock(pcibr_soft, s);
1840
1841 slotp->bss_infos[func] = 0;
1842 pciio_device_info_unregister(pcibr_vhdl, &pcibr_info->f_c);
1843 pciio_device_info_free(&pcibr_info->f_c);
1844
1845 DEL(pcibr_info);
1846 }
1847
1848 /* Reset the mapping usage counters */
1849 slotp->bss_pmu_uctr = 0;
1850 slotp->bss_d32_uctr = 0;
1851 slotp->bss_d64_uctr = 0;
1852
1853 /* Clear the Direct translation info */
1854 slotp->bss_d64_base = PCIBR_D64_BASE_UNSET;
1855 slotp->bss_d64_flags = 0;
1856 slotp->bss_d32_base = PCIBR_D32_BASE_UNSET;
1857 slotp->bss_d32_flags = 0;
1858
1859 /* Clear out shadow info necessary for the external SSRAM workaround */
1860 slotp->bss_ext_ates_active = ATOMIC_INIT(0);
1861 slotp->bss_cmd_pointer = 0;
1862 slotp->bss_cmd_shadow = 0;
1863
1864 }
1865
1866
1867 iopaddr_t
pcibr_bus_addr_alloc(pcibr_soft_t pcibr_soft,pciio_win_info_t win_info_p,pciio_space_t space,int start,int size,int align)1868 pcibr_bus_addr_alloc(pcibr_soft_t pcibr_soft, pciio_win_info_t win_info_p,
1869 pciio_space_t space, int start, int size, int align)
1870 {
1871 pciio_win_map_t win_map_p;
1872 struct resource *root_resource = NULL;
1873 iopaddr_t iopaddr = 0;
1874
1875 switch (space) {
1876
1877 case PCIIO_SPACE_IO:
1878 win_map_p = &pcibr_soft->bs_io_win_map;
1879 root_resource = &pcibr_soft->bs_io_win_root_resource;
1880 break;
1881
1882 case PCIIO_SPACE_MEM:
1883 win_map_p = &pcibr_soft->bs_swin_map;
1884 root_resource = &pcibr_soft->bs_swin_root_resource;
1885 break;
1886
1887 case PCIIO_SPACE_MEM32:
1888 win_map_p = &pcibr_soft->bs_mem_win_map;
1889 root_resource = &pcibr_soft->bs_mem_win_root_resource;
1890 break;
1891
1892 default:
1893 return 0;
1894
1895 }
1896 iopaddr = pciio_device_win_alloc(root_resource,
1897 win_info_p
1898 ? &win_info_p->w_win_alloc
1899 : NULL,
1900 start, size, align);
1901 return(iopaddr);
1902 }
1903
1904
1905 void
pciibr_bus_addr_free(pcibr_soft_t pcibr_soft,pciio_win_info_t win_info_p)1906 pciibr_bus_addr_free(pcibr_soft_t pcibr_soft, pciio_win_info_t win_info_p)
1907 {
1908 pciio_device_win_free(&win_info_p->w_win_alloc);
1909 }
1910
1911 /*
1912 * given a vertex_hdl to the pcibr_vhdl, return the brick's bus number
1913 * associated with that vertex_hdl. The true mapping happens from the
1914 * io_brick_tab[] array defined in ml/SN/iograph.c
1915 */
1916 int
pcibr_widget_to_bus(vertex_hdl_t pcibr_vhdl)1917 pcibr_widget_to_bus(vertex_hdl_t pcibr_vhdl)
1918 {
1919 pcibr_soft_t pcibr_soft = pcibr_soft_get(pcibr_vhdl);
1920 xwidgetnum_t widget = pcibr_soft->bs_xid;
1921 int bricktype = pcibr_soft->bs_bricktype;
1922 int bus = pcibr_soft->bs_busnum;
1923
1924 /*
1925 * For PIC there are 2 busses per widget and pcibr_soft->bs_busnum
1926 * will be 0 or 1. For [X]BRIDGE there is 1 bus per widget and
1927 * pcibr_soft->bs_busnum will always be zero. So we add bs_busnum
1928 * to what io_brick_map_widget returns to get the bus number.
1929 */
1930 if ((bus += io_brick_map_widget(bricktype, widget)) > 0) {
1931 return bus;
1932 } else {
1933 return 0;
1934 }
1935 }
1936