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Searched refs:out_8 (Results 1 – 25 of 44) sorted by relevance

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/linux-2.4.37.9/drivers/macintosh/
Dmacio-adb.c110 out_8(&adb->ctrl.r, 0); in macio_init()
111 out_8(&adb->intr.r, 0); in macio_init()
112 out_8(&adb->error.r, 0); in macio_init()
113 out_8(&adb->active_hi.r, 0xff); /* for now, set all devices active */ in macio_init()
114 out_8(&adb->active_lo.r, 0xff); in macio_init()
115 out_8(&adb->autopoll.r, APE); in macio_init()
123 out_8(&adb->intr_enb.r, DFB | TAG); in macio_init()
135 out_8(&adb->active_hi.r, devs >> 8); in macio_adb_autopoll()
136 out_8(&adb->active_lo.r, devs); in macio_adb_autopoll()
137 out_8(&adb->autopoll.r, devs? APE: 0); in macio_adb_autopoll()
[all …]
Dvia-cuda.c177 out_8(&via[IFR], 0x7f); /* clear interrupts by writing 1s */ in find_via_cuda()
178 out_8(&via[IER], IER_SET|SR_INT); /* enable interrupt from SR */ in find_via_cuda()
260 out_8(&via[DIRB], (in_8(&via[DIRB]) | TACK | TIP) & ~TREQ); /* TACK & TIP out */ in cuda_init_via()
261 out_8(&via[B], in_8(&via[B]) | TACK | TIP); /* negate them */ in cuda_init_via()
262 out_8(&via[ACR] ,(in_8(&via[ACR]) & ~SR_CTRL) | SR_EXT); /* SR data in */ in cuda_init_via()
265 out_8(&via[IER], 0x7f); /* disable interrupts from VIA */ in cuda_init_via()
272 out_8(&via[IFR], in_8(&via[IFR]) & 0x7f); in cuda_init_via()
275 out_8(&via[B], in_8(&via[B]) & ~TACK); in cuda_init_via()
283 out_8(&via[IFR], in_8(&via[IFR]) & 0x7f); in cuda_init_via()
286 out_8(&via[B], in_8(&via[B]) | TACK); in cuda_init_via()
[all …]
Dvia-pmu.c350 out_8(&via[IER], IER_CLR | 0x7f); /* disable all intrs */ in find_via_pmu()
351 out_8(&via[IFR], 0x7f); /* clear IFR */ in find_via_pmu()
425 out_8(&via[IER], IER_SET | SR_INT | CB1_INT); in via_pmu_start()
506 out_8(&via[B], via[B] | TREQ); /* negate TREQ */ in init_pmu()
507 out_8(&via[DIRB], (via[DIRB] | TREQ) & ~TACK); /* TACK in, TREQ out */ in init_pmu()
1073 out_8(&v[ACR], in_8(&v[ACR]) | SR_OUT | SR_EXT); in send_byte()
1074 out_8(&v[SR], x); in send_byte()
1075 out_8(&v[B], in_8(&v[B]) & ~TREQ); /* assert TREQ */ in send_byte()
1084 out_8(&v[ACR], (in_8(&v[ACR]) & ~SR_OUT) | SR_EXT); in recv_byte()
1086 out_8(&v[B], in_8(&v[B]) & ~TREQ); in recv_byte()
[all …]
Dans-lcd.c34 out_8(anslcd_ptr + ANSLCD_CTRL_IX, c); in anslcd_write_byte_ctrl()
47 out_8(anslcd_ptr + ANSLCD_DATA_IX, c); in anslcd_write_byte_data()
/linux-2.4.37.9/drivers/scsi/
Dmesh.c559 out_8(&mr->exception, 0xff); /* clear all exception bits */ in mesh_host_reset()
560 out_8(&mr->error, 0xff); /* clear all error bits */ in mesh_host_reset()
561 out_8(&mr->sequence, SEQ_RESETMESH); in mesh_host_reset()
563 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in mesh_host_reset()
564 out_8(&mr->source_id, ms->host->this_id); in mesh_host_reset()
565 out_8(&mr->sel_timeout, 25); /* 250ms */ in mesh_host_reset()
566 out_8(&mr->sync_params, ASYNC_PARAMS); in mesh_host_reset()
569 out_8(&mr->bus_status1, BS1_RST); /* assert RST */ in mesh_host_reset()
571 out_8(&mr->bus_status1, 0); /* negate RST */ in mesh_host_reset()
594 out_8(&mr->intr_mask, 0); in mesh_notify_reboot()
[all …]
/linux-2.4.37.9/drivers/block/
Dswim3.c262 out_8(&sw->select, RELAX); in swim3_select()
264 out_8(&sw->control_bis, SELECT); in swim3_select()
266 out_8(&sw->control_bic, SELECT); in swim3_select()
267 out_8(&sw->select, sel & CA_MASK); in swim3_select()
276 out_8(&sw->select, sw->select | LSTRB); in swim3_action()
278 out_8(&sw->select, sw->select & ~LSTRB); in swim3_action()
384 out_8(&sw->intr_enable, SEEN_SECTOR); in scan_track()
385 out_8(&sw->control_bis, DO_ACTION); in scan_track()
405 out_8(&sw->intr_enable, SEEK_DONE); in seek_track()
406 out_8(&sw->control_bis, DO_SEEK); in seek_track()
[all …]
/linux-2.4.37.9/drivers/video/
Dhpfb.c216 out_8(fb_regs + WMRR, 0x3); in topcat_blit()
223 out_8(fb_regs + WMOVE, fb_bitmask); in topcat_blit()
293 out_8(base+0x4800, 0); in hpfb_init_one()
294 out_8(base+0x4510, 0); in hpfb_init_one()
295 out_8(base+0x4512, 0); in hpfb_init_one()
296 out_8(base+0x4514, 0); in hpfb_init_one()
297 out_8(base+0x4516, 0); in hpfb_init_one()
298 out_8(base+0x4206, 0x90); in hpfb_init_one()
316 out_8(base + TC_WEN, 0xff); in hpfb_init_one()
317 out_8(base + TC_FBEN, 0xff); in hpfb_init_one()
[all …]
Ddnfb.c319 out_8(AP_CONTROL_3A, RESET_CREG); in dnfb_init()
321 out_8(AP_CONTROL_0, NORMAL_MODE); in dnfb_init()
322 out_8(AP_CONTROL_1, (AD_BLT | DST_EQ_SRC | NORM_CREG1)); in dnfb_init()
323 out_8(AP_CONTROL_2, S_DATA_PLN); in dnfb_init()
351 out_8(AP_CONTROL_3A, 0x0); in dnfbcon_blank()
354 out_8(AP_CONTROL_3A, 0x1); in dnfbcon_blank()
380 out_8(AP_CONTROL_0, in dn_bitblt()
391 out_8(AP_CONTROL_0, in dn_bitblt()
399 out_8(AP_CONTROL_3A, 0xc | (dest >> 16)); in dn_bitblt()
407 out_8(AP_WRITE_ENABLE, start_mask); in dn_bitblt()
[all …]
Dvalkyriefb.c342 out_8(&p->valkyrie_regs->mode.r, init->mode); in valkyriefb_blank()
351 out_8(&p->valkyrie_regs->mode.r, init->mode | 0x40); in valkyriefb_blank()
354 out_8(&p->valkyrie_regs->mode.r, 0x66); in valkyriefb_blank()
391 out_8(&p->cmap_regs->addr, regno); in valkyriefb_setcolreg()
394 out_8(&cmap_regs->lut, red); in valkyriefb_setcolreg()
395 out_8(&cmap_regs->lut, green); in valkyriefb_setcolreg()
396 out_8(&cmap_regs->lut, blue); in valkyriefb_setcolreg()
535 out_8(&valkyrie_regs->status.r, 0); in valkyrie_set_par()
539 out_8(&valkyrie_regs->mode.r, init->mode | 0x80); in valkyrie_set_par()
540 out_8(&valkyrie_regs->depth.r, cmode + 3); in valkyrie_set_par()
[all …]
Dplatinumfb.c418 out_8(&cmap_regs->addr, regno); /* tell clut what addr to fill */ in platinum_setcolreg()
419 out_8(&cmap_regs->lut, red); /* send one color channel at */ in platinum_setcolreg()
420 out_8(&cmap_regs->lut, green); /* a time... */ in platinum_setcolreg()
421 out_8(&cmap_regs->lut, blue); in platinum_setcolreg()
457 out_8(&cmap_regs->addr, (a+32)); \
458 out_8(&cmap_regs->d2, (d)); \
469 out_8(&cmap_regs->addr,3+32); in set_platinum_clock()
715 out_8(&info->cmap_regs->addr, 0x40); in platinum_of_init()
Dcontrolfb.c561 out_8(&p->cmap_regs->addr, regno); /* tell clut what addr to fill */ in controlfb_setcolreg()
562 out_8(&p->cmap_regs->lut, r); /* send one color channel at */ in controlfb_setcolreg()
563 out_8(&p->cmap_regs->lut, g); /* a time... */ in controlfb_setcolreg()
564 out_8(&p->cmap_regs->lut, b); in controlfb_setcolreg()
688 out_8(&p->cmap_regs->addr, (a)); \
689 out_8(&p->cmap_regs->dat, (d))
796 out_8(&p->frame_buffer[0x600000], 0xb3); in find_vram_size()
797 out_8(&p->frame_buffer[0x600001], 0x71); in find_vram_size()
815 out_8(&p->frame_buffer[0], 0x5a); in find_vram_size()
816 out_8(&p->frame_buffer[1], 0xc7); in find_vram_size()
Doffb.c696 out_8(info2->cmap_adr + 0xb0, i); in offbcon_blank()
704 out_8(info2->cmap_adr + 0xb0, i); in offbcon_blank()
708 out_8(info2->cmap_adr + 0xb0, i); in offbcon_blank()
780 out_8(info2->cmap_adr + 0xb0, regno); in offb_setcolreg()
789 out_8(info2->cmap_adr + 0xb0, regno); in offb_setcolreg()
795 out_8(info2->cmap_adr + 0xb0, regno); in offb_setcolreg()
/linux-2.4.37.9/drivers/net/
Dmace.c291 out_8(&mb->biucc, SWRST); in mace_reset()
303 out_8(&mb->imr, 0xff); /* disable all intrs for now */ in mace_reset()
305 out_8(&mb->maccc, 0); /* turn off tx, rx */ in mace_reset()
307 out_8(&mb->biucc, XMTSP_64); in mace_reset()
308 out_8(&mb->utr, RTRD); in mace_reset()
309 out_8(&mb->fifocc, RCVFW_32 | XMTFW_16 | XMTFWU | RCVFWU | XMTBRST); in mace_reset()
310 out_8(&mb->xmtfc, AUTO_PAD_XMIT); /* auto-pad short frames */ in mace_reset()
311 out_8(&mb->rcvfc, 0); in mace_reset()
318 out_8(&mb->iac, LOGADDR); in mace_reset()
320 out_8(&mb->iac, ADDRCHG | LOGADDR); in mace_reset()
[all …]
Dhplance.c123 out_8(va+DIO_IDOFF, 0xff); in hplance_init()
216 out_8(&(hpregs->status), LE_IE); in hplance_open()
225 out_8(&(hpregs->status), 8); /* disable interrupts at boardlevel */ in hplance_close()
D8390.h129 #define outb(val,port) out_8(port,val)
131 #define outb_p(val,port) out_8(port,val)
/linux-2.4.37.9/arch/m68k/hp300/
Dtime.c66 out_8(CLOCKBASE + CLKCR2, 0x1); /* select CR1 */ in hp300_sched_init()
67 out_8(CLOCKBASE + CLKCR1, 0x1); /* reset */ in hp300_sched_init()
73 out_8(CLOCKBASE + CLKCR2, 0x1); /* select CR1 */ in hp300_sched_init()
74 out_8(CLOCKBASE + CLKCR1, 0x40); /* enable irq */ in hp300_sched_init()
Dhil.c31 #define hil_command(x) out_8(HILBASE + HIL_CMD, (x))
33 #define hil_write_data(x) out_8(HILBASE + HIL_DATA, (x))
/linux-2.4.37.9/include/asm-m68k/
Dio.h191 #define isa_outb(val,port) out_8(isa_itb(port),(val))
196 #define isa_writeb(val,p) out_8(isa_mtb(p),(val))
261 #define writeb(val,addr) out_8((addr),(val))
266 #define outb(val,port) out_8((port),(val))
281 #define outb(val,port) ((port)<1024 ? isa_outb((val),(port)) : out_8((port),(val)))
282 #define outb_p(val,port) ((port)<1024 ? isa_outb_p((val),(port)) : out_8((port),(val)))
Dkeyboard.h71 #define kbd_write_output(val) out_8(KBD_DATA_REG, val)
72 #define kbd_write_command(val) out_8(KBD_CNTL_REG, val)
Draw_io.h41 #define out_8(addr,b) (void)((*(volatile unsigned char *) (addr)) = (b)) macro
51 #define raw_outb(val,port) out_8((port),(val))
70 out_8(port, *buf++); in raw_outsb()
Dide.h112 #define outb(val, port) out_8(port, val)
122 #define writeb(val, port) out_8(port, val)
/linux-2.4.37.9/arch/ppc/platforms/
Dpmac_time.c184 out_8(&via[ACR], (via[ACR] & ~T1MODE) | T1MODE_CONT); in via_calibrate_decr()
186 out_8(&via[T1CH], 2); in via_calibrate_decr()
188 out_8(&via[T1LL], count); in via_calibrate_decr()
189 out_8(&via[T1LH], count >> 8); in via_calibrate_decr()
Dpmac_nvram.c142 out_8(base, CORE99_FLASH_CMD_ERASE_SETUP); in core99_erase_bank()
143 out_8(base, CORE99_FLASH_CMD_ERASE_CONFIRM); in core99_erase_bank()
146 out_8(base, CORE99_FLASH_CMD_RESET); in core99_erase_bank()
167 out_8(base+i, CORE99_FLASH_CMD_WRITE_SETUP); in core99_write_bank()
168 out_8(base+i, datas[i]); in core99_write_bank()
174 out_8(base, CORE99_FLASH_CMD_RESET); in core99_write_bank()
Dpmac_smp.c90 #define PSURGE_QUAD_OUT(r, v) (out_8(quad_base + ((r) << 4) + 4, (v)))
157 out_8(psurge_sec_intr, 0); in psurge_set_ipi()
167 out_8(psurge_sec_intr, ~0); in psurge_clr_ipi()
276 out_8(psurge_sec_intr, ~0); in psurge_quad_init()
/linux-2.4.37.9/include/asm-ppc/
Dio.h47 #define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
147 #define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val))
155 #define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val))
313 extern inline void out_8(volatile unsigned char *addr, int val) in out_8() function

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