1 /* 2 * arch/ppc/platforms/ibm_ocp.h 3 * 4 * Definitions for the on-chip peripherals on the IBM 5 * PPC405GP embedded processor. 6 * 7 * Copyright 2001 MontaVista Softare Inc. 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 * 14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * 25 * You should have received a copy of the GNU General Public License along 26 * with this program; if not, write to the Free Software Foundation, Inc., 27 * 675 Mass Ave, Cambridge, MA 02139, USA. 28 * 29 */ 30 31 #ifdef __KERNEL__ 32 #ifndef __ASM_IBM_OCP_H__ 33 #define __ASM_IBM_OCP_H__ 34 35 #ifndef __ASSEMBLY__ 36 #include <linux/types.h> 37 38 // 39 // TODO: DEPRECATE THIS FILE ! 40 // 41 42 /* PCI 32 */ 43 44 struct pmm_regs { 45 u32 la; 46 u32 ma; 47 u32 pcila; 48 u32 pciha; 49 }; 50 51 typedef struct pcil0_regs { 52 struct pmm_regs pmm[3]; 53 u32 ptm1ms; 54 u32 ptm1la; 55 u32 ptm2ms; 56 u32 ptm2la; 57 } pci0_t; 58 59 /* Serial Ports */ 60 61 #define thr rbr 62 #define iir fcr 63 #define dll rbr 64 #define dlm ier 65 66 typedef struct NS16550 { 67 u8 rbr; /* 0 */ 68 u8 ier; /* 1 */ 69 u8 fcr; /* 2 */ 70 u8 lcr; /* 3 */ 71 u8 mcr; /* 4 */ 72 u8 lsr; /* 5 */ 73 u8 msr; /* 6 */ 74 u8 scr; /* 7 */ 75 } uart_t; 76 77 /* I2c */ 78 typedef struct iic_regs { 79 u16 mdbuf; 80 u16 sbbuf; 81 u8 lmadr; 82 u8 hmadr; 83 u8 cntl; 84 u8 mdcntl; 85 u8 sts; 86 u8 extsts; 87 u8 lsadr; 88 u8 hsadr; 89 u8 clkdiv; 90 u8 intmsk; 91 u8 xfrcnt; 92 u8 xtcntlss; 93 u8 directcntl; 94 } iic_t; 95 96 /* OPB arbiter */ 97 typedef struct opb { 98 u8 pr; 99 u8 cr; 100 } opb_t; 101 102 /* General purpose i/o */ 103 104 typedef struct gpio_regs { 105 u32 or; 106 u32 tcr; 107 u32 pad[4]; 108 u32 odr; 109 u32 ir; 110 } gpio_t; 111 112 /* Structure of the memory mapped IDE control. 113 */ 114 typedef struct ide_regs { 115 unsigned int si_stat; /* IDE status */ 116 unsigned int si_intenable; /* IDE interrupt enable */ 117 unsigned int si_control; /* IDE control */ 118 unsigned int pad0[0x3d]; 119 unsigned int si_c0rt; /* Chan 0 Register transfer timing */ 120 unsigned int si_c0fpt; /* Chan 0 Fast PIO transfer timing */ 121 unsigned int si_c0timo; /* Chan 0 timeout */ 122 unsigned int pad1[2]; 123 unsigned int si_c0d0u; /* Chan 0 UDMA transfer timing */ 124 #define si_c0d0m si_c0d0u /* Chan 0 Multiword DMA timing */ 125 unsigned int pad2; 126 unsigned int si_c0d1u; /* Chan 0 dev 1 UDMA timing */ 127 #define si_c0d1m si_c0d1u /* Chan 0 dev 1 Multiword DMA timing */ 128 unsigned int si_c0c; /* Chan 0 Control */ 129 unsigned int si_c0s0; /* Chan 0 Status 0 */ 130 unsigned int si_c0ie; /* Chan 0 Interrupt Enable */ 131 unsigned int si_c0s1; /* Chan 0 Status 0 */ 132 unsigned int pad4[4]; 133 unsigned int si_c0dcm; /* Chan 0 DMA Command */ 134 unsigned int si_c0tb; /* Chan 0 PRD Table base address */ 135 unsigned int si_c0dct; /* Chan 0 DMA Count */ 136 unsigned int si_c0da; /* Chan 0 DMA Address */ 137 unsigned int si_c0sr; /* Chan 0 Slew Rate Output Control */ 138 unsigned char pad5[0xa2]; 139 unsigned short si_c0adc; /* Chan 0 Alt status/control */ 140 unsigned char si_c0d; /* Chan 0 data */ 141 unsigned char si_c0ef; /* Chan 0 error/features */ 142 unsigned char si_c0sct; /* Chan 0 sector count */ 143 unsigned char si_c0sn; /* Chan 0 sector number */ 144 unsigned char si_c0cl; /* Chan 0 cylinder low */ 145 unsigned char si_c0ch; /* Chan 0 cylinder high */ 146 unsigned char si_c0dh; /* Chan 0 device/head */ 147 unsigned char si_c0scm; /* Chan 0 status/command */ 148 } ide_t; 149 150 #endif /* __ASSEMBLY__ */ 151 #endif /* __ASM_IBM_OCP_H__ */ 152 #endif /* __KERNEL__ */ 153