1 /* cpwatchdog.c - driver implementation for hardware watchdog
2 * timers found on Sun Microsystems CP1400 and CP1500 boards.
3 *
4 * This device supports both the generic Linux watchdog
5 * interface and Solaris-compatible ioctls as best it is
6 * able.
7 *
8 * NOTE: CP1400 systems appear to have a defective intr_mask
9 * register on the PLD, preventing the disabling of
10 * timer interrupts. We use a timer to periodically
11 * reset 'stopped' watchdogs on affected platforms.
12 *
13 * TODO: DevFS support (/dev/watchdogs/0 ... /dev/watchdogs/2)
14 *
15 * Copyright (c) 2000 Eric Brower (ebrower@usa.net)
16 */
17
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/version.h>
21 #include <linux/fs.h>
22 #include <linux/errno.h>
23 #include <linux/major.h>
24 #include <linux/init.h>
25 #include <linux/miscdevice.h>
26 #include <linux/sched.h>
27 #include <linux/interrupt.h>
28 #include <linux/ioport.h>
29 #include <linux/timer.h>
30 #include <asm/irq.h>
31 #include <asm/ebus.h>
32 #include <asm/oplib.h>
33 #include <asm/uaccess.h>
34
35 #include <asm/watchdog.h>
36
37 #define WD_OBPNAME "watchdog"
38 #define WD_BADMODEL "SUNW,501-5336"
39 #define WD_BTIMEOUT (jiffies + (HZ * 1000))
40 #define WD_BLIMIT 0xFFFF
41
42 #define WD0_DEVNAME "watchdog0"
43 #define WD1_DEVNAME "watchdog1"
44 #define WD2_DEVNAME "watchdog2"
45
46 #define WD0_MINOR 212
47 #define WD1_MINOR 213
48 #define WD2_MINOR 214
49
50
51 /* Internal driver definitions
52 */
53 #define WD0_ID 0 /* Watchdog0 */
54 #define WD1_ID 1 /* Watchdog1 */
55 #define WD2_ID 2 /* Watchdog2 */
56 #define WD_NUMDEVS 3 /* Device contains 3 timers */
57
58 #define WD_INTR_OFF 0 /* Interrupt disable value */
59 #define WD_INTR_ON 1 /* Interrupt enable value */
60
61 #define WD_STAT_INIT 0x01 /* Watchdog timer is initialized */
62 #define WD_STAT_BSTOP 0x02 /* Watchdog timer is brokenstopped */
63 #define WD_STAT_SVCD 0x04 /* Watchdog interrupt occurred */
64
65 /* Register value definitions
66 */
67 #define WD0_INTR_MASK 0x01 /* Watchdog device interrupt masks */
68 #define WD1_INTR_MASK 0x02
69 #define WD2_INTR_MASK 0x04
70
71 #define WD_S_RUNNING 0x01 /* Watchdog device status running */
72 #define WD_S_EXPIRED 0x02 /* Watchdog device status expired */
73
74 /* Sun uses Altera PLD EPF8820ATC144-4
75 * providing three hardware watchdogs:
76 *
77 * 1) RIC - sends an interrupt when triggered
78 * 2) XIR - asserts XIR_B_RESET when triggered, resets CPU
79 * 3) POR - asserts POR_B_RESET when triggered, resets CPU, backplane, board
80 *
81 *** Timer register block definition (struct wd_timer_regblk)
82 *
83 * dcntr and limit registers (halfword access):
84 * -------------------
85 * | 15 | ...| 1 | 0 |
86 * -------------------
87 * |- counter val -|
88 * -------------------
89 * dcntr - Current 16-bit downcounter value.
90 * When downcounter reaches '0' watchdog expires.
91 * Reading this register resets downcounter with 'limit' value.
92 * limit - 16-bit countdown value in 1/10th second increments.
93 * Writing this register begins countdown with input value.
94 * Reading from this register does not affect counter.
95 * NOTES: After watchdog reset, dcntr and limit contain '1'
96 *
97 * status register (byte access):
98 * ---------------------------
99 * | 7 | ... | 2 | 1 | 0 |
100 * --------------+------------
101 * |- UNUSED -| EXP | RUN |
102 * ---------------------------
103 * status- Bit 0 - Watchdog is running
104 * Bit 1 - Watchdog has expired
105 *
106 *** PLD register block definition (struct wd_pld_regblk)
107 *
108 * intr_mask register (byte access):
109 * ---------------------------------
110 * | 7 | ... | 3 | 2 | 1 | 0 |
111 * +-------------+------------------
112 * |- UNUSED -| WD3 | WD2 | WD1 |
113 * ---------------------------------
114 * WD3 - 1 == Interrupt disabled for watchdog 3
115 * WD2 - 1 == Interrupt disabled for watchdog 2
116 * WD1 - 1 == Interrupt disabled for watchdog 1
117 *
118 * pld_status register (byte access):
119 * UNKNOWN, MAGICAL MYSTERY REGISTER
120 *
121 */
122 struct wd_timer_regblk {
123 volatile __u16 dcntr; /* down counter - hw */
124 volatile __u16 dcntr_pad;
125 volatile __u16 limit; /* limit register - hw */
126 volatile __u16 limit_pad;
127 volatile __u8 status; /* status register - b */
128 volatile __u8 status_pad;
129 volatile __u16 status_pad2;
130 volatile __u32 pad32; /* yet more padding */
131 };
132
133 struct wd_pld_regblk {
134 volatile __u8 intr_mask; /* interrupt mask - b */
135 volatile __u8 intr_mask_pad;
136 volatile __u16 intr_mask_pad2;
137 volatile __u8 status; /* device status - b */
138 volatile __u8 status_pad;
139 volatile __u16 status_pad2;
140 };
141
142 struct wd_regblk {
143 volatile struct wd_timer_regblk wd0_regs;
144 volatile struct wd_timer_regblk wd1_regs;
145 volatile struct wd_timer_regblk wd2_regs;
146 volatile struct wd_pld_regblk pld_regs;
147 };
148
149 /* Individual timer structure
150 */
151 struct wd_timer {
152 __u16 timeout;
153 __u8 intr_mask;
154 unsigned char runstatus;
155 volatile struct wd_timer_regblk* regs;
156 };
157
158 /* Device structure
159 */
160 struct wd_device {
161 int irq;
162 spinlock_t lock;
163 unsigned char isbaddoggie; /* defective PLD */
164 unsigned char opt_enable;
165 unsigned char opt_reboot;
166 unsigned short opt_timeout;
167 unsigned char initialized;
168 struct wd_timer watchdog[WD_NUMDEVS];
169 volatile struct wd_regblk* regs;
170 };
171
172 static struct wd_device wd_dev = {
173 0, SPIN_LOCK_UNLOCKED, 0, 0, 0, 0,
174 };
175
176 static struct timer_list wd_timer;
177
178 static int wd0_timeout = 0;
179 static int wd1_timeout = 0;
180 static int wd2_timeout = 0;
181
182 #ifdef MODULE
183 EXPORT_NO_SYMBOLS;
184
185 MODULE_PARM (wd0_timeout, "i");
186 MODULE_PARM_DESC(wd0_timeout, "Default watchdog0 timeout in 1/10secs");
187 MODULE_PARM (wd1_timeout, "i");
188 MODULE_PARM_DESC(wd1_timeout, "Default watchdog1 timeout in 1/10secs");
189 MODULE_PARM (wd2_timeout, "i");
190 MODULE_PARM_DESC(wd2_timeout, "Default watchdog2 timeout in 1/10secs");
191
192 MODULE_AUTHOR
193 ("Eric Brower <ebrower@usa.net>");
194 MODULE_DESCRIPTION
195 ("Hardware watchdog driver for Sun Microsystems CP1400/1500");
196 MODULE_LICENSE("GPL");
197 MODULE_SUPPORTED_DEVICE
198 ("watchdog");
199 #endif /* ifdef MODULE */
200
201 /* Forward declarations of internal methods
202 */
203 #ifdef WD_DEBUG
204 static void wd_dumpregs(void);
205 #endif
206 static void wd_interrupt(int irq, void *dev_id, struct pt_regs *regs);
207 static void wd_toggleintr(struct wd_timer* pTimer, int enable);
208 static void wd_pingtimer(struct wd_timer* pTimer);
209 static void wd_starttimer(struct wd_timer* pTimer);
210 static void wd_resetbrokentimer(struct wd_timer* pTimer);
211 static void wd_stoptimer(struct wd_timer* pTimer);
212 static void wd_brokentimer(unsigned long data);
213 static int wd_getstatus(struct wd_timer* pTimer);
214
215 /* PLD expects words to be written in LSB format,
216 * so we must flip all words prior to writing them to regs
217 */
flip_word(unsigned short word)218 static inline unsigned short flip_word(unsigned short word)
219 {
220 return ((word & 0xff) << 8) | ((word >> 8) & 0xff);
221 }
222
223 #define wd_writew(val, addr) (writew(flip_word(val), addr))
224 #define wd_readw(addr) (flip_word(readw(addr)))
225 #define wd_writeb(val, addr) (writeb(val, addr))
226 #define wd_readb(addr) (readb(addr))
227
228
229 /* CP1400s seem to have broken PLD implementations--
230 * the interrupt_mask register cannot be written, so
231 * no timer interrupts can be masked within the PLD.
232 */
wd_isbroken(void)233 static inline int wd_isbroken(void)
234 {
235 /* we could test this by read/write/read/restore
236 * on the interrupt mask register only if OBP
237 * 'watchdog-enable?' == FALSE, but it seems
238 * ubiquitous on CP1400s
239 */
240 char val[32];
241 prom_getproperty(prom_root_node, "model", val, sizeof(val));
242 return((!strcmp(val, WD_BADMODEL)) ? 1 : 0);
243 }
244
245 /* Retrieve watchdog-enable? option from OBP
246 * Returns 0 if false, 1 if true
247 */
wd_opt_enable(void)248 static inline int wd_opt_enable(void)
249 {
250 int opt_node;
251
252 opt_node = prom_getchild(prom_root_node);
253 opt_node = prom_searchsiblings(opt_node, "options");
254 return((-1 == prom_getint(opt_node, "watchdog-enable?")) ? 0 : 1);
255 }
256
257 /* Retrieve watchdog-reboot? option from OBP
258 * Returns 0 if false, 1 if true
259 */
wd_opt_reboot(void)260 static inline int wd_opt_reboot(void)
261 {
262 int opt_node;
263
264 opt_node = prom_getchild(prom_root_node);
265 opt_node = prom_searchsiblings(opt_node, "options");
266 return((-1 == prom_getint(opt_node, "watchdog-reboot?")) ? 0 : 1);
267 }
268
269 /* Retrieve watchdog-timeout option from OBP
270 * Returns OBP value, or 0 if not located
271 */
wd_opt_timeout(void)272 static inline int wd_opt_timeout(void)
273 {
274 int opt_node;
275 char value[32];
276 char *p = value;
277
278 opt_node = prom_getchild(prom_root_node);
279 opt_node = prom_searchsiblings(opt_node, "options");
280 opt_node = prom_getproperty(opt_node,
281 "watchdog-timeout",
282 value,
283 sizeof(value));
284 if(-1 != opt_node) {
285 /* atoi implementation */
286 for(opt_node = 0; /* nop */; p++) {
287 if(*p >= '0' && *p <= '9') {
288 opt_node = (10*opt_node)+(*p-'0');
289 }
290 else {
291 break;
292 }
293 }
294 }
295 return((-1 == opt_node) ? (0) : (opt_node));
296 }
297
wd_open(struct inode * inode,struct file * f)298 static int wd_open(struct inode *inode, struct file *f)
299 {
300 switch(MINOR(inode->i_rdev))
301 {
302 case WD0_MINOR:
303 f->private_data = &wd_dev.watchdog[WD0_ID];
304 break;
305 case WD1_MINOR:
306 f->private_data = &wd_dev.watchdog[WD1_ID];
307 break;
308 case WD2_MINOR:
309 f->private_data = &wd_dev.watchdog[WD2_ID];
310 break;
311 default:
312 return(-ENODEV);
313 }
314
315 /* Register IRQ on first open of device */
316 if(0 == wd_dev.initialized)
317 {
318 if (request_irq(wd_dev.irq,
319 &wd_interrupt,
320 SA_SHIRQ,
321 WD_OBPNAME,
322 (void *)wd_dev.regs)) {
323 printk("%s: Cannot register IRQ %s\n",
324 WD_OBPNAME, __irq_itoa(wd_dev.irq));
325 return(-EBUSY);
326 }
327 wd_dev.initialized = 1;
328 }
329
330 MOD_INC_USE_COUNT;
331 return(0);
332 }
333
wd_release(struct inode * inode,struct file * file)334 static int wd_release(struct inode *inode, struct file *file)
335 {
336 MOD_DEC_USE_COUNT;
337 return 0;
338 }
339
wd_ioctl(struct inode * inode,struct file * file,unsigned int cmd,unsigned long arg)340 static int wd_ioctl(struct inode *inode, struct file *file,
341 unsigned int cmd, unsigned long arg)
342 {
343 int setopt = 0;
344 struct wd_timer* pTimer = (struct wd_timer*)file->private_data;
345 struct watchdog_info info = {
346 0,
347 0,
348 "Altera EPF8820ATC144-4"
349 };
350
351 if(NULL == pTimer) {
352 return(-EINVAL);
353 }
354
355 switch(cmd)
356 {
357 /* Generic Linux IOCTLs */
358 case WDIOC_GETSUPPORT:
359 if(copy_to_user((struct watchdog_info *)arg,
360 (struct watchdog_info *)&info,
361 sizeof(struct watchdog_info))) {
362 return(-EFAULT);
363 }
364 break;
365 case WDIOC_GETSTATUS:
366 case WDIOC_GETBOOTSTATUS:
367 if (put_user(0, (int *) arg))
368 return -EFAULT;
369 break;
370 case WDIOC_KEEPALIVE:
371 wd_pingtimer(pTimer);
372 break;
373 case WDIOC_SETOPTIONS:
374 if(copy_from_user(&setopt, (void*) arg, sizeof(unsigned int))) {
375 return -EFAULT;
376 }
377 if(setopt & WDIOS_DISABLECARD) {
378 if(wd_dev.opt_enable) {
379 printk(
380 "%s: cannot disable watchdog in ENABLED mode\n",
381 WD_OBPNAME);
382 return(-EINVAL);
383 }
384 wd_stoptimer(pTimer);
385 }
386 else if(setopt & WDIOS_ENABLECARD) {
387 wd_starttimer(pTimer);
388 }
389 else {
390 return(-EINVAL);
391 }
392 break;
393 /* Solaris-compatible IOCTLs */
394 case WIOCGSTAT:
395 setopt = wd_getstatus(pTimer);
396 if(copy_to_user((void*)arg, &setopt, sizeof(unsigned int))) {
397 return(-EFAULT);
398 }
399 break;
400 case WIOCSTART:
401 wd_starttimer(pTimer);
402 break;
403 case WIOCSTOP:
404 if(wd_dev.opt_enable) {
405 printk("%s: cannot disable watchdog in ENABLED mode\n",
406 WD_OBPNAME);
407 return(-EINVAL);
408 }
409 wd_stoptimer(pTimer);
410 break;
411 default:
412 return(-EINVAL);
413 }
414 return(0);
415 }
416
wd_write(struct file * file,const char * buf,size_t count,loff_t * ppos)417 static ssize_t wd_write( struct file *file,
418 const char *buf,
419 size_t count,
420 loff_t *ppos)
421 {
422 struct wd_timer* pTimer = (struct wd_timer*)file->private_data;
423
424 if(NULL == pTimer) {
425 return(-EINVAL);
426 }
427
428 if (ppos != &file->f_pos)
429 return -ESPIPE;
430
431 if (count) {
432 wd_pingtimer(pTimer);
433 return 1;
434 }
435 return 0;
436 }
437
wd_read(struct file * file,char * buffer,size_t count,loff_t * ppos)438 static ssize_t wd_read(struct file * file, char * buffer,
439 size_t count, loff_t *ppos)
440 {
441 #ifdef WD_DEBUG
442 wd_dumpregs();
443 return(0);
444 #else
445 return(-EINVAL);
446 #endif /* ifdef WD_DEBUG */
447 }
448
wd_interrupt(int irq,void * dev_id,struct pt_regs * regs)449 static void wd_interrupt(int irq, void *dev_id, struct pt_regs *regs)
450 {
451 /* Only WD0 will interrupt-- others are NMI and we won't
452 * see them here....
453 */
454 spin_lock_irq(&wd_dev.lock);
455 if((unsigned long)wd_dev.regs == (unsigned long)dev_id)
456 {
457 wd_stoptimer(&wd_dev.watchdog[WD0_ID]);
458 wd_dev.watchdog[WD0_ID].runstatus |= WD_STAT_SVCD;
459 }
460 spin_unlock_irq(&wd_dev.lock);
461 return;
462 }
463
464 static struct file_operations wd_fops = {
465 owner: THIS_MODULE,
466 ioctl: wd_ioctl,
467 open: wd_open,
468 write: wd_write,
469 read: wd_read,
470 release: wd_release,
471 };
472
473 static struct miscdevice wd0_miscdev = { WD0_MINOR, WD0_DEVNAME, &wd_fops };
474 static struct miscdevice wd1_miscdev = { WD1_MINOR, WD1_DEVNAME, &wd_fops };
475 static struct miscdevice wd2_miscdev = { WD2_MINOR, WD2_DEVNAME, &wd_fops };
476
477 #ifdef WD_DEBUG
wd_dumpregs(void)478 static void wd_dumpregs(void)
479 {
480 /* Reading from downcounters initiates watchdog countdown--
481 * Example is included below for illustration purposes.
482 */
483 int i;
484 printk("%s: dumping register values\n", WD_OBPNAME);
485 for(i = WD0_ID; i < WD_NUMDEVS; ++i) {
486 /* printk("\t%s%i: dcntr at 0x%lx: 0x%x\n",
487 * WD_OBPNAME,
488 * i,
489 * (unsigned long)(&wd_dev.watchdog[i].regs->dcntr),
490 * readw(&wd_dev.watchdog[i].regs->dcntr));
491 */
492 printk("\t%s%i: limit at 0x%lx: 0x%x\n",
493 WD_OBPNAME,
494 i,
495 (unsigned long)(&wd_dev.watchdog[i].regs->limit),
496 readw(&wd_dev.watchdog[i].regs->limit));
497 printk("\t%s%i: status at 0x%lx: 0x%x\n",
498 WD_OBPNAME,
499 i,
500 (unsigned long)(&wd_dev.watchdog[i].regs->status),
501 readb(&wd_dev.watchdog[i].regs->status));
502 printk("\t%s%i: driver status: 0x%x\n",
503 WD_OBPNAME,
504 i,
505 wd_getstatus(&wd_dev.watchdog[i]));
506 }
507 printk("\tintr_mask at 0x%lx: 0x%x\n",
508 (unsigned long)(&wd_dev.regs->pld_regs.intr_mask),
509 readb(&wd_dev.regs->pld_regs.intr_mask));
510 printk("\tpld_status at 0x%lx: 0x%x\n",
511 (unsigned long)(&wd_dev.regs->pld_regs.status),
512 readb(&wd_dev.regs->pld_regs.status));
513 }
514 #endif
515
516 /* Enable or disable watchdog interrupts
517 * Because of the CP1400 defect this should only be
518 * called during initialzation or by wd_[start|stop]timer()
519 *
520 * pTimer - pointer to timer device, or NULL to indicate all timers
521 * enable - non-zero to enable interrupts, zero to disable
522 */
wd_toggleintr(struct wd_timer * pTimer,int enable)523 static void wd_toggleintr(struct wd_timer* pTimer, int enable)
524 {
525 unsigned char curregs = wd_readb(&wd_dev.regs->pld_regs.intr_mask);
526 unsigned char setregs =
527 (NULL == pTimer) ?
528 (WD0_INTR_MASK | WD1_INTR_MASK | WD2_INTR_MASK) :
529 (pTimer->intr_mask);
530
531 (WD_INTR_ON == enable) ?
532 (curregs &= ~setregs):
533 (curregs |= setregs);
534
535 wd_writeb(curregs, &wd_dev.regs->pld_regs.intr_mask);
536 return;
537 }
538
539 /* Reset countdown timer with 'limit' value and continue countdown.
540 * This will not start a stopped timer.
541 *
542 * pTimer - pointer to timer device
543 */
wd_pingtimer(struct wd_timer * pTimer)544 static void wd_pingtimer(struct wd_timer* pTimer)
545 {
546 if(wd_readb(&pTimer->regs->status) & WD_S_RUNNING) {
547 wd_readw(&pTimer->regs->dcntr);
548 }
549 }
550
551 /* Stop a running watchdog timer-- the timer actually keeps
552 * running, but the interrupt is masked so that no action is
553 * taken upon expiration.
554 *
555 * pTimer - pointer to timer device
556 */
wd_stoptimer(struct wd_timer * pTimer)557 static void wd_stoptimer(struct wd_timer* pTimer)
558 {
559 if(wd_readb(&pTimer->regs->status) & WD_S_RUNNING) {
560 wd_toggleintr(pTimer, WD_INTR_OFF);
561
562 if(wd_dev.isbaddoggie) {
563 pTimer->runstatus |= WD_STAT_BSTOP;
564 wd_brokentimer((unsigned long)&wd_dev);
565 }
566 }
567 }
568
569 /* Start a watchdog timer with the specified limit value
570 * If the watchdog is running, it will be restarted with
571 * the provided limit value.
572 *
573 * This function will enable interrupts on the specified
574 * watchdog.
575 *
576 * pTimer - pointer to timer device
577 * limit - limit (countdown) value in 1/10th seconds
578 */
wd_starttimer(struct wd_timer * pTimer)579 static void wd_starttimer(struct wd_timer* pTimer)
580 {
581 if(wd_dev.isbaddoggie) {
582 pTimer->runstatus &= ~WD_STAT_BSTOP;
583 }
584 pTimer->runstatus &= ~WD_STAT_SVCD;
585
586 wd_writew(pTimer->timeout, &pTimer->regs->limit);
587 wd_toggleintr(pTimer, WD_INTR_ON);
588 }
589
590 /* Restarts timer with maximum limit value and
591 * does not unset 'brokenstop' value.
592 */
wd_resetbrokentimer(struct wd_timer * pTimer)593 static void wd_resetbrokentimer(struct wd_timer* pTimer)
594 {
595 wd_toggleintr(pTimer, WD_INTR_ON);
596 wd_writew(WD_BLIMIT, &pTimer->regs->limit);
597 }
598
599 /* Timer device initialization helper.
600 * Returns 0 on success, other on failure
601 */
wd_inittimer(int whichdog)602 static int wd_inittimer(int whichdog)
603 {
604 struct miscdevice *whichmisc;
605 volatile struct wd_timer_regblk *whichregs;
606 char whichident[8];
607 int whichmask;
608 __u16 whichlimit;
609
610 switch(whichdog)
611 {
612 case WD0_ID:
613 whichmisc = &wd0_miscdev;
614 strcpy(whichident, "RIC");
615 whichregs = &wd_dev.regs->wd0_regs;
616 whichmask = WD0_INTR_MASK;
617 whichlimit= (0 == wd0_timeout) ?
618 (wd_dev.opt_timeout):
619 (wd0_timeout);
620 break;
621 case WD1_ID:
622 whichmisc = &wd1_miscdev;
623 strcpy(whichident, "XIR");
624 whichregs = &wd_dev.regs->wd1_regs;
625 whichmask = WD1_INTR_MASK;
626 whichlimit= (0 == wd1_timeout) ?
627 (wd_dev.opt_timeout):
628 (wd1_timeout);
629 break;
630 case WD2_ID:
631 whichmisc = &wd2_miscdev;
632 strcpy(whichident, "POR");
633 whichregs = &wd_dev.regs->wd2_regs;
634 whichmask = WD2_INTR_MASK;
635 whichlimit= (0 == wd2_timeout) ?
636 (wd_dev.opt_timeout):
637 (wd2_timeout);
638 break;
639 default:
640 printk("%s: %s: invalid watchdog id: %i\n",
641 WD_OBPNAME, __FUNCTION__, whichdog);
642 return(1);
643 }
644 if(0 != misc_register(whichmisc))
645 {
646 return(1);
647 }
648 wd_dev.watchdog[whichdog].regs = whichregs;
649 wd_dev.watchdog[whichdog].timeout = whichlimit;
650 wd_dev.watchdog[whichdog].intr_mask = whichmask;
651 wd_dev.watchdog[whichdog].runstatus &= ~WD_STAT_BSTOP;
652 wd_dev.watchdog[whichdog].runstatus |= WD_STAT_INIT;
653
654 printk("%s%i: %s hardware watchdog [%01i.%i sec] %s\n",
655 WD_OBPNAME,
656 whichdog,
657 whichident,
658 wd_dev.watchdog[whichdog].timeout / 10,
659 wd_dev.watchdog[whichdog].timeout % 10,
660 (0 != wd_dev.opt_enable) ? "in ENABLED mode" : "");
661 return(0);
662 }
663
664 /* Timer method called to reset stopped watchdogs--
665 * because of the PLD bug on CP1400, we cannot mask
666 * interrupts within the PLD so me must continually
667 * reset the timers ad infinitum.
668 */
wd_brokentimer(unsigned long data)669 static void wd_brokentimer(unsigned long data)
670 {
671 struct wd_device* pDev = (struct wd_device*)data;
672 int id, tripped = 0;
673
674 /* kill a running timer instance, in case we
675 * were called directly instead of by kernel timer
676 */
677 if(timer_pending(&wd_timer)) {
678 del_timer(&wd_timer);
679 }
680
681 for(id = WD0_ID; id < WD_NUMDEVS; ++id) {
682 if(pDev->watchdog[id].runstatus & WD_STAT_BSTOP) {
683 ++tripped;
684 wd_resetbrokentimer(&pDev->watchdog[id]);
685 }
686 }
687
688 if(tripped) {
689 /* there is at least one timer brokenstopped-- reschedule */
690 wd_timer.expires = WD_BTIMEOUT;
691 add_timer(&wd_timer);
692 }
693 }
694
wd_getstatus(struct wd_timer * pTimer)695 static int wd_getstatus(struct wd_timer* pTimer)
696 {
697 unsigned char stat = wd_readb(&pTimer->regs->status);
698 unsigned char intr = wd_readb(&wd_dev.regs->pld_regs.intr_mask);
699 unsigned char ret = WD_STOPPED;
700
701 /* determine STOPPED */
702 if(0 == stat ) {
703 return(ret);
704 }
705 /* determine EXPIRED vs FREERUN vs RUNNING */
706 else if(WD_S_EXPIRED & stat) {
707 ret = WD_EXPIRED;
708 }
709 else if(WD_S_RUNNING & stat) {
710 if(intr & pTimer->intr_mask) {
711 ret = WD_FREERUN;
712 }
713 else {
714 /* Fudge WD_EXPIRED status for defective CP1400--
715 * IF timer is running
716 * AND brokenstop is set
717 * AND an interrupt has been serviced
718 * we are WD_EXPIRED.
719 *
720 * IF timer is running
721 * AND brokenstop is set
722 * AND no interrupt has been serviced
723 * we are WD_FREERUN.
724 */
725 if(wd_dev.isbaddoggie && (pTimer->runstatus & WD_STAT_BSTOP)) {
726 if(pTimer->runstatus & WD_STAT_SVCD) {
727 ret = WD_EXPIRED;
728 }
729 else {
730 /* we could as well pretend we are expired */
731 ret = WD_FREERUN;
732 }
733 }
734 else {
735 ret = WD_RUNNING;
736 }
737 }
738 }
739
740 /* determine SERVICED */
741 if(pTimer->runstatus & WD_STAT_SVCD) {
742 ret |= WD_SERVICED;
743 }
744
745 return(ret);
746 }
747
wd_init(void)748 static int __init wd_init(void)
749 {
750 int id;
751 struct linux_ebus *ebus = NULL;
752 struct linux_ebus_device *edev = NULL;
753
754 for_each_ebus(ebus) {
755 for_each_ebusdev(edev, ebus) {
756 if (!strcmp(edev->prom_name, WD_OBPNAME))
757 goto ebus_done;
758 }
759 }
760
761 ebus_done:
762 if(!edev) {
763 printk("%s: unable to locate device\n", WD_OBPNAME);
764 return -ENODEV;
765 }
766
767 wd_dev.regs =
768 ioremap(edev->resource[0].start, sizeof(struct wd_regblk));
769
770 if(NULL == wd_dev.regs) {
771 printk("%s: unable to map registers\n", WD_OBPNAME);
772 return(-ENODEV);
773 }
774
775 /* initialize device structure from OBP parameters */
776 wd_dev.irq = edev->irqs[0];
777 wd_dev.opt_enable = wd_opt_enable();
778 wd_dev.opt_reboot = wd_opt_reboot();
779 wd_dev.opt_timeout = wd_opt_timeout();
780 wd_dev.isbaddoggie = wd_isbroken();
781
782 /* disable all interrupts unless watchdog-enabled? == true */
783 if(! wd_dev.opt_enable) {
784 wd_toggleintr(NULL, WD_INTR_OFF);
785 }
786
787 /* register miscellaneous devices */
788 for(id = WD0_ID; id < WD_NUMDEVS; ++id) {
789 if(0 != wd_inittimer(id)) {
790 printk("%s%i: unable to initialize\n", WD_OBPNAME, id);
791 }
792 }
793
794 /* warn about possible defective PLD */
795 if(wd_dev.isbaddoggie) {
796 init_timer(&wd_timer);
797 wd_timer.function = wd_brokentimer;
798 wd_timer.data = (unsigned long)&wd_dev;
799 wd_timer.expires = WD_BTIMEOUT;
800
801 printk("%s: PLD defect workaround enabled for model %s\n",
802 WD_OBPNAME, WD_BADMODEL);
803 }
804 return(0);
805 }
806
wd_cleanup(void)807 static void __exit wd_cleanup(void)
808 {
809 int id;
810
811 /* if 'watchdog-enable?' == TRUE, timers are not stopped
812 * when module is unloaded. All brokenstopped timers will
813 * also now eventually trip.
814 */
815 for(id = WD0_ID; id < WD_NUMDEVS; ++id) {
816 if(WD_S_RUNNING == wd_readb(&wd_dev.watchdog[id].regs->status)) {
817 if(wd_dev.opt_enable) {
818 printk(KERN_WARNING "%s%i: timer not stopped at release\n",
819 WD_OBPNAME, id);
820 }
821 else {
822 wd_stoptimer(&wd_dev.watchdog[id]);
823 if(wd_dev.watchdog[id].runstatus & WD_STAT_BSTOP) {
824 wd_resetbrokentimer(&wd_dev.watchdog[id]);
825 printk(KERN_WARNING
826 "%s%i: defect workaround disabled at release, "\
827 "timer expires in ~%01i sec\n",
828 WD_OBPNAME, id,
829 wd_readw(&wd_dev.watchdog[id].regs->limit) / 10);
830 }
831 }
832 }
833 }
834
835 if(wd_dev.isbaddoggie && timer_pending(&wd_timer)) {
836 del_timer(&wd_timer);
837 }
838 if(0 != (wd_dev.watchdog[WD0_ID].runstatus & WD_STAT_INIT)) {
839 misc_deregister(&wd0_miscdev);
840 }
841 if(0 != (wd_dev.watchdog[WD1_ID].runstatus & WD_STAT_INIT)) {
842 misc_deregister(&wd1_miscdev);
843 }
844 if(0 != (wd_dev.watchdog[WD2_ID].runstatus & WD_STAT_INIT)) {
845 misc_deregister(&wd2_miscdev);
846 }
847 if(0 != wd_dev.initialized) {
848 free_irq(wd_dev.irq, (void *)wd_dev.regs);
849 }
850 iounmap(wd_dev.regs);
851 }
852
853 module_init(wd_init);
854 module_exit(wd_cleanup);
855