| /linux-2.4.37.9/arch/sh/kernel/ |
| D | traps.c | 129 static int handle_unaligned_ins(u16 instruction, struct pt_regs *regs) in handle_unaligned_ins() argument
135 index = (instruction>>8)&15; /* 0x0F00 */ in handle_unaligned_ins()
138 index = (instruction>>4)&15; /* 0x00F0 */ in handle_unaligned_ins()
141 count = 1<<(instruction&3); in handle_unaligned_ins()
144 switch (instruction>>12) { in handle_unaligned_ins()
146 if (instruction & 8) { in handle_unaligned_ins()
190 dst += (instruction&0x000F)<<2; in handle_unaligned_ins()
198 if (instruction & 4) in handle_unaligned_ins()
212 src += (instruction&0x000F)<<2; in handle_unaligned_ins()
223 if (instruction & 4) in handle_unaligned_ins()
[all …]
|
| /linux-2.4.37.9/arch/arm/nwfpe/ |
| D | entry26.S | 71 ldr r0, [r5, #-4] @ get actual instruction into r0
72 bl EmulateAll @ emulate the instruction
77 .Lx1: ldrt r6, [r5], #4 @ get the next instruction and
97 beq next @ get the next instruction;
106 @ We need to be prepared for the instruction at .Lx1 to fault.
|
| D | entry.S | 81 .Lx1: ldrt r0, [r8] @ get actual instruction into r0
83 bl EmulateAll @ emulate the instruction
88 .Lx2: ldrt r6, [r5], #4 @ get the next instruction and
105 beq next @ get the next instruction;
113 @ plain LDR instruction. Weird, but it seems harmless.
|
| D | fpmodule.inl | 25 /* Note: The CPU thinks it has dealt with the current instruction.
27 instruction, and points 4 bytes beyond the actual instruction
28 that caused the invalid instruction trap to occur. We adjust
|
| /linux-2.4.37.9/arch/m68k/fpsp040/ |
| D | bugfix.S | 248 | dest and the dest of the xu. We must clear the instruction in
249 | the cu and restore the state, allowing the instruction in the
250 | xu to complete. Remember, the instruction in the nu
252 | If the result of the xu instruction is not exceptional, we can
253 | restore the instruction from the cu to the frame and continue
276 | Check if the instruction which just completed was exceptional.
281 | It is necessary to isolate the result of the instruction in the
370 | dest and the dest of the xu. We must clear the instruction in
371 | the cu and restore the state, allowing the instruction in the
372 | xu to complete. Remember, the instruction in the nu
[all …]
|
| D | smovecr.S | 5 | offset given in the instruction field.
7 | Input: An offset in the instruction word.
|
| D | x_fline.S | 8 | Next, determine if the instruction is an fmovecr with a non-zero
51 moveal EXC_PC+4(%a6),%a0 |get address of fline instruction
66 | ;if an FMOVECR instruction, fix stack
|
| D | x_unimp.S | 4 | fpsp_unimp --- FPSP handler for unimplemented instruction
19 | instruction.
|
| D | x_ovfl.S | 14 | If the instruction is move_out, then garbage is stored in the
15 | destination. If the instruction is not move_out, then the
|
| /linux-2.4.37.9/arch/arm/lib/ |
| D | backtrace.S | 47 2: stmfd sp!, {pc} @ calculate offset of PC in STMIA instruction
60 1004: ldr r1, [save, #0] @ get instruction at function
72 1005: ldr r1, [save, #4] @ get instruction at function+4
76 addeq save, save, #4 @ next instruction
80 1006: ldr r1, [save, #4] @ Get 'stmia sp!, {rlist, fp, ip, lr, pc}' instruction
|
| /linux-2.4.37.9/Documentation/arm/nwfpe/ |
| D | NOTES | 8 often uses an stfe instruction to save f4 on the stack upon entry to a
9 function, and an ldfe instruction to restore it before returning.
15 This is a side effect of the stfe instruction. The double in f4 had to be
29 in extended precision, due to the stfe instruction used to save f4 in log(y).
|
| /linux-2.4.37.9/arch/ppc/xmon/ |
| D | ppc.h | 109 unsigned long (*insert) PARAMS ((unsigned long instruction, long op,
129 long (*extract) PARAMS ((unsigned long instruction, int *invalid));
|
| /linux-2.4.37.9/arch/ppc64/xmon/ |
| D | ppc.h | 109 unsigned long (*insert) PARAMS ((unsigned long instruction, long op,
129 long (*extract) PARAMS ((unsigned long instruction, int *invalid));
|
| /linux-2.4.37.9/arch/m68k/ifpsp060/ |
| D | CHANGES | 41 3) For an opclass three FP instruction where the effective addressing
62 next instruction, and the result created in fp0 will be
78 For instruction read access errors, the info stacked is:
80 PC = PC of instruction being emulated
82 ADDRESS = PC of instruction being emulated
102 PC = PC of instruction being emulated
|
| D | ilsp.doc | 35 and the "cmp2" instruction. These instructions are not
71 function. A branch instruction located at the selected entry point
78 For example, to use a 64-bit multiply instruction,
115 An example of using the "cmp2" instruction is as follows:
128 If the instruction being emulated is a divide and the source
130 instruction, executes an implemented divide using a zero
133 point to the correct instruction, the user will at least be able
|
| D | fskeleton.S | 111 | instruction.
130 | instruction.
149 | instruction.
168 | instruction.
189 | bit in the FPSR, and does an "rte". The instruction that caused the
227 | frame to the PC of the instruction causing the exception, and does an "rte".
228 | The execution of the instruction then proceeds with an enabled floating-point
245 | This is the exit point for the 060FPSP when an emulated "ftrapcc" instruction
|
| D | os.S | 107 | Reads from data/instruction memory while in supervisor mode.
174 | Read an instruction word from user memory.
180 | d0 - instruction word in d0
210 | Read an instruction longword from user memory.
216 | d0 - instruction longword in d0
|
| D | fplsp.doc | 72 function. A branch instruction located at the selected entry point
79 There are 3 entry-points for each instruction type: single precision,
82 As an example, the "fsin" library instruction can be passed an
111 For example, if the instruction being emulated should cause a
127 the instruction but rather simply executes it.
|
| D | iskeleton.S | 63 | the PC pointing to the instruction following the instruction
65 | To simply continue execution at the next instruction, just
87 | Instruction exception handler. If the instruction was a "chk2"
122 | Instruction exception handler isp_unimp(). If the instruction is a 64-bit
|
| /linux-2.4.37.9/drivers/scsi/aic7xxx_old/ |
| D | sequencer.h | 106 struct instruction { struct
111 struct instruction *stqe_next; argument
|
| /linux-2.4.37.9/drivers/scsi/aic7xxx/aicasm/ |
| D | aicasm.c | 100 static STAILQ_HEAD(,instruction) seq_program;
322 struct instruction *cur_instr; in back_patch()
351 struct instruction *cur_instr; in output_code()
524 struct instruction *cur_instr; in output_listing()
723 struct instruction *
726 struct instruction *new_instr; in seq_alloc()
728 new_instr = (struct instruction *)malloc(sizeof(struct instruction)); in seq_alloc()
|
| D | aicasm_insformat.h | 104 struct instruction { struct
108 STAILQ_ENTRY(instruction) links; argument
|
| /linux-2.4.37.9/drivers/scsi/ |
| D | script_asm.pl | 728 $instruction = $1;
730 if ($instruction =~ /JUMP/i) {
732 } elsif ($instruction =~ /CALL/i) {
771 $instruction = $1;
773 print STDERR "Parsing $instruction\n" if ($debug);
774 $code[$address] = ($instruction =~ /RETURN/i) ? 0x90_00_00_00 :
|
| /linux-2.4.37.9/Documentation/parisc/ |
| D | registers | 56 N (Nullify next instruction) used by C code
94 r1: The addil instruction is hardwired to place its result in r1,
95 so if you use that instruction be aware of that.
116 r31: the ble instruction puts the return pointer in here.
|
| /linux-2.4.37.9/arch/m68k/ifpsp060/src/ |
| D | isp.S | 861 # _imem_read_word() - read instruction word #
862 # _imem_read_long() - read instruction longword #
864 # isp_iacc() - handle instruction access error exception #
1519 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1520 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
1528 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1529 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
1546 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1547 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
1556 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
[all …]
|