1 /*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Board specific pci fixups for the Toshiba rbtx4927
5 *
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * Copyright (C) 2000-2001 Toshiba Corporation
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 */
32 #include <linux/types.h>
33 #include <linux/pci.h>
34 #include <linux/kernel.h>
35 #include <linux/init.h>
36
37 #include <asm/tx4927/tx4927.h>
38 #include <asm/tx4927/tx4927_pci.h>
39
40 #undef DEBUG
41 #ifdef DEBUG
42 #define DBG(x...) printk(x)
43 #else
44 #define DBG(x...)
45 #endif
46
pcibios_fixup_resources(struct pci_dev * dev)47 void __init pcibios_fixup_resources(struct pci_dev *dev)
48 {
49 /* will need to fixup IO resources */
50 }
51
pcibios_fixup(void)52 void __init pcibios_fixup(void)
53 {
54 /* nothing to do here */
55 }
56
57 /* look up table for backplane pci irq for slots 17-20 by pin # */
58 static unsigned char backplane_pci_irq[4][4] = {
59 /* PJ6 SLOT: 17, PIN: 1 */ {TX4927_IRQ_IOC_PCIA,
60 /* PJ6 SLOT: 17, PIN: 2 */
61 TX4927_IRQ_IOC_PCIB,
62 /* PJ6 SLOT: 17, PIN: 3 */
63 TX4927_IRQ_IOC_PCIC,
64 /* PJ6 SLOT: 17, PIN: 4 */
65 TX4927_IRQ_IOC_PCID},
66 /* SB SLOT: 18, PIN: 1 */ {TX4927_IRQ_IOC_PCIB,
67 /* SB SLOT: 18, PIN: 2 */
68 TX4927_IRQ_IOC_PCIC,
69 /* SB SLOT: 18, PIN: 3 */
70 TX4927_IRQ_IOC_PCID,
71 /* SB SLOT: 18, PIN: 4 */
72 TX4927_IRQ_IOC_PCIA},
73 /* PJ5 SLOT: 19, PIN: 1 */ {TX4927_IRQ_IOC_PCIC,
74 /* PJ5 SLOT: 19, PIN: 2 */
75 TX4927_IRQ_IOC_PCID,
76 /* PJ5 SLOT: 19, PIN: 3 */
77 TX4927_IRQ_IOC_PCIA,
78 /* PJ5 SLOT: 19, PIN: 4 */
79 TX4927_IRQ_IOC_PCIB},
80 /* PJ4 SLOT: 20, PIN: 1 */ {TX4927_IRQ_IOC_PCID,
81 /* PJ4 SLOT: 20, PIN: 2 */
82 TX4927_IRQ_IOC_PCIA,
83 /* PJ4 SLOT: 20, PIN: 3 */
84 TX4927_IRQ_IOC_PCIB,
85 /* PJ4 SLOT: 20, PIN: 4 */
86 TX4927_IRQ_IOC_PCIC}
87 };
88
pci_get_irq(struct pci_dev * dev,int pin)89 int pci_get_irq(struct pci_dev *dev, int pin)
90 {
91 unsigned char irq = pin;
92
93 DBG("pci_get_irq: pin is %d\n", pin);
94 /* IRQ rotation */
95 irq--; /* 0-3 */
96 if (dev->bus->parent == NULL &&
97 PCI_SLOT(dev->devfn) == TX4927_PCIC_IDSEL_AD_TO_SLOT(23)) {
98 printk("Onboard PCI_SLOT(dev->devfn) is %d\n",
99 PCI_SLOT(dev->devfn));
100 /* IDSEL=A23 is tx4927 onboard pci slot */
101 irq = (irq + PCI_SLOT(dev->devfn)) % 4;
102 irq++; /* 1-4 */
103 DBG("irq is now %d\n", irq);
104
105 switch (irq) {
106 case 1:
107 irq = TX4927_IRQ_IOC_PCIA;
108 break;
109 case 2:
110 irq = TX4927_IRQ_IOC_PCIB;
111 break;
112 case 3:
113 irq = TX4927_IRQ_IOC_PCIC;
114 break;
115 case 4:
116 irq = TX4927_IRQ_IOC_PCID;
117 break;
118 }
119 } else {
120 /* PCI Backplane */
121 DBG("PCI Backplane PCI_SLOT(dev->devfn) is %d\n",
122 PCI_SLOT(dev->devfn));
123 irq = backplane_pci_irq[PCI_SLOT(dev->devfn) - 17][irq];
124 }
125 DBG("assigned irq %d\n", irq);
126 return irq;
127 }
128
129
130 #ifdef TX4927_SUPPORT_PCI_66
131 extern int tx4927_pci66;
132 extern void tx4927_pci66_setup(void);
133 #endif
134 extern void tx4927_pci_setup(void);
135
136 #ifdef TX4927_SUPPORT_PCI_66
tx4927_pci66_check(void)137 int tx4927_pci66_check(void)
138 {
139 struct pci_dev *dev;
140 unsigned short stat;
141 int cap66 = 1;
142
143 if (tx4927_pci66 < 0)
144 return 0;
145
146 /* check 66MHz capability */
147 pci_for_each_dev(dev) {
148 if (cap66) {
149 pci_read_config_word(dev, PCI_STATUS, &stat);
150 if (!(stat & PCI_STATUS_66MHZ)) {
151 printk(KERN_INFO
152 "PCI: %02x:%02x not 66MHz capable.\n",
153 dev->bus->number, dev->devfn);
154 cap66 = 0;
155 }
156 }
157 }
158 return cap66;
159 }
160 #endif
161
162 #ifdef DEBUG
do_it(u32 offset,u32 reg)163 void do_it(u32 offset, u32 reg)
164 {
165 volatile u32 a1;
166 volatile u32 a2;
167 volatile u32 v1;
168 volatile u32 v2;
169
170 a1 = 0xff1f0000 + offset + reg;
171 a2 = a1 + 4;
172
173 v1 = *(volatile u32 *) a1;
174 v2 = *(volatile u32 *) a2;
175
176 if (v1)
177 printk("TX4927 0x%08x 0x%08x\n", a1, v1);
178 if (v2)
179 printk("TX4927 0x%08x 0x%08x\n", a2, v2);
180 }
181
do_it1(u32 base,u32 r)182 void do_it1(u32 base, u32 r)
183 {
184 do_it(base, r);
185 }
186
do_it2(u32 base,u32 start,u32 stop)187 void do_it2(u32 base, u32 start, u32 stop)
188 {
189 u32 r;
190
191 for (r = start; r <= stop; r += 8) {
192 do_it(base, r);
193 }
194 }
dump_config(void)195 void dump_config(void)
196 {
197 unsigned long id;
198 unsigned long j;
199 struct pci_dev *dev;
200
201 printk("----------------------pci\n");
202 pci_for_each_dev(dev) {
203 for (j = 0; j < 64; j++) {
204 pci_read_config_dword(dev, j * 4, &id);
205 if (id == 0)
206 continue;
207 printk
208 ("dev 0x%02x 0x%02x:0x%02x -- 0x%02x-0x%02x 0x%08x\n",
209 dev->devfn, PCI_SLOT(dev->devfn),
210 PCI_FUNC(dev->devfn), (j * 4) + 3, (j * 4),
211 id);
212 }
213 printk("dev 0x%02x \n", dev->devfn);
214 }
215 printk("----------------------sdram\n");
216 do_it2(0x8000, 0x00, 0x18);
217 do_it1(0x8000, 0x40);
218 do_it1(0x8000, 0x58);
219 printk("----------------------ebus\n");
220 do_it2(0x9000, 0x00, 0x38);
221 printk("----------------------ecc\n");
222 do_it2(0xa000, 0x00, 0x08);
223 printk("----------------------dmac\n");
224 do_it2(0xb000, 0x00, 0xf8);
225 /* b1xx */
226 printk("----------------------pci\n");
227 /* d */
228 printk("----------------------cfg\n");
229 do_it2(0xe000, 0x00, 0x20);
230 do_it1(0xe000, 0x30);
231 do_it1(0xe000, 0x48);
232 printk("----------------------timers\n");
233 do_it2(0xf000, 0x00, 0xf0);
234 do_it2(0xf100, 0x00, 0xf0);
235 do_it2(0xf200, 0x00, 0xf0);
236 printk("----------------------serial\n");
237 do_it2(0xf300, 0x00, 0x20);
238 do_it2(0xf400, 0x00, 0x20);
239 printk("----------------------parallel\n");
240 do_it2(0xf500, 0x00, 0x0c);
241 printk("----------------------pic\n");
242 do_it2(0xf500, 0x10, 0x24);
243 do_it2(0xf600, 0x00, 0x2c);
244 do_it1(0xf600, 0x40);
245 do_it1(0xf600, 0x60);
246 do_it1(0xf600, 0x80);
247 do_it1(0xf600, 0xa0);
248 printk("----------------------aclink\n");
249 do_it2(0xf700, 0x00, 0xfc);
250 printk("----------------------done\n");
251 }
252 #endif
253
254
pcibios_fixup_irqs(void)255 void __init pcibios_fixup_irqs(void)
256 {
257 unsigned char pin;
258 unsigned char irq;
259 struct pci_dev *dev;
260 unsigned int id;
261
262 #ifdef TX4927_SUPPORT_PCI_66
263 {
264 if (tx4927_pci66_check()) {
265 tx4927_pci66_setup();
266 tx4927_pci_setup(); /* Reinitialize PCIC */
267 }
268 }
269 #endif
270
271 pci_for_each_dev(dev) {
272 DBG("FIXUP:\n");
273 DBG(" devfn=0x%02x (0x%02x:0x%02x)\n",
274 dev->devfn, PCI_SLOT(dev->devfn),
275 PCI_FUNC(dev->devfn));
276
277 pci_read_config_dword(dev, PCI_VENDOR_ID, &id);
278 DBG(" id=0x%08x\n", id);
279
280 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
281 DBG(" line=0x%02x/%d\n", irq, irq);
282
283 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
284 DBG(" pin=%d\n", pin);
285
286 #ifdef DEBUG
287 {
288 unsigned int tmp;
289 pci_read_config_dword(dev, 0x10, &tmp);
290 DBG(" bar0:0x10=0x%08x\n", tmp);
291 pci_read_config_dword(dev, 0x14, &tmp);
292 DBG(" bar1:0x14=0x%08x\n", tmp);
293 pci_read_config_dword(dev, 0x1c, &tmp);
294 DBG(" bar2:0x1c=0x%08x\n", tmp);
295 pci_read_config_dword(dev, 0x20, &tmp);
296 DBG(" bar3:0x20=0x%08x\n", tmp);
297 pci_read_config_dword(dev, 0x24, &tmp);
298 DBG(" bar4:0x24=0x%08x\n", tmp);
299 }
300 #endif
301
302 irq = 0;
303
304 if (id == 0x91301055) { /* ide */
305 irq = 14;
306 }
307
308 if (pin == 0) {
309 DBG(" auto irq (now=%d) -- skipping pin=0\n", irq);
310 } else if (irq) {
311 DBG(" auto irq (now=%d) -- skipping hardcoded irq\n", irq);
312 } else {
313 DBG(" auto irq (was=%d)\n", irq);
314 irq = pci_get_irq(dev, pin);
315 pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
316 irq);
317 dev->irq = irq;
318 DBG(" auto irq (now=%d)\n", irq);
319 }
320
321 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
322 printk(KERN_INFO
323 "PCI: 0x%02x:0x%02x(0x%02x,0x%02x) IRQ=%d\n",
324 dev->bus->number, dev->devfn, PCI_SLOT(dev->devfn),
325 PCI_FUNC(dev->devfn), irq);
326
327 }
328
329 }
330