1 /* r128_drm.h -- Public header for the r128 driver -*- linux-c -*- 2 * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com 3 * 4 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 6 * All rights reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the next 16 * paragraph) shall be included in all copies or substantial portions of the 17 * Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 25 * DEALINGS IN THE SOFTWARE. 26 * 27 * Authors: 28 * Gareth Hughes <gareth@valinux.com> 29 * Kevin E. Martin <martin@valinux.com> 30 */ 31 32 #ifndef __R128_DRM_H__ 33 #define __R128_DRM_H__ 34 35 /* WARNING: If you change any of these defines, make sure to change the 36 * defines in the X server file (r128_sarea.h) 37 */ 38 #ifndef __R128_SAREA_DEFINES__ 39 #define __R128_SAREA_DEFINES__ 40 41 /* What needs to be changed for the current vertex buffer? 42 */ 43 #define R128_UPLOAD_CONTEXT 0x001 44 #define R128_UPLOAD_SETUP 0x002 45 #define R128_UPLOAD_TEX0 0x004 46 #define R128_UPLOAD_TEX1 0x008 47 #define R128_UPLOAD_TEX0IMAGES 0x010 48 #define R128_UPLOAD_TEX1IMAGES 0x020 49 #define R128_UPLOAD_CORE 0x040 50 #define R128_UPLOAD_MASKS 0x080 51 #define R128_UPLOAD_WINDOW 0x100 52 #define R128_UPLOAD_CLIPRECTS 0x200 /* handled client-side */ 53 #define R128_REQUIRE_QUIESCENCE 0x400 54 #define R128_UPLOAD_ALL 0x7ff 55 56 #define R128_FRONT 0x1 57 #define R128_BACK 0x2 58 #define R128_DEPTH 0x4 59 60 /* Primitive types 61 */ 62 #define R128_POINTS 0x1 63 #define R128_LINES 0x2 64 #define R128_LINE_STRIP 0x3 65 #define R128_TRIANGLES 0x4 66 #define R128_TRIANGLE_FAN 0x5 67 #define R128_TRIANGLE_STRIP 0x6 68 69 /* Vertex/indirect buffer size 70 */ 71 #define R128_BUFFER_SIZE 16384 72 73 /* Byte offsets for indirect buffer data 74 */ 75 #define R128_INDEX_PRIM_OFFSET 20 76 #define R128_HOSTDATA_BLIT_OFFSET 32 77 78 /* Keep these small for testing. 79 */ 80 #define R128_NR_SAREA_CLIPRECTS 12 81 82 /* There are 2 heaps (local/AGP). Each region within a heap is a 83 * minimum of 64k, and there are at most 64 of them per heap. 84 */ 85 #define R128_LOCAL_TEX_HEAP 0 86 #define R128_AGP_TEX_HEAP 1 87 #define R128_NR_TEX_HEAPS 2 88 #define R128_NR_TEX_REGIONS 64 89 #define R128_LOG_TEX_GRANULARITY 16 90 91 #define R128_NR_CONTEXT_REGS 12 92 93 #define R128_MAX_TEXTURE_LEVELS 11 94 #define R128_MAX_TEXTURE_UNITS 2 95 96 #endif /* __R128_SAREA_DEFINES__ */ 97 98 typedef struct { 99 /* Context state - can be written in one large chunk */ 100 unsigned int dst_pitch_offset_c; 101 unsigned int dp_gui_master_cntl_c; 102 unsigned int sc_top_left_c; 103 unsigned int sc_bottom_right_c; 104 unsigned int z_offset_c; 105 unsigned int z_pitch_c; 106 unsigned int z_sten_cntl_c; 107 unsigned int tex_cntl_c; 108 unsigned int misc_3d_state_cntl_reg; 109 unsigned int texture_clr_cmp_clr_c; 110 unsigned int texture_clr_cmp_msk_c; 111 unsigned int fog_color_c; 112 113 /* Texture state */ 114 unsigned int tex_size_pitch_c; 115 unsigned int constant_color_c; 116 117 /* Setup state */ 118 unsigned int pm4_vc_fpu_setup; 119 unsigned int setup_cntl; 120 121 /* Mask state */ 122 unsigned int dp_write_mask; 123 unsigned int sten_ref_mask_c; 124 unsigned int plane_3d_mask_c; 125 126 /* Window state */ 127 unsigned int window_xy_offset; 128 129 /* Core state */ 130 unsigned int scale_3d_cntl; 131 } drm_r128_context_regs_t; 132 133 /* Setup registers for each texture unit 134 */ 135 typedef struct { 136 unsigned int tex_cntl; 137 unsigned int tex_combine_cntl; 138 unsigned int tex_size_pitch; 139 unsigned int tex_offset[R128_MAX_TEXTURE_LEVELS]; 140 unsigned int tex_border_color; 141 } drm_r128_texture_regs_t; 142 143 144 typedef struct drm_r128_sarea { 145 /* The channel for communication of state information to the kernel 146 * on firing a vertex buffer. 147 */ 148 drm_r128_context_regs_t context_state; 149 drm_r128_texture_regs_t tex_state[R128_MAX_TEXTURE_UNITS]; 150 unsigned int dirty; 151 unsigned int vertsize; 152 unsigned int vc_format; 153 154 /* The current cliprects, or a subset thereof. 155 */ 156 drm_clip_rect_t boxes[R128_NR_SAREA_CLIPRECTS]; 157 unsigned int nbox; 158 159 /* Counters for client-side throttling of rendering clients. 160 */ 161 unsigned int last_frame; 162 unsigned int last_dispatch; 163 164 drm_tex_region_t tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS+1]; 165 int tex_age[R128_NR_TEX_HEAPS]; 166 int ctx_owner; 167 } drm_r128_sarea_t; 168 169 170 /* WARNING: If you change any of these defines, make sure to change the 171 * defines in the Xserver file (xf86drmR128.h) 172 */ 173 174 /* Rage 128 specific ioctls 175 * The device specific ioctl range is 0x40 to 0x79. 176 */ 177 #define DRM_IOCTL_R128_INIT DRM_IOW( 0x40, drm_r128_init_t) 178 #define DRM_IOCTL_R128_CCE_START DRM_IO( 0x41) 179 #define DRM_IOCTL_R128_CCE_STOP DRM_IOW( 0x42, drm_r128_cce_stop_t) 180 #define DRM_IOCTL_R128_CCE_RESET DRM_IO( 0x43) 181 #define DRM_IOCTL_R128_CCE_IDLE DRM_IO( 0x44) 182 #define DRM_IOCTL_R128_RESET DRM_IO( 0x46) 183 #define DRM_IOCTL_R128_SWAP DRM_IO( 0x47) 184 #define DRM_IOCTL_R128_CLEAR DRM_IOW( 0x48, drm_r128_clear_t) 185 #define DRM_IOCTL_R128_VERTEX DRM_IOW( 0x49, drm_r128_vertex_t) 186 #define DRM_IOCTL_R128_INDICES DRM_IOW( 0x4a, drm_r128_indices_t) 187 #define DRM_IOCTL_R128_BLIT DRM_IOW( 0x4b, drm_r128_blit_t) 188 #define DRM_IOCTL_R128_DEPTH DRM_IOW( 0x4c, drm_r128_depth_t) 189 #define DRM_IOCTL_R128_STIPPLE DRM_IOW( 0x4d, drm_r128_stipple_t) 190 #define DRM_IOCTL_R128_INDIRECT DRM_IOWR(0x4f, drm_r128_indirect_t) 191 #define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( 0x50, drm_r128_fullscreen_t) 192 #define DRM_IOCTL_R128_CLEAR2 DRM_IOW( 0x51, drm_r128_clear2_t) 193 194 typedef struct drm_r128_init { 195 enum { 196 R128_INIT_CCE = 0x01, 197 R128_CLEANUP_CCE = 0x02 198 } func; 199 #if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0) 200 int sarea_priv_offset; 201 #else 202 unsigned long sarea_priv_offset; 203 #endif 204 int is_pci; 205 int cce_mode; 206 int cce_secure; 207 int ring_size; 208 int usec_timeout; 209 210 unsigned int fb_bpp; 211 unsigned int front_offset, front_pitch; 212 unsigned int back_offset, back_pitch; 213 unsigned int depth_bpp; 214 unsigned int depth_offset, depth_pitch; 215 unsigned int span_offset; 216 217 #if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0) 218 unsigned int fb_offset; 219 unsigned int mmio_offset; 220 unsigned int ring_offset; 221 unsigned int ring_rptr_offset; 222 unsigned int buffers_offset; 223 unsigned int agp_textures_offset; 224 #else 225 unsigned long fb_offset; 226 unsigned long mmio_offset; 227 unsigned long ring_offset; 228 unsigned long ring_rptr_offset; 229 unsigned long buffers_offset; 230 unsigned long agp_textures_offset; 231 #endif 232 } drm_r128_init_t; 233 234 typedef struct drm_r128_cce_stop { 235 int flush; 236 int idle; 237 } drm_r128_cce_stop_t; 238 239 typedef struct drm_r128_clear { 240 unsigned int flags; 241 #if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0) 242 int x, y, w, h; 243 #endif 244 unsigned int clear_color; 245 unsigned int clear_depth; 246 #if CONFIG_XFREE86_VERSION >= XFREE86_VERSION(4,1,0,0) 247 unsigned int color_mask; 248 unsigned int depth_mask; 249 #endif 250 } drm_r128_clear_t; 251 252 typedef struct drm_r128_vertex { 253 int prim; 254 int idx; /* Index of vertex buffer */ 255 int count; /* Number of vertices in buffer */ 256 int discard; /* Client finished with buffer? */ 257 } drm_r128_vertex_t; 258 259 typedef struct drm_r128_indices { 260 int prim; 261 int idx; 262 int start; 263 int end; 264 int discard; /* Client finished with buffer? */ 265 } drm_r128_indices_t; 266 267 typedef struct drm_r128_blit { 268 int idx; 269 int pitch; 270 int offset; 271 int format; 272 unsigned short x, y; 273 unsigned short width, height; 274 } drm_r128_blit_t; 275 276 typedef struct drm_r128_depth { 277 enum { 278 R128_WRITE_SPAN = 0x01, 279 R128_WRITE_PIXELS = 0x02, 280 R128_READ_SPAN = 0x03, 281 R128_READ_PIXELS = 0x04 282 } func; 283 int n; 284 int *x; 285 int *y; 286 unsigned int *buffer; 287 unsigned char *mask; 288 } drm_r128_depth_t; 289 290 typedef struct drm_r128_stipple { 291 unsigned int *mask; 292 } drm_r128_stipple_t; 293 294 typedef struct drm_r128_indirect { 295 int idx; 296 int start; 297 int end; 298 int discard; 299 } drm_r128_indirect_t; 300 301 typedef struct drm_r128_fullscreen { 302 enum { 303 R128_INIT_FULLSCREEN = 0x01, 304 R128_CLEANUP_FULLSCREEN = 0x02 305 } func; 306 } drm_r128_fullscreen_t; 307 308 #endif 309