Searched refs:dpll (Results 1 – 2 of 2) sorted by relevance
834 u32 *dpll, *fp0, *fp1; in intelfbhw_mode_to_hw() local857 dpll = &hw->dpll_b; in intelfbhw_mode_to_hw()869 dpll = &hw->dpll_a; in intelfbhw_mode_to_hw()903 *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE); in intelfbhw_mode_to_hw()904 *dpll &= ~(DPLL_RATE_SELECT_MASK | DPLL_REFERENCE_SELECT_MASK); in intelfbhw_mode_to_hw()905 *dpll |= (DPLL_REFERENCE_DEFAULT | DPLL_RATE_SELECT_FP0); in intelfbhw_mode_to_hw()926 *dpll &= ~DPLL_P1_FORCE_DIV2; in intelfbhw_mode_to_hw()927 *dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) | in intelfbhw_mode_to_hw()929 *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT); in intelfbhw_mode_to_hw()1064 const u32 *dpll, *fp0, *fp1, *pipe_conf; in intelfbhw_program_mode() local[all …]
212 cards. Use "mode dpll" for clock source (see below).251 clock dpll # clock source: 252 # dpll = normal half duplex operation