Searched refs:dma_base2 (Results 1 – 4 of 4) sorted by relevance
1012 if (hwif->dma_base2) in ide_release_mmio_dma()1022 if (hwif->dma_base2) in ide_release_iomio_dma()1105 if (hwif->dma_base2) { in ide_mmio_dma()1106 if (!check_mem_region(hwif->dma_base2, ports)) in ide_mmio_dma()1107 request_mem_region(hwif->dma_base2, ports, hwif->name); in ide_mmio_dma()1133 if (hwif->dma_base2) { in ide_iomio_dma()1134 if (!request_region(hwif->dma_base2, ports, hwif->name)) in ide_iomio_dma()
273 unsigned long *ending_dma = (unsigned long *) hwif->dma_base2; in sgiioc4_ide_dma_end()466 hwif->dma_base2 = (unsigned long) pci_alloc_consistent(hwif->pci_dev, IOC4_IDE_CACHELINE_SIZE, in ide_dma_sgiioc4()469 if (!hwif->dma_base2) { in ide_dma_sgiioc4()534 memset((unsigned int *) hwif->dma_base2, 0,IOC4_IDE_CACHELINE_SIZE); in sgiioc4_configure_for_dma()
1041 hwif->dma_base2 = base + (ch ? 0x08 : 0x00); in init_mmio_iops_siimage()1042 hwif->dma_prdtable = hwif->dma_base2 + 4; in init_mmio_iops_siimage()1045 hwif->dma_base2 = base + (ch ? 0x18 : 0x10); in init_mmio_iops_siimage()
986 unsigned long dma_base2; /* extended base addr for dma ports */ member