1 /*
2 drivers/net/tulip/tulip.h
3
4 Copyright 2000,2001 The Linux Kernel Team
5 Written/copyright 1994-2001 by Donald Becker.
6
7 This software may be used and distributed according to the terms
8 of the GNU General Public License, incorporated herein by reference.
9
10 Please refer to Documentation/DocBook/tulip.{pdf,ps,html}
11 for more information on this driver, or visit the project
12 Web page at http://sourceforge.net/projects/tulip/
13
14 */
15
16 #ifndef __NET_TULIP_H__
17 #define __NET_TULIP_H__
18
19 #include <linux/config.h>
20 #include <linux/kernel.h>
21 #include <linux/types.h>
22 #include <linux/spinlock.h>
23 #include <linux/netdevice.h>
24 #include <linux/timer.h>
25 #include <linux/delay.h>
26 #include <asm/io.h>
27 #include <asm/irq.h>
28
29
30
31 /* undefine, or define to various debugging levels (>4 == obscene levels) */
32 #define TULIP_DEBUG 1
33
34 /* undefine USE_IO_OPS for MMIO, define for PIO */
35 #ifdef CONFIG_TULIP_MMIO
36 # undef USE_IO_OPS
37 #else
38 # define USE_IO_OPS 1
39 #endif
40
41
42
43 struct tulip_chip_table {
44 char *chip_name;
45 int io_size;
46 int valid_intrs; /* CSR7 interrupt enable settings */
47 int flags;
48 void (*media_timer) (unsigned long data);
49 };
50
51
52 enum tbl_flag {
53 HAS_MII = 0x0001,
54 HAS_MEDIA_TABLE = 0x0002,
55 CSR12_IN_SROM = 0x0004,
56 ALWAYS_CHECK_MII = 0x0008,
57 HAS_ACPI = 0x0010,
58 MC_HASH_ONLY = 0x0020, /* Hash-only multicast filter. */
59 HAS_PNICNWAY = 0x0080,
60 HAS_NWAY = 0x0040, /* Uses internal NWay xcvr. */
61 HAS_INTR_MITIGATION = 0x0100,
62 IS_ASIX = 0x0200,
63 HAS_8023X = 0x0400,
64 COMET_MAC_ADDR = 0x0800,
65 HAS_PCI_MWI = 0x1000,
66 HAS_PHY_IRQ = 0x2000,
67 };
68
69
70 /* chip types. careful! order is VERY IMPORTANT here, as these
71 * are used throughout the driver as indices into arrays */
72 /* Note 21142 == 21143. */
73 enum chips {
74 DC21040 = 0,
75 DC21041 = 1,
76 DC21140 = 2,
77 DC21142 = 3, DC21143 = 3,
78 LC82C168,
79 MX98713,
80 MX98715,
81 MX98725,
82 AX88140,
83 PNIC2,
84 COMET,
85 COMPEX9881,
86 I21145,
87 DM910X,
88 CONEXANT,
89 };
90
91
92 enum MediaIs {
93 MediaIsFD = 1,
94 MediaAlwaysFD = 2,
95 MediaIsMII = 4,
96 MediaIsFx = 8,
97 MediaIs100 = 16
98 };
99
100
101 /* Offsets to the Command and Status Registers, "CSRs". All accesses
102 must be longword instructions and quadword aligned. */
103 enum tulip_offsets {
104 CSR0 = 0,
105 CSR1 = 0x08,
106 CSR2 = 0x10,
107 CSR3 = 0x18,
108 CSR4 = 0x20,
109 CSR5 = 0x28,
110 CSR6 = 0x30,
111 CSR7 = 0x38,
112 CSR8 = 0x40,
113 CSR9 = 0x48,
114 CSR10 = 0x50,
115 CSR11 = 0x58,
116 CSR12 = 0x60,
117 CSR13 = 0x68,
118 CSR14 = 0x70,
119 CSR15 = 0x78,
120 };
121
122 /* register offset and bits for CFDD PCI config reg */
123 enum pci_cfg_driver_reg {
124 CFDD = 0x40,
125 CFDD_Sleep = (1 << 31),
126 CFDD_Snooze = (1 << 30),
127 };
128
129
130 /* The bits in the CSR5 status registers, mostly interrupt sources. */
131 enum status_bits {
132 TimerInt = 0x800,
133 SytemError = 0x2000,
134 TPLnkFail = 0x1000,
135 TPLnkPass = 0x10,
136 NormalIntr = 0x10000,
137 AbnormalIntr = 0x8000,
138 RxJabber = 0x200,
139 RxDied = 0x100,
140 RxNoBuf = 0x80,
141 RxIntr = 0x40,
142 TxFIFOUnderflow = 0x20,
143 TxJabber = 0x08,
144 TxNoBuf = 0x04,
145 TxDied = 0x02,
146 TxIntr = 0x01,
147 };
148
149 /* bit mask for CSR5 TX/RX process state */
150 #define CSR5_TS 0x00700000
151 #define CSR5_RS 0x000e0000
152
153 enum tulip_mode_bits {
154 TxThreshold = (1 << 22),
155 FullDuplex = (1 << 9),
156 TxOn = 0x2000,
157 AcceptBroadcast = 0x0100,
158 AcceptAllMulticast = 0x0080,
159 AcceptAllPhys = 0x0040,
160 AcceptRunt = 0x0008,
161 RxOn = 0x0002,
162 RxTx = (TxOn | RxOn),
163 };
164
165
166 enum tulip_busconfig_bits {
167 MWI = (1 << 24),
168 MRL = (1 << 23),
169 MRM = (1 << 21),
170 CALShift = 14,
171 BurstLenShift = 8,
172 };
173
174
175 /* The Tulip Rx and Tx buffer descriptors. */
176 struct tulip_rx_desc {
177 s32 status;
178 s32 length;
179 u32 buffer1;
180 u32 buffer2;
181 };
182
183
184 struct tulip_tx_desc {
185 s32 status;
186 s32 length;
187 u32 buffer1;
188 u32 buffer2; /* We use only buffer 1. */
189 };
190
191
192 enum desc_status_bits {
193 DescOwned = 0x80000000,
194 /*
195 * Error summary flag is logical or of 'CRC Error', 'Collision Seen',
196 * 'Frame Too Long', 'Runt' and 'Descriptor Error' flags generated
197 * within tulip chip.
198 */
199 RxDescErrorSummary = 0x8000,
200 RxDescCRCError = 0x0002,
201 RxDescCollisionSeen = 0x0040,
202
203 /*
204 * 'Frame Too Long' flag is set if packet length including CRC exceeds
205 * 1518. However, a full sized VLAN tagged frame is 1522 bytes
206 * including CRC.
207 *
208 * The tulip chip does not block oversized frames, and if this flag is
209 * set on a receive descriptor it does not indicate the frame has been
210 * truncated. The receive descriptor also includes the actual length.
211 * Therefore we can safety ignore this flag and check the length
212 * ourselves.
213 */
214 RxDescFrameTooLong = 0x0080,
215 RxDescRunt = 0x0800,
216 RxDescDescErr = 0x4000,
217 RxWholePkt = 0x0300,
218 /*
219 * Top three bits of 14 bit frame length (status bits 27-29) should
220 * never be set as that would make frame over 2047 bytes. The Receive
221 * Watchdog flag (bit 4) may indicate the length is over 2048 and the
222 * length field is invalid.
223 */
224 RxLengthOver2047 = 0x38000010
225 };
226
227
228 enum t21041_csr13_bits {
229 csr13_eng = (0xEF0<<4), /* for eng. purposes only, hardcode at EF0h */
230 csr13_aui = (1<<3), /* clear to force 10bT, set to force AUI/BNC */
231 csr13_cac = (1<<2), /* CSR13/14/15 autoconfiguration */
232 csr13_srl = (1<<0), /* When reset, resets all SIA functions, machines */
233
234 csr13_mask_auibnc = (csr13_eng | csr13_aui | csr13_srl),
235 csr13_mask_10bt = (csr13_eng | csr13_srl),
236 };
237
238 enum t21143_csr6_bits {
239 csr6_sc = (1<<31),
240 csr6_ra = (1<<30),
241 csr6_ign_dest_msb = (1<<26),
242 csr6_mbo = (1<<25),
243 csr6_scr = (1<<24), /* scramble mode flag: can't be set */
244 csr6_pcs = (1<<23), /* Enables PCS functions (symbol mode requires csr6_ps be set) default is set */
245 csr6_ttm = (1<<22), /* Transmit Threshold Mode, set for 10baseT, 0 for 100BaseTX */
246 csr6_sf = (1<<21), /* Store and forward. If set ignores TR bits */
247 csr6_hbd = (1<<19), /* Heart beat disable. Disables SQE function in 10baseT */
248 csr6_ps = (1<<18), /* Port Select. 0 (defualt) = 10baseT, 1 = 100baseTX: can't be set */
249 csr6_ca = (1<<17), /* Collision Offset Enable. If set uses special algorithm in low collision situations */
250 csr6_trh = (1<<15), /* Transmit Threshold high bit */
251 csr6_trl = (1<<14), /* Transmit Threshold low bit */
252
253 /***************************************************************
254 * This table shows transmit threshold values based on media *
255 * and these two registers (from PNIC1 & 2 docs) Note: this is *
256 * all meaningless if sf is set. *
257 ***************************************************************/
258
259 /***********************************
260 * (trh,trl) * 100BaseTX * 10BaseT *
261 ***********************************
262 * (0,0) * 128 * 72 *
263 * (0,1) * 256 * 96 *
264 * (1,0) * 512 * 128 *
265 * (1,1) * 1024 * 160 *
266 ***********************************/
267
268 csr6_fc = (1<<12), /* Forces a collision in next transmission (for testing in loopback mode) */
269 csr6_om_int_loop = (1<<10), /* internal (FIFO) loopback flag */
270 csr6_om_ext_loop = (1<<11), /* external (PMD) loopback flag */
271 /* set both and you get (PHY) loopback */
272 csr6_fd = (1<<9), /* Full duplex mode, disables hearbeat, no loopback */
273 csr6_pm = (1<<7), /* Pass All Multicast */
274 csr6_pr = (1<<6), /* Promiscuous mode */
275 csr6_sb = (1<<5), /* Start(1)/Stop(0) backoff counter */
276 csr6_if = (1<<4), /* Inverse Filtering, rejects only addresses in address table: can't be set */
277 csr6_pb = (1<<3), /* Pass Bad Frames, (1) causes even bad frames to be passed on */
278 csr6_ho = (1<<2), /* Hash-only filtering mode: can't be set */
279 csr6_hp = (1<<0), /* Hash/Perfect Receive Filtering Mode: can't be set */
280
281 csr6_mask_capture = (csr6_sc | csr6_ca),
282 csr6_mask_defstate = (csr6_mask_capture | csr6_mbo),
283 csr6_mask_hdcap = (csr6_mask_defstate | csr6_hbd | csr6_ps),
284 csr6_mask_hdcaptt = (csr6_mask_hdcap | csr6_trh | csr6_trl),
285 csr6_mask_fullcap = (csr6_mask_hdcaptt | csr6_fd),
286 csr6_mask_fullpromisc = (csr6_pr | csr6_pm),
287 csr6_mask_filters = (csr6_hp | csr6_ho | csr6_if),
288 csr6_mask_100bt = (csr6_scr | csr6_pcs | csr6_hbd),
289 };
290
291
292 /* Keep the ring sizes a power of two for efficiency.
293 Making the Tx ring too large decreases the effectiveness of channel
294 bonding and packet priority.
295 There are no ill effects from too-large receive rings. */
296 #define TX_RING_SIZE 16
297 #define RX_RING_SIZE 32
298
299 #define MEDIA_MASK 31
300
301 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */
302
303 #define TULIP_MIN_CACHE_LINE 8 /* in units of 32-bit words */
304
305 #if defined(__sparc__) || defined(__hppa__)
306 /* The UltraSparc PCI controllers will disconnect at every 64-byte
307 * crossing anyways so it makes no sense to tell Tulip to burst
308 * any more than that.
309 */
310 #define TULIP_MAX_CACHE_LINE 16 /* in units of 32-bit words */
311 #else
312 #define TULIP_MAX_CACHE_LINE 32 /* in units of 32-bit words */
313 #endif
314
315
316 /* Ring-wrap flag in length field, use for last ring entry.
317 0x01000000 means chain on buffer2 address,
318 0x02000000 means use the ring start address in CSR2/3.
319 Note: Some work-alike chips do not function correctly in chained mode.
320 The ASIX chip works only in chained mode.
321 Thus we indicates ring mode, but always write the 'next' field for
322 chained mode as well.
323 */
324 #define DESC_RING_WRAP 0x02000000
325
326
327 #define EEPROM_SIZE 128 /* 2 << EEPROM_ADDRLEN */
328
329
330 #define RUN_AT(x) (jiffies + (x))
331
332 #if defined(__i386__) /* AKA get_unaligned() */
333 #define get_u16(ptr) (*(u16 *)(ptr))
334 #else
335 #define get_u16(ptr) (((u8*)(ptr))[0] + (((u8*)(ptr))[1]<<8))
336 #endif
337
338 struct medialeaf {
339 u8 type;
340 u8 media;
341 unsigned char *leafdata;
342 };
343
344
345 struct mediatable {
346 u16 defaultmedia;
347 u8 leafcount;
348 u8 csr12dir; /* General purpose pin directions. */
349 unsigned has_mii:1;
350 unsigned has_nonmii:1;
351 unsigned has_reset:6;
352 u32 csr15dir;
353 u32 csr15val; /* 21143 NWay setting. */
354 struct medialeaf mleaf[0];
355 };
356
357
358 struct mediainfo {
359 struct mediainfo *next;
360 int info_type;
361 int index;
362 unsigned char *info;
363 };
364
365 struct ring_info {
366 struct sk_buff *skb;
367 dma_addr_t mapping;
368 };
369
370
371 struct tulip_private {
372 const char *product_name;
373 struct net_device *next_module;
374 struct tulip_rx_desc *rx_ring;
375 struct tulip_tx_desc *tx_ring;
376 dma_addr_t rx_ring_dma;
377 dma_addr_t tx_ring_dma;
378 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
379 struct ring_info tx_buffers[TX_RING_SIZE];
380 /* The addresses of receive-in-place skbuffs. */
381 struct ring_info rx_buffers[RX_RING_SIZE];
382 u16 setup_frame[96]; /* Pseudo-Tx frame to init address table. */
383 int chip_id;
384 int revision;
385 int flags;
386 struct net_device_stats stats;
387 struct timer_list timer; /* Media selection timer. */
388 u32 mc_filter[2];
389 spinlock_t lock;
390 spinlock_t mii_lock;
391 unsigned int cur_rx, cur_tx; /* The next free ring entry */
392 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
393
394 #ifdef CONFIG_NET_HW_FLOWCONTROL
395 #define RX_A_NBF_STOP 0xffffff3f /* To disable RX and RX-NOBUF ints. */
396 int fc_bit;
397 int mit_sel;
398 int mit_change; /* Signal for Interrupt Mitigtion */
399 #endif
400 unsigned int full_duplex:1; /* Full-duplex operation requested. */
401 unsigned int full_duplex_lock:1;
402 unsigned int fake_addr:1; /* Multiport board faked address. */
403 unsigned int default_port:4; /* Last dev->if_port value. */
404 unsigned int media2:4; /* Secondary monitored media port. */
405 unsigned int medialock:1; /* Don't sense media type. */
406 unsigned int mediasense:1; /* Media sensing in progress. */
407 unsigned int nway:1, nwayset:1; /* 21143 internal NWay. */
408 unsigned int csr0; /* CSR0 setting. */
409 unsigned int csr6; /* Current CSR6 control settings. */
410 unsigned char eeprom[EEPROM_SIZE]; /* Serial EEPROM contents. */
411 void (*link_change) (struct net_device * dev, int csr5);
412 u16 sym_advertise, mii_advertise; /* NWay capabilities advertised. */
413 u16 lpar; /* 21143 Link partner ability. */
414 u16 advertising[4];
415 signed char phys[4], mii_cnt; /* MII device addresses. */
416 struct mediatable *mtable;
417 int cur_index; /* Current media index. */
418 int saved_if_port;
419 struct pci_dev *pdev;
420 int ttimer;
421 int susp_rx;
422 unsigned long nir;
423 unsigned long base_addr;
424 int csr12_shadow;
425 int pad0; /* Used for 8-byte alignment */
426 };
427
428
429 struct eeprom_fixup {
430 char *name;
431 unsigned char addr0;
432 unsigned char addr1;
433 unsigned char addr2;
434 u16 newtable[32]; /* Max length below. */
435 };
436
437
438 /* 21142.c */
439 extern u16 t21142_csr14[];
440 void t21142_timer(unsigned long data);
441 void t21142_start_nway(struct net_device *dev);
442 void t21142_lnk_change(struct net_device *dev, int csr5);
443
444
445 /* PNIC2.c */
446 void pnic2_lnk_change(struct net_device *dev, int csr5);
447 void pnic2_timer(unsigned long data);
448 void pnic2_start_nway(struct net_device *dev);
449 void pnic2_lnk_change(struct net_device *dev, int csr5);
450
451 /* eeprom.c */
452 void tulip_parse_eeprom(struct net_device *dev);
453 int tulip_read_eeprom(long ioaddr, int location, int addr_len);
454
455 /* interrupt.c */
456 extern unsigned int tulip_max_interrupt_work;
457 extern int tulip_rx_copybreak;
458 void tulip_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
459 int tulip_refill_rx(struct net_device *dev);
460
461 /* media.c */
462 int tulip_mdio_read(struct net_device *dev, int phy_id, int location);
463 void tulip_mdio_write(struct net_device *dev, int phy_id, int location, int value);
464 void tulip_select_media(struct net_device *dev, int startup);
465 int tulip_check_duplex(struct net_device *dev);
466 void tulip_find_mii (struct net_device *dev, int board_idx);
467
468 /* pnic.c */
469 void pnic_do_nway(struct net_device *dev);
470 void pnic_lnk_change(struct net_device *dev, int csr5);
471 void pnic_timer(unsigned long data);
472
473 /* timer.c */
474 void tulip_timer(unsigned long data);
475 void mxic_timer(unsigned long data);
476 void comet_timer(unsigned long data);
477
478 /* tulip_core.c */
479 extern int tulip_debug;
480 extern const char * const medianame[];
481 extern const char tulip_media_cap[];
482 extern struct tulip_chip_table tulip_tbl[];
483 extern u8 t21040_csr13[];
484 extern u16 t21041_csr13[];
485 extern u16 t21041_csr14[];
486 extern u16 t21041_csr15[];
487
488 #ifndef USE_IO_OPS
489 #undef inb
490 #undef inw
491 #undef inl
492 #undef outb
493 #undef outw
494 #undef outl
495 #define inb(addr) readb((void*)(addr))
496 #define inw(addr) readw((void*)(addr))
497 #define inl(addr) readl((void*)(addr))
498 #define outb(val,addr) writeb((val), (void*)(addr))
499 #define outw(val,addr) writew((val), (void*)(addr))
500 #define outl(val,addr) writel((val), (void*)(addr))
501 #endif /* !USE_IO_OPS */
502
503
504
tulip_start_rxtx(struct tulip_private * tp)505 static inline void tulip_start_rxtx(struct tulip_private *tp)
506 {
507 long ioaddr = tp->base_addr;
508 outl(tp->csr6 | RxTx, ioaddr + CSR6);
509 barrier();
510 (void) inl(ioaddr + CSR6); /* mmio sync */
511 }
512
tulip_stop_rxtx(struct tulip_private * tp)513 static inline void tulip_stop_rxtx(struct tulip_private *tp)
514 {
515 long ioaddr = tp->base_addr;
516 u32 csr6 = inl(ioaddr + CSR6);
517
518 if (csr6 & RxTx) {
519 unsigned i=1300/10;
520 outl(csr6 & ~RxTx, ioaddr + CSR6);
521 barrier();
522 /* wait until in-flight frame completes.
523 * Max time @ 10BT: 1500*8b/10Mbps == 1200us (+ 100us margin)
524 * Typically expect this loop to end in < 50us on 100BT.
525 */
526 while (--i && (inl(ioaddr + CSR5) & (CSR5_TS|CSR5_RS)))
527 udelay(10);
528
529 if (!i)
530 printk (KERN_DEBUG "%s: tulip_stop_rxtx() failed\n",
531 tp->pdev->slot_name);
532 }
533 }
534
tulip_restart_rxtx(struct tulip_private * tp)535 static inline void tulip_restart_rxtx(struct tulip_private *tp)
536 {
537 tulip_stop_rxtx(tp);
538 udelay(5);
539 tulip_start_rxtx(tp);
540 }
541
542 #endif /* __NET_TULIP_H__ */
543