1 /*
2 * Code to handle x86 style IRQs plus some generic interrupt stuff.
3 *
4 * Copyright (C) 1992 Linus Torvalds
5 * Copyright (C) 1994, 1995, 1996, 1997, 1998 Ralf Baechle
6 * Copyright (C) 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org)
7 * Copyright (C) 1999-2000 Grant Grundler
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23 #include <linux/bitops.h>
24 #include <asm/bitops.h>
25 #include <linux/config.h>
26 #include <asm/pdc.h>
27 #include <linux/errno.h>
28 #include <linux/init.h>
29 #include <linux/signal.h>
30 #include <linux/types.h>
31 #include <linux/ioport.h>
32 #include <linux/timex.h>
33 #include <linux/slab.h>
34 #include <linux/random.h>
35 #include <linux/sched.h>
36 #include <linux/interrupt.h>
37 #include <linux/kernel_stat.h>
38 #include <linux/irq.h>
39 #include <linux/spinlock.h>
40
41 #include <asm/cache.h>
42
43 #undef DEBUG_IRQ
44 #undef PARISC_IRQ_CR16_COUNTS
45
46 extern void timer_interrupt(int, void *, struct pt_regs *);
47 extern void ipi_interrupt(int, void *, struct pt_regs *);
48
49 #ifdef DEBUG_IRQ
50 #define DBG_IRQ(irq, x) if ((irq) != TIMER_IRQ) printk x
51 #else /* DEBUG_IRQ */
52 #define DBG_IRQ(irq, x) do { } while (0)
53 #endif /* DEBUG_IRQ */
54
55 #define EIEM_MASK(irq) (1UL<<(MAX_CPU_IRQ-IRQ_OFFSET(irq)))
56
57 /* Bits in EIEM correlate with cpu_irq_action[].
58 ** Numbered *Big Endian*! (ie bit 0 is MSB)
59 */
60 static volatile unsigned long cpu_eiem = 0;
61
62 static spinlock_t irq_lock = SPIN_LOCK_UNLOCKED; /* protect IRQ regions */
63
64 #ifdef CONFIG_SMP
cpu_set_eiem(void * info)65 static void cpu_set_eiem(void *info)
66 {
67 set_eiem((unsigned long) info);
68 }
69 #endif
70
disable_cpu_irq(void * unused,int irq)71 static inline void disable_cpu_irq(void *unused, int irq)
72 {
73 unsigned long eirr_bit = EIEM_MASK(irq);
74
75 cpu_eiem &= ~eirr_bit;
76 set_eiem(cpu_eiem);
77 smp_call_function(cpu_set_eiem, (void *) cpu_eiem, 1, 1);
78 }
79
enable_cpu_irq(void * unused,int irq)80 static void enable_cpu_irq(void *unused, int irq)
81 {
82 unsigned long eirr_bit = EIEM_MASK(irq);
83
84 mtctl(eirr_bit, 23); /* clear EIRR bit before unmasking */
85 cpu_eiem |= eirr_bit;
86 smp_call_function(cpu_set_eiem, (void *) cpu_eiem, 1, 1);
87 set_eiem(cpu_eiem);
88 }
89
90 /* mask and disable are the same at the CPU level
91 ** Difference is enable clears pending interrupts
92 */
93 #define mask_cpu_irq disable_cpu_irq
94
unmask_cpu_irq(void * unused,int irq)95 static inline void unmask_cpu_irq(void *unused, int irq)
96 {
97 unsigned long eirr_bit = EIEM_MASK(irq);
98 cpu_eiem |= eirr_bit;
99 /* NOTE: sending an IPI will cause do_cpu_irq_mask() to
100 ** handle *any* unmasked pending interrupts.
101 ** ie We don't need to check for pending interrupts here.
102 */
103 smp_call_function(cpu_set_eiem, (void *) cpu_eiem, 1, 1);
104 set_eiem(cpu_eiem);
105 }
106
107 /*
108 * XXX cpu_irq_actions[] will become 2 dimensional for per CPU EIR support.
109 * correspond changes needed in:
110 * processor_probe() initialize additional action arrays
111 * request_irq() handle CPU IRQ region specially
112 * do_cpu_irq_mask() index into the matching irq_action array.
113 */
114 struct irqaction cpu_irq_actions[IRQ_PER_REGION] = {
115 [IRQ_OFFSET(TIMER_IRQ)] { handler: timer_interrupt, name: "timer", },
116 #ifdef CONFIG_SMP
117 [IRQ_OFFSET(IPI_IRQ)] { handler: ipi_interrupt, name: "IPI", },
118 #endif
119 };
120
121 struct irq_region_ops cpu_irq_ops = {
122 disable_cpu_irq, enable_cpu_irq, unmask_cpu_irq, unmask_cpu_irq
123 };
124
125 struct irq_region cpu0_irq_region = {
126 ops: { disable_cpu_irq, enable_cpu_irq, unmask_cpu_irq, unmask_cpu_irq },
127 data: { dev: &cpu_data[0],
128 name: "PARISC-CPU",
129 irqbase: IRQ_FROM_REGION(CPU_IRQ_REGION), },
130 action: cpu_irq_actions,
131 };
132
133 struct irq_region *irq_region[NR_IRQ_REGS] = {
134 [ 0 ] NULL, /* reserved for EISA, else causes data page fault (aka code 15) */
135 [ CPU_IRQ_REGION ] &cpu0_irq_region,
136 };
137
138
139 /*
140 ** Generic interfaces that device drivers can use:
141 ** mask_irq() block IRQ
142 ** unmask_irq() re-enable IRQ and trigger if IRQ is pending
143 ** disable_irq() block IRQ
144 ** enable_irq() clear pending and re-enable IRQ
145 */
146
mask_irq(int irq)147 void mask_irq(int irq)
148 {
149 struct irq_region *region;
150
151 DBG_IRQ(irq, ("mask_irq(%d) %d+%d eiem 0x%lx\n", irq,
152 IRQ_REGION(irq), IRQ_OFFSET(irq), cpu_eiem));
153 irq = irq_cannonicalize(irq);
154 region = irq_region[IRQ_REGION(irq)];
155 if (region->ops.mask_irq)
156 region->ops.mask_irq(region->data.dev, IRQ_OFFSET(irq));
157 }
158
unmask_irq(int irq)159 void unmask_irq(int irq)
160 {
161 struct irq_region *region;
162
163 DBG_IRQ(irq, ("unmask_irq(%d) %d+%d eiem 0x%lx\n", irq,
164 IRQ_REGION(irq), IRQ_OFFSET(irq), cpu_eiem));
165 irq = irq_cannonicalize(irq);
166 region = irq_region[IRQ_REGION(irq)];
167 if (region->ops.unmask_irq)
168 region->ops.unmask_irq(region->data.dev, IRQ_OFFSET(irq));
169 }
170
disable_irq(int irq)171 void disable_irq(int irq)
172 {
173 struct irq_region *region;
174
175 DBG_IRQ(irq, ("disable_irq(%d) %d+%d eiem 0x%lx\n", irq,
176 IRQ_REGION(irq), IRQ_OFFSET(irq), cpu_eiem));
177 irq = irq_cannonicalize(irq);
178 region = irq_region[IRQ_REGION(irq)];
179 if (region->ops.disable_irq)
180 region->ops.disable_irq(region->data.dev, IRQ_OFFSET(irq));
181 else
182 BUG();
183 }
184
enable_irq(int irq)185 void enable_irq(int irq)
186 {
187 struct irq_region *region;
188
189 DBG_IRQ(irq, ("enable_irq(%d) %d+%d eiem 0x%lx\n", irq,
190 IRQ_REGION(irq), IRQ_OFFSET(irq), cpu_eiem));
191 irq = irq_cannonicalize(irq);
192 region = irq_region[IRQ_REGION(irq)];
193
194 if (region->ops.enable_irq)
195 region->ops.enable_irq(region->data.dev, IRQ_OFFSET(irq));
196 else
197 BUG();
198 }
199
get_irq_list(char * buf)200 int get_irq_list(char *buf)
201 {
202 #ifdef CONFIG_PROC_FS
203 char *p = buf;
204 unsigned int regnr = 0;
205
206 p += sprintf(p, " ");
207 #ifdef CONFIG_SMP
208 for (regnr = 0; regnr < smp_num_cpus; regnr++)
209 #endif
210 p += sprintf(p, " CPU%02d ", regnr);
211
212
213 #ifdef PARISC_IRQ_CR16_COUNTS
214 p += sprintf(p, "[min/avg/max] (CPU cycle counts)");
215 #endif
216 *p++ = '\n';
217
218 /* We don't need *irqsave lock variants since this is
219 ** only allowed to change while in the base context.
220 */
221 spin_lock(&irq_lock);
222 for (regnr = 0; regnr < NR_IRQ_REGS; regnr++) {
223 unsigned int i;
224 struct irq_region *region = irq_region[regnr];
225 #ifdef CONFIG_SMP
226 unsigned int j;
227 #endif
228
229 if (!region || !region->action)
230 continue;
231
232 for (i = 0; i <= MAX_CPU_IRQ; i++) {
233 struct irqaction *action = ®ion->action[i];
234 unsigned int irq_no = IRQ_FROM_REGION(regnr) + i;
235
236 if (!action->handler)
237 continue;
238
239 p += sprintf(p, "%3d: ", irq_no);
240 #ifndef CONFIG_SMP
241 p += sprintf(p, "%10u ", kstat_irqs(irq_no));
242 #else
243 for (j = 0; j < smp_num_cpus; j++)
244 p += sprintf(p, "%10u ",
245 kstat.irqs[j][regnr][i]);
246 #endif
247 p += sprintf(p, " %14s",
248 region->data.name ? region->data.name : "N/A");
249
250 #ifndef PARISC_IRQ_CR16_COUNTS
251 p += sprintf(p, " %s", action->name);
252
253 while ((action = action->next))
254 p += sprintf(p, ", %s", action->name);
255 #else
256 for ( ;action; action = action->next) {
257 unsigned int i, avg, min, max;
258
259 min = max = action->cr16_hist[0];
260
261 for (avg = i = 0; i < PARISC_CR16_HIST_SIZE; i++) {
262 int hist = action->cr16_hist[i];
263
264 if (hist) {
265 avg += hist;
266 } else
267 break;
268
269 if (hist > max) max = hist;
270 if (hist < min) min = hist;
271 }
272
273 avg /= i;
274 p += sprintf(p, " %s[%d/%d/%d]", action->name,
275 min,avg,max);
276 }
277 #endif
278
279 *p++ = '\n';
280 }
281 }
282 spin_unlock(&irq_lock);
283
284 p += sprintf(p, "\n");
285 return p - buf;
286
287 #else /* CONFIG_PROC_FS */
288
289 return 0;
290
291 #endif /* CONFIG_PROC_FS */
292 }
293
294
295
296 /*
297 ** The following form a "set": Virtual IRQ, Transaction Address, Trans Data.
298 ** Respectively, these map to IRQ region+EIRR, Processor HPA, EIRR bit.
299 **
300 ** To use txn_XXX() interfaces, get a Virtual IRQ first.
301 ** Then use that to get the Transaction address and data.
302 */
303
304 int
txn_alloc_irq(void)305 txn_alloc_irq(void)
306 {
307 int irq;
308
309 /* never return irq 0 cause that's the interval timer */
310 for (irq = 1; irq <= MAX_CPU_IRQ; irq++) {
311 if (cpu_irq_actions[irq].handler == NULL) {
312 return (IRQ_FROM_REGION(CPU_IRQ_REGION) + irq);
313 }
314 }
315
316 /* unlikely, but be prepared */
317 return -1;
318 }
319
320 int
txn_claim_irq(int irq)321 txn_claim_irq(int irq)
322 {
323 if (irq_region[IRQ_REGION(irq)]->action[IRQ_OFFSET(irq)].handler ==NULL)
324 return irq;
325
326 /* unlikely, but be prepared */
327 return -1;
328 }
329
330 unsigned long
txn_alloc_addr(int virt_irq)331 txn_alloc_addr(int virt_irq)
332 {
333 static int next_cpu = -1;
334
335 next_cpu++; /* assign to "next" CPU we want this bugger on */
336
337 /* validate entry */
338 while ((next_cpu < NR_CPUS) && !cpu_data[next_cpu].txn_addr)
339 next_cpu++;
340
341 if (next_cpu >= NR_CPUS)
342 next_cpu = 0; /* nothing else, assign monarch */
343
344 return cpu_data[next_cpu].txn_addr;
345 }
346
347
348 /*
349 ** The alloc process needs to accept a parameter to accomodate limitations
350 ** of the HW/SW which use these bits:
351 ** Legacy PA I/O (GSC/NIO): 5 bits (architected EIM register)
352 ** V-class (EPIC): 6 bits
353 ** N/L-class/A500: 8 bits (iosapic)
354 ** PCI 2.2 MSI: 16 bits (I think)
355 ** Existing PCI devices: 32-bits (all Symbios SCSI/ATM/HyperFabric)
356 **
357 ** On the service provider side:
358 ** o PA 1.1 (and PA2.0 narrow mode) 5-bits (width of EIR register)
359 ** o PA 2.0 wide mode 6-bits (per processor)
360 ** o IA64 8-bits (0-256 total)
361 **
362 ** So a Legacy PA I/O device on a PA 2.0 box can't use all
363 ** the bits supported by the processor...and the N/L-class
364 ** I/O subsystem supports more bits than PA2.0 has. The first
365 ** case is the problem.
366 */
367 unsigned int
txn_alloc_data(int virt_irq,unsigned int bits_wide)368 txn_alloc_data(int virt_irq, unsigned int bits_wide)
369 {
370 /* XXX FIXME : bits_wide indicates how wide the transaction
371 ** data is allowed to be...we may need a different virt_irq
372 ** if this one won't work. Another reason to index virtual
373 ** irq's into a table which can manage CPU/IRQ bit seperately.
374 */
375 if (IRQ_OFFSET(virt_irq) > (1 << (bits_wide -1)))
376 {
377 panic("Sorry -- didn't allocate valid IRQ for this device\n");
378 }
379
380 return (IRQ_OFFSET(virt_irq));
381 }
382
do_irq(struct irqaction * action,int irq,struct pt_regs * regs)383 void do_irq(struct irqaction *action, int irq, struct pt_regs * regs)
384 {
385 int cpu = smp_processor_id();
386
387 irq_enter(cpu, irq);
388 ++kstat.irqs[cpu][IRQ_REGION(irq)][IRQ_OFFSET(irq)];
389
390 DBG_IRQ(irq, ("do_irq(%d) %d+%d\n", irq, IRQ_REGION(irq), IRQ_OFFSET(irq)));
391
392 for (; action; action = action->next) {
393 #ifdef PARISC_IRQ_CR16_COUNTS
394 unsigned long cr_start = mfctl(16);
395 #endif
396
397 if (action->handler == NULL) {
398 if (IRQ_REGION(irq) == EISA_IRQ_REGION && irq_region[EISA_IRQ_REGION]) {
399 /* were we called due to autodetecting (E)ISA irqs ? */
400 unsigned int *status;
401 status = &irq_region[EISA_IRQ_REGION]->data.status[IRQ_OFFSET(irq)];
402 if (*status & IRQ_AUTODETECT) {
403 *status &= ~IRQ_WAITING;
404 continue;
405 }
406 }
407 printk(KERN_ERR "IRQ: CPU:%d No handler for IRQ %d !\n", cpu, irq);
408 continue;
409 }
410
411 action->handler(irq, action->dev_id, regs);
412
413 #ifdef PARISC_IRQ_CR16_COUNTS
414 {
415 unsigned long cr_end = mfctl(16);
416 unsigned long tmp = cr_end - cr_start;
417 /* check for roll over */
418 cr_start = (cr_end < cr_start) ? -(tmp) : (tmp);
419 }
420 action->cr16_hist[action->cr16_idx++] = (int) cr_start;
421 action->cr16_idx &= PARISC_CR16_HIST_SIZE - 1;
422 #endif
423 }
424
425 irq_exit(cpu, irq);
426 }
427
428
429 /* ONLY called from entry.S:intr_extint() */
do_cpu_irq_mask(struct pt_regs * regs)430 void do_cpu_irq_mask(struct pt_regs *regs)
431 {
432 unsigned long eirr_val;
433 unsigned int i=3; /* limit time in interrupt context */
434
435 /*
436 * PSW_I or EIEM bits cannot be enabled until after the
437 * interrupts are processed.
438 * timer_interrupt() assumes it won't get interrupted when it
439 * holds the xtime_lock...an unmasked interrupt source could
440 * interrupt and deadlock by trying to grab xtime_lock too.
441 * Keeping PSW_I and EIEM disabled avoids this.
442 */
443 set_eiem(0UL); /* disable all extr interrupt for now */
444
445 /* 1) only process IRQs that are enabled/unmasked (cpu_eiem)
446 * 2) We loop here on EIRR contents in order to avoid
447 * nested interrupts or having to take another interupt
448 * when we could have just handled it right away.
449 * 3) Limit the number of times we loop to make sure other
450 * processing can occur.
451 */
452 while ((eirr_val = (mfctl(23) & cpu_eiem)) && --i) {
453 unsigned long bit = (1UL<<MAX_CPU_IRQ);
454 unsigned int irq;
455
456 mtctl(eirr_val, 23); /* reset bits we are going to process */
457
458 #ifdef DEBUG_IRQ
459 if (eirr_val != (1UL << MAX_CPU_IRQ))
460 printk(KERN_DEBUG "do_cpu_irq_mask %x\n", eirr_val);
461 #endif
462
463 for (irq = 0; eirr_val && bit; bit>>=1, irq++)
464 {
465 if (!(bit&eirr_val&cpu_eiem))
466 continue;
467
468 /* clear bit in mask - can exit loop sooner */
469 eirr_val &= ~bit;
470
471 do_irq(&cpu_irq_actions[irq], TIMER_IRQ+irq, regs);
472 }
473 }
474 set_eiem(cpu_eiem);
475 }
476
477
478 /* Called from second level IRQ regions: eg dino or iosapic. */
do_irq_mask(unsigned long mask,struct irq_region * region,struct pt_regs * regs)479 void do_irq_mask(unsigned long mask, struct irq_region *region, struct pt_regs *regs)
480 {
481 unsigned long bit;
482 unsigned int irq;
483
484 #ifdef DEBUG_IRQ
485 if (mask != (1L<<MAX_CPU_IRQ))
486 printk(KERN_DEBUG "do_irq_mask %08lx %p %p\n", mask, region, regs);
487 #endif
488
489 for (bit = (1L<<MAX_CPU_IRQ), irq = 0; mask && bit; bit>>=1, irq++) {
490 unsigned int irq_num;
491 if (!(bit&mask))
492 continue;
493
494 mask &= ~bit; /* clear bit in mask - can exit loop sooner */
495 irq_num = region->data.irqbase + irq;
496
497 mask_irq(irq_num);
498 do_irq(®ion->action[irq], irq_num, regs);
499 unmask_irq(irq_num);
500 }
501 }
502
503
find_free_region(void)504 static inline int find_free_region(void)
505 {
506 int irqreg;
507
508 for (irqreg=1; irqreg <= (NR_IRQ_REGS); irqreg++) {
509 if (irq_region[irqreg] == NULL)
510 return irqreg;
511 }
512
513 return 0;
514 }
515
516
517 /*****
518 * alloc_irq_region - allocate/init a new IRQ region
519 * @count: number of IRQs in this region.
520 * @ops: function table with request/release/mask/unmask/etc.. entries.
521 * @name: name of region owner for /proc/interrupts output.
522 * @dev: private data to associate with the new IRQ region.
523 *
524 * Every IRQ must become a MMIO write to the CPU's EIRR in
525 * order to get CPU service. The IRQ region represents the
526 * number of unique events the region handler can (or must)
527 * identify. For PARISC CPU, that's the width of the EIR Register.
528 * IRQ regions virtualize IRQs (eg EISA or PCI host bus controllers)
529 * for line based devices.
530 */
alloc_irq_region(int count,struct irq_region_ops * ops,const char * name,void * dev)531 struct irq_region *alloc_irq_region( int count, struct irq_region_ops *ops,
532 const char *name, void *dev)
533 {
534 struct irq_region *region;
535 int index;
536
537 index = find_free_region();
538 if (index == 0) {
539 printk(KERN_ERR "Maximum number of irq regions exceeded. Increase NR_IRQ_REGS!\n");
540 return NULL;
541 }
542
543 if ((IRQ_REGION(count-1)))
544 return NULL;
545
546 if (count < IRQ_PER_REGION) {
547 DBG_IRQ(0, ("alloc_irq_region() using minimum of %d irq lines for %s (%d)\n",
548 IRQ_PER_REGION, name, count));
549 count = IRQ_PER_REGION;
550 }
551
552 /* if either mask *or* unmask is set, both have to be set. */
553 if((ops->mask_irq || ops->unmask_irq) &&
554 !(ops->mask_irq && ops->unmask_irq))
555 return NULL;
556
557 /* ditto for enable/disable */
558 if( (ops->disable_irq || ops->enable_irq) &&
559 !(ops->disable_irq && ops->enable_irq) )
560 return NULL;
561
562 region = kmalloc(sizeof(*region), GFP_ATOMIC);
563 if (!region)
564 return NULL;
565 memset(region, 0, sizeof(*region));
566
567 region->action = kmalloc(count * sizeof(*region->action), GFP_ATOMIC);
568 if (!region->action) {
569 kfree(region);
570 return NULL;
571 }
572 memset(region->action, 0, count * sizeof(*region->action));
573
574 region->ops = *ops;
575 region->data.irqbase = IRQ_FROM_REGION(index);
576 region->data.name = name;
577 region->data.dev = dev;
578
579 irq_region[index] = region;
580
581 return irq_region[index];
582 }
583
584 /* FIXME: SMP, flags, bottom halves, rest */
585
request_irq(unsigned int irq,void (* handler)(int,void *,struct pt_regs *),unsigned long irqflags,const char * devname,void * dev_id)586 int request_irq(unsigned int irq,
587 void (*handler)(int, void *, struct pt_regs *),
588 unsigned long irqflags,
589 const char * devname,
590 void *dev_id)
591 {
592 struct irqaction * action;
593
594 #if 0
595 printk(KERN_INFO "request_irq(%d, %p, 0x%lx, %s, %p)\n",irq, handler, irqflags, devname, dev_id);
596 #endif
597
598 irq = irq_cannonicalize(irq);
599 /* request_irq()/free_irq() may not be called from interrupt context. */
600 if (in_interrupt())
601 BUG();
602
603 if (!handler) {
604 printk(KERN_ERR "request_irq(%d,...): Augh! No handler for irq!\n",
605 irq);
606 return -EINVAL;
607 }
608
609 if (irq_region[IRQ_REGION(irq)] == NULL) {
610 /*
611 ** Bug catcher for drivers which use "char" or u8 for
612 ** the IRQ number. They lose the region number which
613 ** is in pcidev->irq (an int).
614 */
615 printk(KERN_ERR "%p (%s?) called request_irq with an invalid irq %d\n",
616 __builtin_return_address(0), devname, irq);
617 return -EINVAL;
618 }
619
620 spin_lock(&irq_lock);
621 action = &(irq_region[IRQ_REGION(irq)]->action[IRQ_OFFSET(irq)]);
622
623 /* First one is preallocated. */
624 if (action->handler) {
625 /* But it's in use...find the tail and allocate a new one */
626 while (action->next)
627 action = action->next;
628
629 action->next = kmalloc(sizeof(*action), GFP_ATOMIC);
630 memset(action->next, 0, sizeof(*action));
631
632 action = action->next;
633 }
634
635 if (!action) {
636 spin_unlock(&irq_lock);
637 printk(KERN_ERR "request_irq(): Augh! No action!\n") ;
638 return -ENOMEM;
639 }
640
641 action->handler = handler;
642 action->flags = irqflags;
643 action->mask = 0;
644 action->name = devname;
645 action->next = NULL;
646 action->dev_id = dev_id;
647 spin_unlock(&irq_lock);
648
649 enable_irq(irq);
650 return 0;
651 }
652
free_irq(unsigned int irq,void * dev_id)653 void free_irq(unsigned int irq, void *dev_id)
654 {
655 struct irqaction *action, **p;
656
657 /* See comments in request_irq() about interrupt context */
658 irq = irq_cannonicalize(irq);
659
660 if (in_interrupt()) BUG();
661
662 spin_lock(&irq_lock);
663 action = &irq_region[IRQ_REGION(irq)]->action[IRQ_OFFSET(irq)];
664
665 if (action->dev_id == dev_id) {
666 if (action->next == NULL) {
667 action->handler = NULL;
668 } else {
669 memcpy(action, action->next, sizeof(*action));
670 }
671
672 spin_unlock(&irq_lock);
673 return;
674 }
675
676 p = &action->next;
677 action = action->next;
678
679 for (; (action = *p) != NULL; p = &action->next) {
680 if (action->dev_id != dev_id)
681 continue;
682
683 /* Found it - now free it */
684 *p = action->next;
685 kfree(action);
686
687 spin_unlock(&irq_lock);
688 return;
689 }
690
691 spin_unlock(&irq_lock);
692 printk(KERN_ERR "Trying to free free IRQ%d\n",irq);
693 }
694
695
696 /*
697 * IRQ autodetection code..
698 *
699 * This depends on the fact that any interrupt that
700 * comes in on to an unassigned handler will get stuck
701 * with "IRQ_WAITING" cleared and the interrupt
702 * disabled.
703 */
704
705 static DECLARE_MUTEX(probe_sem);
706
707 /**
708 * probe_irq_on - begin an interrupt autodetect
709 *
710 * Commence probing for an interrupt. The interrupts are scanned
711 * and a mask of potential interrupt lines is returned.
712 *
713 */
714
715 /* TODO: spin_lock_irq(desc->lock -> irq_lock) */
716
probe_irq_on(void)717 unsigned long probe_irq_on(void)
718 {
719 unsigned int i;
720 unsigned long val;
721 unsigned long delay;
722 struct irq_region *region;
723
724 /* support for irq autoprobing is limited to EISA (irq region 0) */
725 region = irq_region[EISA_IRQ_REGION];
726 if (!EISA_bus || !region)
727 return 0;
728
729 down(&probe_sem);
730
731 /*
732 * enable any unassigned irqs
733 * (we must startup again here because if a longstanding irq
734 * happened in the previous stage, it may have masked itself)
735 */
736 for (i = EISA_MAX_IRQS-1; i > 0; i--) {
737 struct irqaction *action;
738
739 spin_lock_irq(&irq_lock);
740 action = region->action + i;
741 if (!action->handler) {
742 region->data.status[i] |= IRQ_AUTODETECT | IRQ_WAITING;
743 region->ops.enable_irq(region->data.dev,i);
744 }
745 spin_unlock_irq(&irq_lock);
746 }
747
748 /*
749 * Wait for spurious interrupts to trigger
750 */
751 for (delay = jiffies + HZ/10; time_after(delay, jiffies); )
752 /* about 100ms delay */ synchronize_irq();
753
754 /*
755 * Now filter out any obviously spurious interrupts
756 */
757 val = 0;
758 for (i = 0; i < EISA_MAX_IRQS; i++) {
759 unsigned int status;
760
761 spin_lock_irq(&irq_lock);
762 status = region->data.status[i];
763
764 if (status & IRQ_AUTODETECT) {
765 /* It triggered already - consider it spurious. */
766 if (!(status & IRQ_WAITING)) {
767 region->data.status[i] = status & ~IRQ_AUTODETECT;
768 region->ops.disable_irq(region->data.dev,i);
769 } else
770 if (i < BITS_PER_LONG)
771 val |= (1 << i);
772 }
773 spin_unlock_irq(&irq_lock);
774 }
775
776 return val;
777 }
778
779 /*
780 * Return the one interrupt that triggered (this can
781 * handle any interrupt source).
782 */
783
784 /**
785 * probe_irq_off - end an interrupt autodetect
786 * @val: mask of potential interrupts (unused)
787 *
788 * Scans the unused interrupt lines and returns the line which
789 * appears to have triggered the interrupt. If no interrupt was
790 * found then zero is returned. If more than one interrupt is
791 * found then minus the first candidate is returned to indicate
792 * their is doubt.
793 *
794 * The interrupt probe logic state is returned to its previous
795 * value.
796 *
797 * BUGS: When used in a module (which arguably shouldnt happen)
798 * nothing prevents two IRQ probe callers from overlapping. The
799 * results of this are non-optimal.
800 */
801
probe_irq_off(unsigned long val)802 int probe_irq_off(unsigned long val)
803 {
804 struct irq_region *region;
805 int i, irq_found, nr_irqs;
806
807 /* support for irq autoprobing is limited to EISA (irq region 0) */
808 region = irq_region[EISA_IRQ_REGION];
809 if (!EISA_bus || !region)
810 return 0;
811
812 nr_irqs = 0;
813 irq_found = 0;
814 for (i = 0; i < EISA_MAX_IRQS; i++) {
815 unsigned int status;
816
817 spin_lock_irq(&irq_lock);
818 status = region->data.status[i];
819
820 if (status & IRQ_AUTODETECT) {
821 if (!(status & IRQ_WAITING)) {
822 if (!nr_irqs)
823 irq_found = i;
824 nr_irqs++;
825 }
826 region->ops.disable_irq(region->data.dev,i);
827 region->data.status[i] = status & ~IRQ_AUTODETECT;
828 }
829 spin_unlock_irq(&irq_lock);
830 }
831 up(&probe_sem);
832
833 if (nr_irqs > 1)
834 irq_found = -irq_found;
835 return irq_found;
836 }
837
838
init_IRQ(void)839 void __init init_IRQ(void)
840 {
841 local_irq_disable(); /* PARANOID - should already be disabled */
842 mtctl(-1L, 23); /* EIRR : clear all pending external intr */
843 #ifdef CONFIG_SMP
844 if (!cpu_eiem)
845 cpu_eiem = EIEM_MASK(IPI_IRQ) | EIEM_MASK(TIMER_IRQ);
846 #else
847 cpu_eiem = EIEM_MASK(TIMER_IRQ);
848 #endif
849 set_eiem(cpu_eiem); /* EIEM : enable all external intr */
850
851 }
852
853 #ifdef CONFIG_PROC_FS
854 /* called from kernel/sysctl.c:sysctl_init() */
init_irq_proc(void)855 void __init init_irq_proc(void)
856 {
857 }
858 #endif
859