Searched refs:cond_reg (Results 1 – 12 of 12) sorted by relevance
143 while((dregs->cond_reg & DMA_PEND_READ) && (--count > 0)) in dma_do_drain()147 printk("%s:%d timeout CSR %08lx\n", __FILE__, __LINE__, dregs->cond_reg); in dma_do_drain()150 dregs->cond_reg |= DMA_FIFO_STDRAIN; in dma_do_drain()154 while((dregs->cond_reg & DMA_FIFO_ISDRAIN) && (--count > 0)) in dma_do_drain()158 printk("%s:%d timeout CSR %08lx\n", __FILE__, __LINE__, dregs->cond_reg); in dma_do_drain()169 while((dregs->cond_reg & DMA_PEND_READ) && (--count > 0)) in dma_barrier()173 printk("%s:%d timeout CSR %08lx\n", __FILE__, __LINE__, dregs->cond_reg); in dma_barrier()176 dregs->cond_reg &= ~(DMA_ENABLE); in dma_barrier()203 if(dregs->cond_reg & DMA_FIFO_ISDRAIN) { in dma_drain()204 dregs->cond_reg |= DMA_FIFO_STDRAIN; in dma_drain()[all …]
20 volatile unsigned char cond_reg; /* DMA cond (ro) [0x000] */ member21 #define ctrl_reg cond_reg /* DMA control (wo) [0x000] */
20 volatile unsigned char cond_reg; /* DMA status (ro) [0x0000] */ member21 #define ctrl_reg cond_reg /* DMA control (wo) [0x0000] */
28 volatile unsigned char cond_reg; /* DMA cond (ro) [0x402] */ member29 #define ctrl_reg cond_reg /* DMA control (wo) [0x402] */
21 #define DMA_PORTS_P (dregs->cond_reg & DMA_INT_ENAB)
187 (esp->dregs))->cond_reg)); in dma_dump_state()270 ((((struct cyber_dma_registers *)(esp->dregs))->cond_reg) & in dma_irq_p()
225 (esp->dregs))->cond_reg)); in dma_dump_state()314 dma_status = dregs->cond_reg; in dma_irq_p()
177 (esp->dregs))->cond_reg)); in dma_dump_state()
606 (esp->dregs))->cond_reg)); in dma_dump_state()
170 #define DMA_ERROR_P(regs) ((((regs)->cond_reg) & DMA_HNDL_ERROR))171 #define DMA_IRQ_P(regs) ((((regs)->cond_reg) & (DMA_HNDL_INTR | DMA_HNDL_ERROR)))172 #define DMA_WRITE_P(regs) ((((regs)->cond_reg) & DMA_ST_WRITE))173 #define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE)))174 #define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))175 #define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB)))176 #define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV))179 ((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB))))181 ((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE)))))206 while((regs->cond_reg&bit) && (ctr>0)) {[all …]
92 __volatile__ unsigned long cond_reg; /* DMA condition register */ member199 #define DMA_ERROR_P(regs) ((((regs)->cond_reg) & DMA_HNDL_ERROR))200 #define DMA_IRQ_P(regs) ((((regs)->cond_reg) & (DMA_HNDL_INTR | DMA_HNDL_ERROR)))201 #define DMA_WRITE_P(regs) ((((regs)->cond_reg) & DMA_ST_WRITE))202 #define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE)))203 #define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))204 #define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB)))205 #define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV))208 ((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB))))210 ((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE)))))[all …]