Searched refs:cmd_sts (Results 1 – 4 of 4) sorted by relevance
189 pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT; in mv64340_eth_rx_task()388 if (pkt_info.cmd_sts & BIT0) { in mv64340_eth_free_tx_queue()484 ((pkt_info.cmd_sts487 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {490 (pkt_info.cmd_sts & (ETH_RX_FIRST_DESC |499 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) {516 if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) {518 skb->csum = htons((pkt_info.cmd_sts1127 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT |1152 pkt_info.cmd_sts = ETH_TX_FIRST_DESC | [all …]
165 u32 cmd_sts; /* Command and Status */ member171 u16 cmd_sts; /* Command, Status and Buffer count */ member181 u32 cmd_sts; /* Command and Status info */ member188 u16 cmd_sts; /* Command, Status and Buffer count */ member197 unsigned int cmd_sts; member
496 u32 cmd_sts; /* Descriptor command status */ member504 u32 cmd_sts; /* Command/status field */ member511 u32 cmd_sts; /* Descriptor command status */ member519 u32 cmd_sts; /* Command/status field */ member534 unsigned int cmd_sts; /* Descriptor command status */ member
699 rx_desc->cmd_sts = TITAN_GE_RX_BUFFER_OWNED;1193 tx_curr->cmd_sts = 0x1 | (1 << 15) | (1 << 5);1526 if (rx_desc->cmd_sts & TITAN_GE_RX_BUFFER_OWNED) 1530 packet->len = (rx_desc->cmd_sts & 0x7fff);1616 if ((packet.cmd_sts & TITAN_GE_RX_PERR) ||1617 (packet.cmd_sts & TITAN_GE_RX_OVERFLOW_ERROR) ||1618 (packet.cmd_sts & TITAN_GE_RX_TRUNC) ||1619 (packet.cmd_sts & TITAN_GE_RX_CRC_ERROR)) {2079 rx_desc[index].cmd_sts = 0;2119 tx_desc[index].cmd_sts = 0x0000;