1 #ifndef __TRID4DWAVE_H
2 #define __TRID4DWAVE_H
3
4 /*
5 * audio@tridentmicro.com
6 * Fri Feb 19 15:55:28 MST 1999
7 * Definitions for Trident 4DWave DX/NX chips
8 *
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 *
24 */
25
26 /* PCI vendor and device ID */
27 #ifndef PCI_VENDOR_ID_TRIDENT
28 #define PCI_VENDOR_ID_TRIDENT 0x1023
29 #endif
30
31 #ifndef PCI_VENDOR_ID_SI
32 #define PCI_VENDOR_ID_SI 0x1039
33 #endif
34
35 #ifndef PCI_VENDOR_ID_ALI
36 #define PCI_VENDOR_ID_ALI 0x10b9
37 #endif
38
39 #ifndef PCI_DEVICE_ID_TRIDENT_4DWAVE_DX
40 #define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX 0x2000
41 #endif
42
43 #ifndef PCI_DEVICE_ID_TRIDENT_4DWAVE_NX
44 #define PCI_DEVICE_ID_TRIDENT_4DWAVE_NX 0x2001
45 #endif
46
47 #ifndef PCI_DEVICE_ID_SI_7018
48 #define PCI_DEVICE_ID_SI_7018 0x7018
49 #endif
50
51 #ifndef PCI_DEVICE_ID_ALI_5451
52 #define PCI_DEVICE_ID_ALI_5451 0x5451
53 #endif
54
55 #ifndef PCI_DEVICE_ID_ALI_1533
56 #define PCI_DEVICE_ID_ALI_1533 0x1533
57 #endif
58
59 #ifndef FALSE
60 #define FALSE 0
61 #define TRUE 1
62 #endif
63
64 #define CHANNEL_REGS 5
65 #define CHANNEL_START 0xe0 // The first bytes of the contiguous register space.
66
67 #define BANK_A 0
68 #define BANK_B 1
69 #define NR_BANKS 2
70
71 #define TRIDENT_FMT_STEREO 0x01
72 #define TRIDENT_FMT_16BIT 0x02
73 #define TRIDENT_FMT_MASK 0x03
74
75 #define DAC_RUNNING 0x01
76 #define ADC_RUNNING 0x02
77
78 /* Register Addresses */
79
80 /* operational registers common to DX, NX, 7018 */
81 enum trident_op_registers {
82 T4D_REC_CH = 0x70,
83 T4D_START_A = 0x80, T4D_STOP_A = 0x84,
84 T4D_DLY_A = 0x88, T4D_SIGN_CSO_A = 0x8c,
85 T4D_CSPF_A = 0x90, T4D_CEBC_A = 0x94,
86 T4D_AINT_A = 0x98, T4D_EINT_A = 0x9c,
87 T4D_LFO_GC_CIR = 0xa0, T4D_AINTEN_A = 0xa4,
88 T4D_MUSICVOL_WAVEVOL = 0xa8, T4D_SBDELTA_DELTA_R = 0xac,
89 T4D_MISCINT = 0xb0, T4D_START_B = 0xb4,
90 T4D_STOP_B = 0xb8, T4D_CSPF_B = 0xbc,
91 T4D_SBBL_SBCL = 0xc0, T4D_SBCTRL_SBE2R_SBDD = 0xc4,
92 T4D_STIMER = 0xc8, T4D_LFO_B_I2S_DELTA = 0xcc,
93 T4D_AINT_B = 0xd8, T4D_AINTEN_B = 0xdc,
94 ALI_MPUR2 = 0x22, ALI_GPIO = 0x7c,
95 ALI_EBUF1 = 0xf4,
96 ALI_EBUF2 = 0xf8
97 };
98
99 enum ali_op_registers {
100 ALI_SCTRL = 0x48,
101 ALI_GLOBAL_CONTROL = 0xd4,
102 ALI_STIMER = 0xc8,
103 ALI_SPDIF_CS = 0x70,
104 ALI_SPDIF_CTRL = 0x74
105 };
106
107 enum ali_registers_number {
108 ALI_GLOBAL_REGS = 56,
109 ALI_CHANNEL_REGS = 8,
110 ALI_MIXER_REGS = 20
111 };
112
113 enum ali_sctrl_control_bit {
114 ALI_SPDIF_OUT_ENABLE = 0x20
115 };
116
117 enum ali_global_control_bit {
118 ALI_SPDIF_OUT_SEL_PCM = 0x00000400,
119 ALI_SPDIF_IN_SUPPORT = 0x00000800,
120 ALI_SPDIF_OUT_CH_ENABLE = 0x00008000,
121 ALI_SPDIF_IN_CH_ENABLE = 0x00080000,
122 ALI_PCM_IN_DISABLE = 0x7fffffff,
123 ALI_PCM_IN_ENABLE = 0x80000000,
124 ALI_SPDIF_IN_CH_DISABLE = 0xfff7ffff,
125 ALI_SPDIF_OUT_CH_DISABLE = 0xffff7fff,
126 ALI_SPDIF_OUT_SEL_SPDIF = 0xfffffbff
127
128 };
129
130 enum ali_spdif_control_bit {
131 ALI_SPDIF_IN_FUNC_ENABLE = 0x02,
132 ALI_SPDIF_IN_CH_STATUS = 0x40,
133 ALI_SPDIF_OUT_CH_STATUS = 0xbf
134
135 };
136
137 enum ali_control_all {
138 ALI_DISABLE_ALL_IRQ = 0,
139 ALI_CHANNELS = 32,
140 ALI_STOP_ALL_CHANNELS = 0xffffffff,
141 ALI_MULTI_CHANNELS_START_STOP = 0x07800000
142 };
143
144 enum ali_EMOD_control_bit {
145 ALI_EMOD_DEC = 0x00000000,
146 ALI_EMOD_INC = 0x10000000,
147 ALI_EMOD_Delay = 0x20000000,
148 ALI_EMOD_Still = 0x30000000
149 };
150
151 enum ali_pcm_in_channel_num {
152 ALI_NORMAL_CHANNEL = 0,
153 ALI_SPDIF_OUT_CHANNEL = 15,
154 ALI_SPDIF_IN_CHANNEL = 19,
155 ALI_LEF_CHANNEL = 23,
156 ALI_CENTER_CHANNEL = 24,
157 ALI_SURR_RIGHT_CHANNEL = 25,
158 ALI_SURR_LEFT_CHANNEL = 26,
159 ALI_PCM_IN_CHANNEL = 31
160 };
161
162 enum ali_pcm_out_channel_num {
163 ALI_PCM_OUT_CHANNEL_FIRST = 0,
164 ALI_PCM_OUT_CHANNEL_LAST = 31
165 };
166
167 enum ali_ac97_power_control_bit {
168 ALI_EAPD_POWER_DOWN = 0x8000
169 };
170
171 enum ali_update_ptr_flags {
172 ALI_ADDRESS_INT_UPDATE = 0x01
173 };
174
175 enum ali_revision {
176 ALI_5451_V02 = 0x02
177 };
178
179 enum ali_spdif_out_control {
180 ALI_PCM_TO_SPDIF_OUT = 0,
181 ALI_SPDIF_OUT_TO_SPDIF_OUT = 1,
182 ALI_SPDIF_OUT_PCM = 0,
183 ALI_SPDIF_OUT_NON_PCM = 2
184 };
185
186 /* S/PDIF Operational Registers for 4D-NX */
187 enum nx_spdif_registers {
188 NX_SPCTRL_SPCSO = 0x24, NX_SPLBA = 0x28,
189 NX_SPESO = 0x2c, NX_SPCSTATUS = 0x64
190 };
191
192 /* OP registers to access each hardware channel */
193 enum channel_registers {
194 CH_DX_CSO_ALPHA_FMS = 0xe0, CH_DX_ESO_DELTA = 0xe8,
195 CH_DX_FMC_RVOL_CVOL = 0xec,
196 CH_NX_DELTA_CSO = 0xe0, CH_NX_DELTA_ESO = 0xe8,
197 CH_NX_ALPHA_FMS_FMC_RVOL_CVOL = 0xec,
198 CH_LBA = 0xe4,
199 CH_GVSEL_PAN_VOL_CTRL_EC = 0xf0
200 };
201
202 /* registers to read/write/control AC97 codec */
203 enum dx_ac97_registers {
204 DX_ACR0_AC97_W = 0x40, DX_ACR1_AC97_R = 0x44,
205 DX_ACR2_AC97_COM_STAT = 0x48
206 };
207
208 enum nx_ac97_registers {
209 NX_ACR0_AC97_COM_STAT = 0x40, NX_ACR1_AC97_W = 0x44,
210 NX_ACR2_AC97_R_PRIMARY = 0x48, NX_ACR3_AC97_R_SECONDARY = 0x4c
211 };
212
213 enum si_ac97_registers {
214 SI_AC97_WRITE = 0x40, SI_AC97_READ = 0x44,
215 SI_SERIAL_INTF_CTRL = 0x48, SI_AC97_GPIO = 0x4c
216 };
217
218 enum ali_ac97_registers {
219 ALI_AC97_WRITE = 0x40, ALI_AC97_READ = 0x44
220 };
221
222 /* Bit mask for operational registers */
223 #define AC97_REG_ADDR 0x000000ff
224
225 enum ali_ac97_bits {
226 ALI_AC97_BUSY_WRITE = 0x8000, ALI_AC97_BUSY_READ = 0x8000,
227 ALI_AC97_WRITE_ACTION = 0x8000, ALI_AC97_READ_ACTION = 0x8000,
228 ALI_AC97_AUDIO_BUSY = 0x4000, ALI_AC97_SECONDARY = 0x0080,
229 ALI_AC97_READ_MIXER_REGISTER = 0xfeff,
230 ALI_AC97_WRITE_MIXER_REGISTER = 0x0100
231 };
232
233 enum sis7018_ac97_bits {
234 SI_AC97_BUSY_WRITE = 0x8000, SI_AC97_BUSY_READ = 0x8000,
235 SI_AC97_AUDIO_BUSY = 0x4000, SI_AC97_MODEM_BUSY = 0x2000,
236 SI_AC97_SECONDARY = 0x0080
237 };
238
239 enum trident_dx_ac97_bits {
240 DX_AC97_BUSY_WRITE = 0x8000, DX_AC97_BUSY_READ = 0x8000,
241 DX_AC97_READY = 0x0010, DX_AC97_RECORD = 0x0008,
242 DX_AC97_PLAYBACK = 0x0002
243 };
244
245 enum trident_nx_ac97_bits {
246 /* ACR1-3 */
247 NX_AC97_BUSY_WRITE = 0x0800, NX_AC97_BUSY_READ = 0x0800,
248 NX_AC97_BUSY_DATA = 0x0400, NX_AC97_WRITE_SECONDARY = 0x0100,
249 /* ACR0 */
250 NX_AC97_SECONDARY_READY = 0x0040, NX_AC97_SECONDARY_RECORD = 0x0020,
251 NX_AC97_SURROUND_OUTPUT = 0x0010,
252 NX_AC97_PRIMARY_READY = 0x0008, NX_AC97_PRIMARY_RECORD = 0x0004,
253 NX_AC97_PCM_OUTPUT = 0x0002,
254 NX_AC97_WARM_RESET = 0x0001
255 };
256
257 enum serial_intf_ctrl_bits {
258 WARM_REST = 0x00000001, COLD_RESET = 0x00000002,
259 I2S_CLOCK = 0x00000004, PCM_SEC_AC97= 0x00000008,
260 AC97_DBL_RATE = 0x00000010, SPDIF_EN = 0x00000020,
261 I2S_OUTPUT_EN = 0x00000040, I2S_INPUT_EN = 0x00000080,
262 PCMIN = 0x00000100, LINE1IN = 0x00000200,
263 MICIN = 0x00000400, LINE2IN = 0x00000800,
264 HEAD_SET_IN = 0x00001000, GPIOIN = 0x00002000,
265 /* 7018 spec says id = 01 but the demo board routed to 10
266 SECONDARY_ID= 0x00004000, */
267 SECONDARY_ID= 0x00004000,
268 PCMOUT = 0x00010000, SURROUT = 0x00020000,
269 CENTEROUT = 0x00040000, LFEOUT = 0x00080000,
270 LINE1OUT = 0x00100000, LINE2OUT = 0x00200000,
271 GPIOOUT = 0x00400000,
272 SI_AC97_PRIMARY_READY = 0x01000000,
273 SI_AC97_SECONDARY_READY = 0x02000000,
274 };
275
276 enum global_control_bits {
277 CHANNLE_IDX = 0x0000003f, PB_RESET = 0x00000100,
278 PAUSE_ENG = 0x00000200,
279 OVERRUN_IE = 0x00000400, UNDERRUN_IE = 0x00000800,
280 ENDLP_IE = 0x00001000, MIDLP_IE = 0x00002000,
281 ETOG_IE = 0x00004000,
282 EDROP_IE = 0x00008000, BANK_B_EN = 0x00010000
283 };
284
285 enum channel_control_bits {
286 CHANNEL_LOOP = 0x00001000, CHANNEL_SIGNED = 0x00002000,
287 CHANNEL_STEREO = 0x00004000, CHANNEL_16BITS = 0x00008000,
288 };
289
290 enum channel_attribute {
291 /* playback/record select */
292 CHANNEL_PB = 0x0000, CHANNEL_SPC_PB = 0x4000,
293 CHANNEL_REC = 0x8000, CHANNEL_REC_PB = 0xc000,
294 /* playback destination/record source select */
295 MODEM_LINE1 = 0x0000, MODEM_LINE2 = 0x0400,
296 PCM_LR = 0x0800, HSET = 0x0c00,
297 I2S_LR = 0x1000, CENTER_LFE = 0x1400,
298 SURR_LR = 0x1800, SPDIF_LR = 0x1c00,
299 MIC = 0x1400,
300 /* mist stuff */
301 MONO_LEFT = 0x0000, MONO_RIGHT = 0x0100,
302 MONO_MIX = 0x0200, SRC_ENABLE = 0x0080,
303 };
304
305 enum miscint_bits {
306 PB_UNDERRUN_IRO = 0x00000001, REC_OVERRUN_IRQ = 0x00000002,
307 SB_IRQ = 0x00000004, MPU401_IRQ = 0x00000008,
308 OPL3_IRQ = 0x00000010, ADDRESS_IRQ = 0x00000020,
309 ENVELOPE_IRQ = 0x00000040, ST_IRQ = 0x00000080,
310 PB_UNDERRUN = 0x00000100, REC_OVERRUN = 0x00000200,
311 MIXER_UNDERFLOW = 0x00000400, MIXER_OVERFLOW = 0x00000800,
312 ST_TARGET_REACHED = 0x00008000, PB_24K_MODE = 0x00010000,
313 ST_IRQ_EN = 0x00800000, ACGPIO_IRQ = 0x01000000
314 };
315
316 #define TRID_REG( trident, x ) ( (trident) -> iobase + (x) )
317
318 #define CYBER_PORT_AUDIO 0x3CE
319 #define CYBER_IDX_AUDIO_ENABLE 0x7B
320 #define CYBER_BMSK_AUDIO_INT_ENABLE 0x09
321 #define CYBER_BMSK_AUENZ 0x01
322 #define CYBER_BMSK_AUENZ_ENABLE 0x00
323 #define CYBER_IDX_IRQ_ENABLE 0x12
324
325 #define VALIDATE_MAGIC(FOO,MAG) \
326 ({ \
327 if (!(FOO) || (FOO)->magic != MAG) { \
328 printk(invalid_magic,__FUNCTION__); \
329 return -ENXIO; \
330 } \
331 })
332
333 #define VALIDATE_STATE(a) VALIDATE_MAGIC(a,TRIDENT_STATE_MAGIC)
334 #define VALIDATE_CARD(a) VALIDATE_MAGIC(a,TRIDENT_CARD_MAGIC)
335
ld2(unsigned int x)336 static inline unsigned ld2(unsigned int x)
337 {
338 unsigned r = 0;
339
340 if (x >= 0x10000) {
341 x >>= 16;
342 r += 16;
343 }
344 if (x >= 0x100) {
345 x >>= 8;
346 r += 8;
347 }
348 if (x >= 0x10) {
349 x >>= 4;
350 r += 4;
351 }
352 if (x >= 4) {
353 x >>= 2;
354 r += 2;
355 }
356 if (x >= 2)
357 r++;
358 return r;
359 }
360
361 #ifdef DEBUG
362
363 #define TRDBG(msg, args...) do { \
364 printk(KERN_DEBUG msg , ##args ); \
365 } while (0)
366
367 #else /* !defined(DEBUG) */
368
369 #define TRDBG(msg, args...) do { } while (0)
370
371 #endif /* DEBUG */
372
373 #endif /* __TRID4DWAVE_H */
374