1 /*****************************************************************************/
2
3 /*
4 * sm_wss.c -- soundcard radio modem driver, WSS (half duplex) driver
5 *
6 * Copyright (C) 1996 Thomas Sailer (sailer@ife.ee.ethz.ch)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * Please note that the GPL allows you to use the driver, NOT the radio.
23 * In order to use the radio, you need a license from the communications
24 * authority of your country.
25 *
26 */
27
28 #include <linux/ptrace.h>
29 #include <linux/sched.h>
30 #include <linux/interrupt.h>
31 #include <asm/io.h>
32 #include <asm/dma.h>
33 #include <linux/ioport.h>
34 #include <linux/soundmodem.h>
35 #include "sm.h"
36 #include "smdma.h"
37
38 /* --------------------------------------------------------------------- */
39
40 /*
41 * currently this module is supposed to support both module styles, i.e.
42 * the old one present up to about 2.1.9, and the new one functioning
43 * starting with 2.1.21. The reason is I have a kit allowing to compile
44 * this module also under 2.0.x which was requested by several people.
45 * This will go in 2.2
46 */
47 #include <linux/version.h>
48 #include <asm/uaccess.h>
49
50 /* --------------------------------------------------------------------- */
51
52 struct sc_state_wss {
53 unsigned char revwss, revid, revv, revcid;
54 unsigned char fmt[2];
55 unsigned char crystal;
56 };
57
58 #define SCSTATE ((struct sc_state_wss *)(&sm->hw))
59
60 /* --------------------------------------------------------------------- */
61
62 #define WSS_CONFIG(iobase) (iobase+0)
63 #define WSS_STATUS(iobase) (iobase+3)
64 #define WSS_CODEC_IA(iobase) (iobase+4)
65 #define WSS_CODEC_ID(iobase) (iobase+5)
66 #define WSS_CODEC_STATUS(iobase) (iobase+6)
67 #define WSS_CODEC_DATA(iobase) (iobase+7)
68
69 #define WSS_EXTENT 8
70
71 #define CS423X_HOTFIX
72
73 /* --------------------------------------------------------------------- */
74
write_codec(struct net_device * dev,unsigned char idx,unsigned char data)75 static void write_codec(struct net_device *dev, unsigned char idx,
76 unsigned char data)
77 {
78 int timeout = 900000;
79
80 /* wait until codec ready */
81 while (timeout > 0 && inb(WSS_CODEC_IA(dev->base_addr)) & 0x80)
82 timeout--;
83 outb(idx, WSS_CODEC_IA(dev->base_addr));
84 outb(data, WSS_CODEC_ID(dev->base_addr));
85 }
86
87
88 /* --------------------------------------------------------------------- */
89
read_codec(struct net_device * dev,unsigned char idx)90 static unsigned char read_codec(struct net_device *dev, unsigned char idx)
91 {
92 int timeout = 900000;
93
94 /* wait until codec ready */
95 while (timeout > 0 && inb(WSS_CODEC_IA(dev->base_addr)) & 0x80)
96 timeout--;
97 outb(idx & 0x1f, WSS_CODEC_IA(dev->base_addr));
98 return inb(WSS_CODEC_ID(dev->base_addr));
99 }
100
101 /* --------------------------------------------------------------------- */
102
wss_ack_int(struct net_device * dev)103 extern void inline wss_ack_int(struct net_device *dev)
104 {
105 outb(0, WSS_CODEC_STATUS(dev->base_addr));
106 }
107
108 /* --------------------------------------------------------------------- */
109
110 static int wss_srate_tab[16] = {
111 8000, 5510, 16000, 11025, 27420, 18900, 32000, 22050,
112 -1, 37800, -1, 44100, 48000, 33075, 9600, 6620
113 };
114
wss_srate_index(int srate)115 static int wss_srate_index(int srate)
116 {
117 int i;
118
119 for (i = 0; i < (sizeof(wss_srate_tab)/sizeof(wss_srate_tab[0])); i++)
120 if (srate == wss_srate_tab[i] && wss_srate_tab[i] > 0)
121 return i;
122 return -1;
123 }
124
125 /* --------------------------------------------------------------------- */
126
wss_set_codec_fmt(struct net_device * dev,struct sm_state * sm,unsigned char fmt,unsigned char fmt2,char fdx,char fullcalib)127 static int wss_set_codec_fmt(struct net_device *dev, struct sm_state *sm, unsigned char fmt,
128 unsigned char fmt2, char fdx, char fullcalib)
129 {
130 unsigned long time;
131 unsigned long flags;
132
133 save_flags(flags);
134 cli();
135 /* Clock and data format register */
136 write_codec(dev, 0x48, fmt);
137 if (SCSTATE->crystal) {
138 write_codec(dev, 0x5c, fmt2 & 0xf0);
139 /* MCE and interface config reg */
140 write_codec(dev, 0x49, (fdx ? 0 : 0x4) | (fullcalib ? 0x18 : 0));
141 } else
142 /* MCE and interface config reg */
143 write_codec(dev, 0x49, fdx ? 0x8 : 0xc);
144 outb(0xb, WSS_CODEC_IA(dev->base_addr)); /* leave MCE */
145 if (SCSTATE->crystal && !fullcalib) {
146 restore_flags(flags);
147 return 0;
148 }
149 /*
150 * wait for ACI start
151 */
152 time = 1000;
153 while (!(read_codec(dev, 0x0b) & 0x20))
154 if (!(--time)) {
155 printk(KERN_WARNING "%s: ad1848 auto calibration timed out (1)\n",
156 sm_drvname);
157 restore_flags(flags);
158 return -1;
159 }
160 /*
161 * wait for ACI end
162 */
163 sti();
164 time = jiffies + HZ/4;
165 while ((read_codec(dev, 0x0b) & 0x20) && ((signed)(jiffies - time) < 0));
166 restore_flags(flags);
167 if ((signed)(jiffies - time) >= 0) {
168 printk(KERN_WARNING "%s: ad1848 auto calibration timed out (2)\n",
169 sm_drvname);
170 return -1;
171 }
172 return 0;
173 }
174
175 /* --------------------------------------------------------------------- */
176
wss_init_codec(struct net_device * dev,struct sm_state * sm,char fdx,unsigned char src_l,unsigned char src_r,int igain_l,int igain_r,int ogain_l,int ogain_r)177 static int wss_init_codec(struct net_device *dev, struct sm_state *sm, char fdx,
178 unsigned char src_l, unsigned char src_r,
179 int igain_l, int igain_r,
180 int ogain_l, int ogain_r)
181 {
182 unsigned char tmp, reg0, reg1, reg6, reg7;
183 static const signed char irqtab[16] =
184 { -1, -1, 0x10, -1, -1, -1, -1, 0x08, -1, 0x10, 0x18, 0x20, -1, -1,
185 -1, -1 };
186 static const signed char dmatab[4] = { 1, 2, -1, 3 };
187
188 tmp = inb(WSS_STATUS(dev->base_addr));
189 if ((tmp & 0x3f) != 0x04 && (tmp & 0x3f) != 0x00 &&
190 (tmp & 0x3f) != 0x0f) {
191 printk(KERN_WARNING "sm: WSS card id register not found, "
192 "address 0x%lx, ID register 0x%02x\n",
193 dev->base_addr, (int)tmp);
194 /* return -1; */
195 SCSTATE->revwss = 0;
196 } else {
197 if ((tmp & 0x80) && ((dev->dma == 0) ||
198 ((dev->irq >= 8) && (dev->irq != 9)))) {
199 printk(KERN_ERR "%s: WSS: DMA0 and/or IRQ8..IRQ15 "
200 "(except IRQ9) cannot be used on an 8bit "
201 "card\n", sm_drvname);
202 return -1;
203 }
204 if (dev->irq > 15 || irqtab[dev->irq] == -1) {
205 printk(KERN_ERR "%s: WSS: invalid interrupt %d\n",
206 sm_drvname, (int)dev->irq);
207 return -1;
208 }
209 if (dev->dma > 3 || dmatab[dev->dma] == -1) {
210 printk(KERN_ERR "%s: WSS: invalid dma channel %d\n",
211 sm_drvname, (int)dev->dma);
212 return -1;
213 }
214 tmp = irqtab[dev->irq] | dmatab[dev->dma];
215 /* irq probe */
216 outb((tmp & 0x38) | 0x40, WSS_CONFIG(dev->base_addr));
217 if (!(inb(WSS_STATUS(dev->base_addr)) & 0x40)) {
218 outb(0, WSS_CONFIG(dev->base_addr));
219 printk(KERN_ERR "%s: WSS: IRQ%d is not free!\n",
220 sm_drvname, dev->irq);
221 }
222 outb(tmp, WSS_CONFIG(dev->base_addr));
223 SCSTATE->revwss = inb(WSS_STATUS(dev->base_addr)) & 0x3f;
224 }
225 /*
226 * initialize the codec
227 */
228 if (igain_l < 0)
229 igain_l = 0;
230 if (igain_r < 0)
231 igain_r = 0;
232 if (ogain_l > 0)
233 ogain_l = 0;
234 if (ogain_r > 0)
235 ogain_r = 0;
236 reg0 = (src_l << 6) & 0xc0;
237 reg1 = (src_r << 6) & 0xc0;
238 if (reg0 == 0x80 && igain_l >= 20) {
239 reg0 |= 0x20;
240 igain_l -= 20;
241 }
242 if (reg1 == 0x80 && igain_r >= 20) {
243 reg1 |= 0x20;
244 igain_r -= 20;
245 }
246 if (igain_l > 23)
247 igain_l = 23;
248 if (igain_r > 23)
249 igain_r = 23;
250 reg0 |= igain_l * 2 / 3;
251 reg1 |= igain_r * 2 / 3;
252 reg6 = (ogain_l < -95) ? 0x80 : (ogain_l * (-2) / 3);
253 reg7 = (ogain_r < -95) ? 0x80 : (ogain_r * (-2) / 3);
254 write_codec(dev, 9, 0);
255 write_codec(dev, 0, 0x45);
256 if (read_codec(dev, 0) != 0x45)
257 goto codec_err;
258 write_codec(dev, 0, 0xaa);
259 if (read_codec(dev, 0) != 0xaa)
260 goto codec_err;
261 write_codec(dev, 12, 0x40); /* enable MODE2 */
262 write_codec(dev, 16, 0);
263 write_codec(dev, 0, 0x45);
264 SCSTATE->crystal = (read_codec(dev, 16) != 0x45);
265 write_codec(dev, 0, 0xaa);
266 SCSTATE->crystal &= (read_codec(dev, 16) != 0xaa);
267 if (SCSTATE->crystal) {
268 SCSTATE->revcid = read_codec(dev, 0x19);
269 SCSTATE->revv = (SCSTATE->revcid >> 5) & 7;
270 SCSTATE->revcid &= 7;
271 write_codec(dev, 0x10, 0x80); /* maximum output level */
272 write_codec(dev, 0x11, 0x02); /* xtal enable and no HPF */
273 write_codec(dev, 0x12, 0x80); /* left line input control */
274 write_codec(dev, 0x13, 0x80); /* right line input control */
275 write_codec(dev, 0x16, 0); /* disable alternative freq sel */
276 write_codec(dev, 0x1a, 0xe0); /* mono IO disable */
277 write_codec(dev, 0x1b, 0x00); /* left out no att */
278 write_codec(dev, 0x1d, 0x00); /* right out no att */
279 }
280
281 if (wss_set_codec_fmt(dev, sm, SCSTATE->fmt[0], SCSTATE->fmt[0], fdx, 1))
282 goto codec_err;
283
284 write_codec(dev, 0, reg0); /* left input control */
285 write_codec(dev, 1, reg1); /* right input control */
286 write_codec(dev, 2, 0x80); /* left aux#1 input control */
287 write_codec(dev, 3, 0x80); /* right aux#1 input control */
288 write_codec(dev, 4, 0x80); /* left aux#2 input control */
289 write_codec(dev, 5, 0x80); /* right aux#2 input control */
290 write_codec(dev, 6, reg6); /* left dac control */
291 write_codec(dev, 7, reg7); /* right dac control */
292 write_codec(dev, 0xa, 0x2); /* pin control register */
293 write_codec(dev, 0xd, 0x0); /* digital mix control */
294 SCSTATE->revid = read_codec(dev, 0xc) & 0xf;
295 /*
296 * print revisions
297 */
298 if (SCSTATE->crystal)
299 printk(KERN_INFO "%s: Crystal CODEC ID %d, Chip revision %d, "
300 " Chip ID %d\n", sm_drvname, (int)SCSTATE->revid,
301 (int)SCSTATE->revv, (int)SCSTATE->revcid);
302 else
303 printk(KERN_INFO "%s: WSS revision %d, CODEC revision %d\n",
304 sm_drvname, (int)SCSTATE->revwss,
305 (int)SCSTATE->revid);
306 return 0;
307 codec_err:
308 outb(0, WSS_CONFIG(dev->base_addr));
309 printk(KERN_ERR "%s: no WSS soundcard found at address 0x%lx\n",
310 sm_drvname, dev->base_addr);
311 return -1;
312 }
313
314 /* --------------------------------------------------------------------- */
315
setup_dma_wss(struct net_device * dev,struct sm_state * sm,int send)316 static void setup_dma_wss(struct net_device *dev, struct sm_state *sm, int send)
317 {
318 unsigned long flags;
319 static const unsigned char codecmode[2] = { 0x0e, 0x0d };
320 unsigned char oldcodecmode;
321 long abrt;
322 unsigned char fmt;
323 unsigned int numsamps;
324
325 send = !!send;
326 fmt = SCSTATE->fmt[send];
327 save_flags(flags);
328 cli();
329 /*
330 * perform the final DMA sequence to disable the codec request
331 */
332 oldcodecmode = read_codec(dev, 9);
333 write_codec(dev, 9, 0xc); /* disable codec */
334 wss_ack_int(dev);
335 if (read_codec(dev, 11) & 0x10) {
336 dma_setup(sm, oldcodecmode & 1, dev->dma);
337 abrt = 0;
338 while ((read_codec(dev, 11) & 0x10) || ((++abrt) >= 0x10000));
339 }
340 #ifdef CS423X_HOTFIX
341 if (read_codec(dev, 0x8) != fmt || SCSTATE->crystal)
342 wss_set_codec_fmt(dev, sm, fmt, fmt, 0, 0);
343 #else /* CS423X_HOTFIX */
344 if (read_codec(dev, 0x8) != fmt)
345 wss_set_codec_fmt(dev, sm, fmt, fmt, 0, 0);
346 #endif /* CS423X_HOTFIX */
347 numsamps = dma_setup(sm, send, dev->dma) - 1;
348 write_codec(dev, 15, numsamps & 0xff);
349 write_codec(dev, 14, numsamps >> 8);
350 write_codec(dev, 9, codecmode[send]);
351 restore_flags(flags);
352 }
353
354 /* --------------------------------------------------------------------- */
355
wss_interrupt(int irq,void * dev_id,struct pt_regs * regs)356 static void wss_interrupt(int irq, void *dev_id, struct pt_regs *regs)
357 {
358 struct net_device *dev = (struct net_device *)dev_id;
359 struct sm_state *sm = (struct sm_state *)dev->priv;
360 unsigned int curfrag;
361 unsigned int nums;
362
363 if (!dev || !sm || !sm->mode_rx || !sm->mode_tx ||
364 sm->hdrv.magic != HDLCDRV_MAGIC)
365 return;
366 cli();
367 wss_ack_int(dev);
368 disable_dma(dev->dma);
369 clear_dma_ff(dev->dma);
370 nums = dma_ptr(sm, sm->dma.ptt_cnt > 0, dev->dma, &curfrag) - 1;
371 write_codec(dev, 15, nums & 0xff);
372 write_codec(dev, 14, nums >> 8);
373 enable_dma(dev->dma);
374 sm_int_freq(sm);
375 sti();
376 if (sm->dma.ptt_cnt <= 0) {
377 dma_receive(sm, curfrag);
378 hdlcdrv_arbitrate(dev, &sm->hdrv);
379 if (hdlcdrv_ptt(&sm->hdrv)) {
380 /* starting to transmit */
381 disable_dma(dev->dma);
382 hdlcdrv_transmitter(dev, &sm->hdrv); /* prefill HDLC buffer */
383 dma_start_transmit(sm);
384 setup_dma_wss(dev, sm, 1);
385 dma_transmit(sm);
386 }
387 } else if (dma_end_transmit(sm, curfrag)) {
388 /* stopping transmission */
389 disable_dma(dev->dma);
390 dma_init_receive(sm);
391 setup_dma_wss(dev, sm, 0);
392 } else
393 dma_transmit(sm);
394 sm_output_status(sm);
395 hdlcdrv_transmitter(dev, &sm->hdrv);
396 hdlcdrv_receiver(dev, &sm->hdrv);
397 }
398
399 /* --------------------------------------------------------------------- */
400
wss_open(struct net_device * dev,struct sm_state * sm)401 static int wss_open(struct net_device *dev, struct sm_state *sm)
402 {
403 unsigned int dmasz, u;
404
405 if (sizeof(sm->m) < sizeof(struct sc_state_wss)) {
406 printk(KERN_ERR "sm wss: wss state too big: %d > %d\n",
407 sizeof(struct sc_state_wss), sizeof(sm->m));
408 return -ENODEV;
409 }
410 if (!dev || !sm || !sm->mode_rx || !sm->mode_tx)
411 return -ENXIO;
412 if (dev->base_addr <= 0 || dev->base_addr > 0x1000-WSS_EXTENT ||
413 dev->irq < 2 || dev->irq > 15 || dev->dma > 3)
414 return -ENXIO;
415 if (check_region(dev->base_addr, WSS_EXTENT))
416 return -EACCES;
417 /*
418 * check if a card is available
419 */
420 if (wss_init_codec(dev, sm, 0, 1, 1, 0, 0, -45, -45))
421 return -ENODEV;
422 /*
423 * initialize some variables
424 */
425 dma_init_receive(sm);
426 dmasz = (NUM_FRAGMENTS + 1) * sm->dma.ifragsz;
427 u = NUM_FRAGMENTS * sm->dma.ofragsz;
428 if (u > dmasz)
429 dmasz = u;
430 if (!(sm->dma.ibuf = sm->dma.obuf = kmalloc(dmasz, GFP_KERNEL | GFP_DMA)))
431 return -ENOMEM;
432 dma_init_transmit(sm);
433 dma_init_receive(sm);
434
435 memset(&sm->m, 0, sizeof(sm->m));
436 memset(&sm->d, 0, sizeof(sm->d));
437 if (sm->mode_tx->init)
438 sm->mode_tx->init(sm);
439 if (sm->mode_rx->init)
440 sm->mode_rx->init(sm);
441
442 if (request_dma(dev->dma, sm->hwdrv->hw_name)) {
443 kfree(sm->dma.obuf);
444 return -EBUSY;
445 }
446 if (request_irq(dev->irq, wss_interrupt, SA_INTERRUPT,
447 sm->hwdrv->hw_name, dev)) {
448 free_dma(dev->dma);
449 kfree(sm->dma.obuf);
450 return -EBUSY;
451 }
452 request_region(dev->base_addr, WSS_EXTENT, sm->hwdrv->hw_name);
453 setup_dma_wss(dev, sm, 0);
454 return 0;
455 }
456
457 /* --------------------------------------------------------------------- */
458
wss_close(struct net_device * dev,struct sm_state * sm)459 static int wss_close(struct net_device *dev, struct sm_state *sm)
460 {
461 if (!dev || !sm)
462 return -EINVAL;
463 /*
464 * disable interrupts
465 */
466 disable_dma(dev->dma);
467 write_codec(dev, 9, 0xc); /* disable codec */
468 free_irq(dev->irq, dev);
469 free_dma(dev->dma);
470 release_region(dev->base_addr, WSS_EXTENT);
471 kfree(sm->dma.obuf);
472 return 0;
473 }
474
475 /* --------------------------------------------------------------------- */
476
wss_sethw(struct net_device * dev,struct sm_state * sm,char * mode)477 static int wss_sethw(struct net_device *dev, struct sm_state *sm, char *mode)
478 {
479 char *cp = strchr(mode, '.');
480 const struct modem_tx_info **mtp = sm_modem_tx_table;
481 const struct modem_rx_info **mrp;
482 int i, j;
483
484 if (!strcmp(mode, "off")) {
485 sm->mode_tx = NULL;
486 sm->mode_rx = NULL;
487 return 0;
488 }
489 if (cp)
490 *cp++ = '\0';
491 else
492 cp = mode;
493 for (; *mtp; mtp++) {
494 if ((*mtp)->loc_storage > sizeof(sm->m)) {
495 printk(KERN_ERR "%s: insufficient storage for modulator %s (%d)\n",
496 sm_drvname, (*mtp)->name, (*mtp)->loc_storage);
497 continue;
498 }
499 if (!(*mtp)->name || strcmp((*mtp)->name, mode))
500 continue;
501 if ((i = wss_srate_index((*mtp)->srate)) < 0)
502 continue;
503 for (mrp = sm_modem_rx_table; *mrp; mrp++) {
504 if ((*mrp)->loc_storage > sizeof(sm->d)) {
505 printk(KERN_ERR "%s: insufficient storage for demodulator %s (%d)\n",
506 sm_drvname, (*mrp)->name, (*mrp)->loc_storage);
507 continue;
508 }
509 if ((*mrp)->name && !strcmp((*mrp)->name, cp) &&
510 ((j = wss_srate_index((*mrp)->srate)) >= 0)) {
511 sm->mode_tx = *mtp;
512 sm->mode_rx = *mrp;
513 SCSTATE->fmt[0] = j;
514 SCSTATE->fmt[1] = i;
515 sm->dma.ifragsz = (sm->mode_rx->srate + 50)/100;
516 sm->dma.ofragsz = (sm->mode_tx->srate + 50)/100;
517 if (sm->dma.ifragsz < sm->mode_rx->overlap)
518 sm->dma.ifragsz = sm->mode_rx->overlap;
519 /* prefer same data format if possible to minimize switching times */
520 sm->dma.i16bit = sm->dma.o16bit = 2;
521 if (sm->mode_rx->srate == sm->mode_tx->srate) {
522 if (sm->mode_rx->demodulator_s16 && sm->mode_tx->modulator_s16)
523 sm->dma.i16bit = sm->dma.o16bit = 1;
524 else if (sm->mode_rx->demodulator_u8 && sm->mode_tx->modulator_u8)
525 sm->dma.i16bit = sm->dma.o16bit = 0;
526 }
527 if (sm->dma.i16bit == 2) {
528 if (sm->mode_rx->demodulator_s16)
529 sm->dma.i16bit = 1;
530 else if (sm->mode_rx->demodulator_u8)
531 sm->dma.i16bit = 0;
532 }
533 if (sm->dma.o16bit == 2) {
534 if (sm->mode_tx->modulator_s16)
535 sm->dma.o16bit = 1;
536 else if (sm->mode_tx->modulator_u8)
537 sm->dma.o16bit = 0;
538 }
539 if (sm->dma.i16bit == 2 || sm->dma.o16bit == 2) {
540 printk(KERN_INFO "%s: mode %s or %s unusable\n", sm_drvname,
541 sm->mode_rx->name, sm->mode_tx->name);
542 sm->mode_tx = NULL;
543 sm->mode_rx = NULL;
544 return -EINVAL;
545 }
546 #ifdef __BIG_ENDIAN
547 /* big endian 16bit only works on crystal cards... */
548 if (sm->dma.i16bit) {
549 SCSTATE->fmt[0] |= 0xc0;
550 sm->dma.ifragsz <<= 1;
551 }
552 if (sm->dma.o16bit) {
553 SCSTATE->fmt[1] |= 0xc0;
554 sm->dma.ofragsz <<= 1;
555 }
556 #else /* __BIG_ENDIAN */
557 if (sm->dma.i16bit) {
558 SCSTATE->fmt[0] |= 0x40;
559 sm->dma.ifragsz <<= 1;
560 }
561 if (sm->dma.o16bit) {
562 SCSTATE->fmt[1] |= 0x40;
563 sm->dma.ofragsz <<= 1;
564 }
565 #endif /* __BIG_ENDIAN */
566 return 0;
567 }
568 }
569 }
570 return -EINVAL;
571 }
572
573 /* --------------------------------------------------------------------- */
574
wss_ioctl(struct net_device * dev,struct sm_state * sm,struct ifreq * ifr,struct hdlcdrv_ioctl * hi,int cmd)575 static int wss_ioctl(struct net_device *dev, struct sm_state *sm, struct ifreq *ifr,
576 struct hdlcdrv_ioctl *hi, int cmd)
577 {
578 struct sm_ioctl bi;
579 int i;
580
581 if (cmd != SIOCDEVPRIVATE)
582 return -ENOIOCTLCMD;
583
584 if (hi->cmd == HDLCDRVCTL_MODEMPARMASK)
585 return HDLCDRV_PARMASK_IOBASE | HDLCDRV_PARMASK_IRQ |
586 HDLCDRV_PARMASK_DMA | HDLCDRV_PARMASK_SERIOBASE |
587 HDLCDRV_PARMASK_PARIOBASE | HDLCDRV_PARMASK_MIDIIOBASE;
588
589 if (copy_from_user(&bi, ifr->ifr_data, sizeof(bi)))
590 return -EFAULT;
591
592 switch (bi.cmd) {
593 default:
594 return -ENOIOCTLCMD;
595
596 case SMCTL_GETMIXER:
597 i = 0;
598 bi.data.mix.sample_rate = sm->mode_rx->srate;
599 bi.data.mix.bit_rate = sm->hdrv.par.bitrate;
600 bi.data.mix.mixer_type = SCSTATE->crystal ?
601 SM_MIXER_CRYSTAL : SM_MIXER_AD1848;
602 if (((SCSTATE->crystal ? 0x2c0c20fflu: 0x20fflu)
603 >> bi.data.mix.reg) & 1) {
604 bi.data.mix.data = read_codec(dev, bi.data.mix.reg);
605 i = 1;
606 }
607 if (copy_to_user(ifr->ifr_data, &bi, sizeof(bi)))
608 return -EFAULT;
609 return i;
610
611 case SMCTL_SETMIXER:
612 if (!capable(CAP_SYS_RAWIO))
613 return -EACCES;
614 if ((bi.data.mix.mixer_type != SM_MIXER_CRYSTAL ||
615 !SCSTATE->crystal) &&
616 (bi.data.mix.mixer_type != SM_MIXER_AD1848 ||
617 bi.data.mix.reg >= 0x10))
618 return -EINVAL;
619 if (!((0x2c0c20fflu >> bi.data.mix.reg) & 1))
620 return -EACCES;
621 write_codec(dev, bi.data.mix.reg, bi.data.mix.data);
622 return 0;
623
624 }
625 if (copy_to_user(ifr->ifr_data, &bi, sizeof(bi)))
626 return -EFAULT;
627 return 0;
628
629 }
630
631 /* --------------------------------------------------------------------- */
632
633 const struct hardware_info sm_hw_wss = {
634 "wss", sizeof(struct sc_state_wss),
635 wss_open, wss_close, wss_ioctl, wss_sethw
636 };
637
638 /* --------------------------------------------------------------------- */
639
setup_fdx_dma_wss(struct net_device * dev,struct sm_state * sm)640 static void setup_fdx_dma_wss(struct net_device *dev, struct sm_state *sm)
641 {
642 unsigned long flags;
643 unsigned char oldcodecmode, codecdma;
644 long abrt;
645 unsigned int osamps, isamps;
646
647 save_flags(flags);
648 cli();
649 /*
650 * perform the final DMA sequence to disable the codec request
651 */
652 oldcodecmode = read_codec(dev, 9);
653 write_codec(dev, 9, 0); /* disable codec DMA */
654 wss_ack_int(dev);
655 if ((codecdma = read_codec(dev, 11)) & 0x10) {
656 dma_setup(sm, 1, dev->dma);
657 dma_setup(sm, 0, sm->hdrv.ptt_out.dma2);
658 abrt = 0;
659 while (((codecdma = read_codec(dev, 11)) & 0x10) || ((++abrt) >= 0x10000));
660 }
661 wss_set_codec_fmt(dev, sm, SCSTATE->fmt[1], SCSTATE->fmt[0], 1, 1);
662 osamps = dma_setup(sm, 1, dev->dma) - 1;
663 isamps = dma_setup(sm, 0, sm->hdrv.ptt_out.dma2) - 1;
664 write_codec(dev, 15, osamps & 0xff);
665 write_codec(dev, 14, osamps >> 8);
666 if (SCSTATE->crystal) {
667 write_codec(dev, 31, isamps & 0xff);
668 write_codec(dev, 30, isamps >> 8);
669 }
670 write_codec(dev, 9, 3);
671 restore_flags(flags);
672 }
673
674 /* --------------------------------------------------------------------- */
675
wssfdx_interrupt(int irq,void * dev_id,struct pt_regs * regs)676 static void wssfdx_interrupt(int irq, void *dev_id, struct pt_regs *regs)
677 {
678 struct net_device *dev = (struct net_device *)dev_id;
679 struct sm_state *sm = (struct sm_state *)dev->priv;
680 unsigned long flags;
681 unsigned char cry_int_src;
682 unsigned icfrag, ocfrag, isamps, osamps;
683
684 if (!dev || !sm || !sm->mode_rx || !sm->mode_tx ||
685 sm->hdrv.magic != HDLCDRV_MAGIC)
686 return;
687 save_flags(flags);
688 cli();
689 if (SCSTATE->crystal) {
690 /* Crystal has an essentially different interrupt handler! */
691 cry_int_src = read_codec(dev, 0x18);
692 wss_ack_int(dev);
693 if (cry_int_src & 0x10) { /* playback interrupt */
694 disable_dma(dev->dma);
695 clear_dma_ff(dev->dma);
696 osamps = dma_ptr(sm, 1, dev->dma, &ocfrag)-1;
697 write_codec(dev, 15, osamps & 0xff);
698 write_codec(dev, 14, osamps >> 8);
699 enable_dma(dev->dma);
700 }
701 if (cry_int_src & 0x20) { /* capture interrupt */
702 disable_dma(sm->hdrv.ptt_out.dma2);
703 clear_dma_ff(sm->hdrv.ptt_out.dma2);
704 isamps = dma_ptr(sm, 0, sm->hdrv.ptt_out.dma2, &icfrag)-1;
705 write_codec(dev, 31, isamps & 0xff);
706 write_codec(dev, 30, isamps >> 8);
707 enable_dma(sm->hdrv.ptt_out.dma2);
708 }
709 restore_flags(flags);
710 sm_int_freq(sm);
711 sti();
712 if (cry_int_src & 0x10) {
713 if (dma_end_transmit(sm, ocfrag))
714 dma_clear_transmit(sm);
715 dma_transmit(sm);
716 }
717 if (cry_int_src & 0x20) {
718 dma_receive(sm, icfrag);
719 hdlcdrv_arbitrate(dev, &sm->hdrv);
720 }
721 sm_output_status(sm);
722 hdlcdrv_transmitter(dev, &sm->hdrv);
723 hdlcdrv_receiver(dev, &sm->hdrv);
724 return;
725 }
726 wss_ack_int(dev);
727 disable_dma(dev->dma);
728 disable_dma(sm->hdrv.ptt_out.dma2);
729 clear_dma_ff(dev->dma);
730 clear_dma_ff(sm->hdrv.ptt_out.dma2);
731 osamps = dma_ptr(sm, 1, dev->dma, &ocfrag)-1;
732 isamps = dma_ptr(sm, 0, sm->hdrv.ptt_out.dma2, &icfrag)-1;
733 write_codec(dev, 15, osamps & 0xff);
734 write_codec(dev, 14, osamps >> 8);
735 if (SCSTATE->crystal) {
736 write_codec(dev, 31, isamps & 0xff);
737 write_codec(dev, 30, isamps >> 8);
738 }
739 enable_dma(dev->dma);
740 enable_dma(sm->hdrv.ptt_out.dma2);
741 restore_flags(flags);
742 sm_int_freq(sm);
743 sti();
744 if (dma_end_transmit(sm, ocfrag))
745 dma_clear_transmit(sm);
746 dma_transmit(sm);
747 dma_receive(sm, icfrag);
748 hdlcdrv_arbitrate(dev, &sm->hdrv);
749 sm_output_status(sm);
750 hdlcdrv_transmitter(dev, &sm->hdrv);
751 hdlcdrv_receiver(dev, &sm->hdrv);
752 }
753
754 /* --------------------------------------------------------------------- */
755
wssfdx_open(struct net_device * dev,struct sm_state * sm)756 static int wssfdx_open(struct net_device *dev, struct sm_state *sm)
757 {
758 if (!dev || !sm || !sm->mode_rx || !sm->mode_tx)
759 return -ENXIO;
760 if (dev->base_addr <= 0 || dev->base_addr > 0x1000-WSS_EXTENT ||
761 dev->irq < 2 || dev->irq > 15 || dev->dma > 3)
762 return -ENXIO;
763 if (check_region(dev->base_addr, WSS_EXTENT))
764 return -EACCES;
765 /*
766 * check if a card is available
767 */
768 if (wss_init_codec(dev, sm, 1, 1, 1, 0, 0, -45, -45))
769 return -ENODEV;
770 /*
771 * initialize some variables
772 */
773 if (!(sm->dma.ibuf = kmalloc(sm->dma.ifragsz * (NUM_FRAGMENTS+1), GFP_KERNEL | GFP_DMA)))
774 return -ENOMEM;
775 if (!(sm->dma.obuf = kmalloc(sm->dma.ofragsz * NUM_FRAGMENTS, GFP_KERNEL | GFP_DMA))) {
776 kfree(sm->dma.ibuf);
777 return -ENOMEM;
778 }
779 dma_init_transmit(sm);
780 dma_init_receive(sm);
781
782 memset(&sm->m, 0, sizeof(sm->m));
783 memset(&sm->d, 0, sizeof(sm->d));
784 if (sm->mode_tx->init)
785 sm->mode_tx->init(sm);
786 if (sm->mode_rx->init)
787 sm->mode_rx->init(sm);
788
789 if (request_dma(dev->dma, sm->hwdrv->hw_name)) {
790 kfree(sm->dma.ibuf);
791 kfree(sm->dma.obuf);
792 return -EBUSY;
793 }
794 if (request_dma(sm->hdrv.ptt_out.dma2, sm->hwdrv->hw_name)) {
795 kfree(sm->dma.ibuf);
796 kfree(sm->dma.obuf);
797 free_dma(dev->dma);
798 return -EBUSY;
799 }
800 if (request_irq(dev->irq, wssfdx_interrupt, SA_INTERRUPT,
801 sm->hwdrv->hw_name, dev)) {
802 kfree(sm->dma.ibuf);
803 kfree(sm->dma.obuf);
804 free_dma(dev->dma);
805 free_dma(sm->hdrv.ptt_out.dma2);
806 return -EBUSY;
807 }
808 request_region(dev->base_addr, WSS_EXTENT, sm->hwdrv->hw_name);
809 setup_fdx_dma_wss(dev, sm);
810 return 0;
811 }
812
813 /* --------------------------------------------------------------------- */
814
wssfdx_close(struct net_device * dev,struct sm_state * sm)815 static int wssfdx_close(struct net_device *dev, struct sm_state *sm)
816 {
817 if (!dev || !sm)
818 return -EINVAL;
819 /*
820 * disable interrupts
821 */
822 disable_dma(dev->dma);
823 disable_dma(sm->hdrv.ptt_out.dma2);
824 write_codec(dev, 9, 0xc); /* disable codec */
825 free_irq(dev->irq, dev);
826 free_dma(dev->dma);
827 free_dma(sm->hdrv.ptt_out.dma2);
828 release_region(dev->base_addr, WSS_EXTENT);
829 kfree(sm->dma.ibuf);
830 kfree(sm->dma.obuf);
831 return 0;
832 }
833
834 /* --------------------------------------------------------------------- */
835
wssfdx_sethw(struct net_device * dev,struct sm_state * sm,char * mode)836 static int wssfdx_sethw(struct net_device *dev, struct sm_state *sm, char *mode)
837 {
838 char *cp = strchr(mode, '.');
839 const struct modem_tx_info **mtp = sm_modem_tx_table;
840 const struct modem_rx_info **mrp;
841 int i;
842
843 if (!strcmp(mode, "off")) {
844 sm->mode_tx = NULL;
845 sm->mode_rx = NULL;
846 return 0;
847 }
848 if (cp)
849 *cp++ = '\0';
850 else
851 cp = mode;
852 for (; *mtp; mtp++) {
853 if ((*mtp)->loc_storage > sizeof(sm->m)) {
854 printk(KERN_ERR "%s: insufficient storage for modulator %s (%d)\n",
855 sm_drvname, (*mtp)->name, (*mtp)->loc_storage);
856 continue;
857 }
858 if (!(*mtp)->name || strcmp((*mtp)->name, mode))
859 continue;
860 if ((i = wss_srate_index((*mtp)->srate)) < 0)
861 continue;
862 for (mrp = sm_modem_rx_table; *mrp; mrp++) {
863 if ((*mrp)->loc_storage > sizeof(sm->d)) {
864 printk(KERN_ERR "%s: insufficient storage for demodulator %s (%d)\n",
865 sm_drvname, (*mrp)->name, (*mrp)->loc_storage);
866 continue;
867 }
868 if ((*mrp)->name && !strcmp((*mrp)->name, cp) &&
869 (*mtp)->srate == (*mrp)->srate) {
870 sm->mode_tx = *mtp;
871 sm->mode_rx = *mrp;
872 SCSTATE->fmt[0] = SCSTATE->fmt[1] = i;
873 sm->dma.ifragsz = sm->dma.ofragsz = (sm->mode_rx->srate + 50)/100;
874 if (sm->dma.ifragsz < sm->mode_rx->overlap)
875 sm->dma.ifragsz = sm->mode_rx->overlap;
876 sm->dma.i16bit = sm->dma.o16bit = 2;
877 if (sm->mode_rx->demodulator_s16) {
878 sm->dma.i16bit = 1;
879 sm->dma.ifragsz <<= 1;
880 #ifdef __BIG_ENDIAN /* big endian 16bit only works on crystal cards... */
881 SCSTATE->fmt[0] |= 0xc0;
882 #else /* __BIG_ENDIAN */
883 SCSTATE->fmt[0] |= 0x40;
884 #endif /* __BIG_ENDIAN */
885 } else if (sm->mode_rx->demodulator_u8)
886 sm->dma.i16bit = 0;
887 if (sm->mode_tx->modulator_s16) {
888 sm->dma.o16bit = 1;
889 sm->dma.ofragsz <<= 1;
890 #ifdef __BIG_ENDIAN /* big endian 16bit only works on crystal cards... */
891 SCSTATE->fmt[1] |= 0xc0;
892 #else /* __BIG_ENDIAN */
893 SCSTATE->fmt[1] |= 0x40;
894 #endif /* __BIG_ENDIAN */
895 } else if (sm->mode_tx->modulator_u8)
896 sm->dma.o16bit = 0;
897 if (sm->dma.i16bit == 2 || sm->dma.o16bit == 2) {
898 printk(KERN_INFO "%s: mode %s or %s unusable\n", sm_drvname,
899 sm->mode_rx->name, sm->mode_tx->name);
900 sm->mode_tx = NULL;
901 sm->mode_rx = NULL;
902 return -EINVAL;
903 }
904 return 0;
905 }
906 }
907 }
908 return -EINVAL;
909 }
910
911 /* --------------------------------------------------------------------- */
912
wssfdx_ioctl(struct net_device * dev,struct sm_state * sm,struct ifreq * ifr,struct hdlcdrv_ioctl * hi,int cmd)913 static int wssfdx_ioctl(struct net_device *dev, struct sm_state *sm, struct ifreq *ifr,
914 struct hdlcdrv_ioctl *hi, int cmd)
915 {
916 if (cmd != SIOCDEVPRIVATE)
917 return -ENOIOCTLCMD;
918
919 if (hi->cmd == HDLCDRVCTL_MODEMPARMASK)
920 return HDLCDRV_PARMASK_IOBASE | HDLCDRV_PARMASK_IRQ |
921 HDLCDRV_PARMASK_DMA | HDLCDRV_PARMASK_DMA2 |
922 HDLCDRV_PARMASK_SERIOBASE | HDLCDRV_PARMASK_PARIOBASE |
923 HDLCDRV_PARMASK_MIDIIOBASE;
924
925 return wss_ioctl(dev, sm, ifr, hi, cmd);
926 }
927
928 /* --------------------------------------------------------------------- */
929
930 const struct hardware_info sm_hw_wssfdx = {
931 "wssfdx", sizeof(struct sc_state_wss),
932 wssfdx_open, wssfdx_close, wssfdx_ioctl, wssfdx_sethw
933 };
934
935 /* --------------------------------------------------------------------- */
936
937 #undef SCSTATE
938