1 #define _VERSION "0.20"
2 /* ns83820.c by Benjamin LaHaise with contributions.
3 *
4 * Questions/comments/discussion to linux-ns83820@kvack.org.
5 *
6 * $Revision: 1.34.2.23 $
7 *
8 * Copyright 2001 Benjamin LaHaise.
9 * Copyright 2001, 2002 Red Hat.
10 *
11 * Mmmm, chocolate vanilla mocha...
12 *
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 *
28 *
29 * ChangeLog
30 * =========
31 * 20010414 0.1 - created
32 * 20010622 0.2 - basic rx and tx.
33 * 20010711 0.3 - added duplex and link state detection support.
34 * 20010713 0.4 - zero copy, no hangs.
35 * 0.5 - 64 bit dma support (davem will hate me for this)
36 * - disable jumbo frames to avoid tx hangs
37 * - work around tx deadlocks on my 1.02 card via
38 * fiddling with TXCFG
39 * 20010810 0.6 - use pci dma api for ringbuffers, work on ia64
40 * 20010816 0.7 - misc cleanups
41 * 20010826 0.8 - fix critical zero copy bugs
42 * 0.9 - internal experiment
43 * 20010827 0.10 - fix ia64 unaligned access.
44 * 20010906 0.11 - accept all packets with checksum errors as
45 * otherwise fragments get lost
46 * - fix >> 32 bugs
47 * 0.12 - add statistics counters
48 * - add allmulti/promisc support
49 * 20011009 0.13 - hotplug support, other smaller pci api cleanups
50 * 20011204 0.13a - optical transceiver support added
51 * by Michael Clark <michael@metaparadigm.com>
52 * 20011205 0.13b - call register_netdev earlier in initialization
53 * suppress duplicate link status messages
54 * 20011117 0.14 - ethtool GDRVINFO, GLINK support from jgarzik
55 * 20011204 0.15 get ppc (big endian) working
56 * 20011218 0.16 various cleanups
57 * 20020310 0.17 speedups
58 * 20020610 0.18 - actually use the pci dma api for highmem
59 * - remove pci latency register fiddling
60 * 0.19 - better bist support
61 * - add ihr and reset_phy parameters
62 * - gmii bus probing
63 * - fix missed txok introduced during performance
64 * tuning
65 * 0.20 - fix stupid RFEN thinko. i am such a smurf.
66 *
67 * Driver Overview
68 * ===============
69 *
70 * This driver was originally written for the National Semiconductor
71 * 83820 chip, a 10/100/1000 Mbps 64 bit PCI ethernet NIC. Hopefully
72 * this code will turn out to be a) clean, b) correct, and c) fast.
73 * With that in mind, I'm aiming to split the code up as much as
74 * reasonably possible. At present there are X major sections that
75 * break down into a) packet receive, b) packet transmit, c) link
76 * management, d) initialization and configuration. Where possible,
77 * these code paths are designed to run in parallel.
78 *
79 * This driver has been tested and found to work with the following
80 * cards (in no particular order):
81 *
82 * Cameo SOHO-GA2000T SOHO-GA2500T
83 * D-Link DGE-500T
84 * PureData PDP8023Z-TG
85 * SMC SMC9452TX SMC9462TX
86 * Netgear GA621
87 *
88 * Special thanks to SMC for providing hardware to test this driver on.
89 *
90 * Reports of success or failure would be greatly appreciated.
91 */
92 //#define dprintk printk
93 #define dprintk(x...) do { } while (0)
94
95 #include <linux/module.h>
96 #include <linux/types.h>
97 #include <linux/pci.h>
98 #include <linux/netdevice.h>
99 #include <linux/etherdevice.h>
100 #include <linux/delay.h>
101 #include <linux/smp_lock.h>
102 #include <linux/tqueue.h>
103 #include <linux/init.h>
104 #include <linux/ip.h> /* for iph */
105 #include <linux/in.h> /* for IPPROTO_... */
106 #include <linux/eeprom.h>
107 #include <linux/compiler.h>
108 #include <linux/prefetch.h>
109 #include <linux/ethtool.h>
110 #include <linux/timer.h>
111
112 #include <asm/io.h>
113 #include <asm/uaccess.h>
114
115 /* Global parameters. See MODULE_PARM near the bottom. */
116 static int ihr = 2;
117 static int reset_phy = 0;
118 static int lnksts = 0; /* CFG_LNKSTS bit polarity */
119
120 /* Dprintk is used for more interesting debug events */
121 #undef Dprintk
122 #define Dprintk dprintk
123
124 #if defined(CONFIG_HIGHMEM64G) || defined(__ia64__)
125 #define USE_64BIT_ADDR "+"
126 #endif
127
128 #if defined(USE_64BIT_ADDR)
129 #define VERSION _VERSION USE_64BIT_ADDR
130 #define TRY_DAC 1
131 #else
132 #define VERSION _VERSION
133 #define TRY_DAC 0
134 #endif
135
136 /* tunables */
137 #define RX_BUF_SIZE 1500 /* 8192 */
138
139 /* Must not exceed ~65000. */
140 #define NR_RX_DESC 64
141 #define NR_TX_DESC 128
142
143 /* not tunable */
144 #define REAL_RX_BUF_SIZE (RX_BUF_SIZE + 14) /* rx/tx mac addr + type */
145
146 #define MIN_TX_DESC_FREE 8
147
148 /* register defines */
149 #define CFGCS 0x04
150
151 #define CR_TXE 0x00000001
152 #define CR_TXD 0x00000002
153 /* Ramit : Here's a tip, don't do a RXD immediately followed by an RXE
154 * The Receive engine skips one descriptor and moves
155 * onto the next one!! */
156 #define CR_RXE 0x00000004
157 #define CR_RXD 0x00000008
158 #define CR_TXR 0x00000010
159 #define CR_RXR 0x00000020
160 #define CR_SWI 0x00000080
161 #define CR_RST 0x00000100
162
163 #define PTSCR_EEBIST_FAIL 0x00000001
164 #define PTSCR_EEBIST_EN 0x00000002
165 #define PTSCR_EELOAD_EN 0x00000004
166 #define PTSCR_RBIST_FAIL 0x000001b8
167 #define PTSCR_RBIST_DONE 0x00000200
168 #define PTSCR_RBIST_EN 0x00000400
169 #define PTSCR_RBIST_RST 0x00002000
170
171 #define MEAR_EEDI 0x00000001
172 #define MEAR_EEDO 0x00000002
173 #define MEAR_EECLK 0x00000004
174 #define MEAR_EESEL 0x00000008
175 #define MEAR_MDIO 0x00000010
176 #define MEAR_MDDIR 0x00000020
177 #define MEAR_MDC 0x00000040
178
179 #define ISR_TXDESC3 0x40000000
180 #define ISR_TXDESC2 0x20000000
181 #define ISR_TXDESC1 0x10000000
182 #define ISR_TXDESC0 0x08000000
183 #define ISR_RXDESC3 0x04000000
184 #define ISR_RXDESC2 0x02000000
185 #define ISR_RXDESC1 0x01000000
186 #define ISR_RXDESC0 0x00800000
187 #define ISR_TXRCMP 0x00400000
188 #define ISR_RXRCMP 0x00200000
189 #define ISR_DPERR 0x00100000
190 #define ISR_SSERR 0x00080000
191 #define ISR_RMABT 0x00040000
192 #define ISR_RTABT 0x00020000
193 #define ISR_RXSOVR 0x00010000
194 #define ISR_HIBINT 0x00008000
195 #define ISR_PHY 0x00004000
196 #define ISR_PME 0x00002000
197 #define ISR_SWI 0x00001000
198 #define ISR_MIB 0x00000800
199 #define ISR_TXURN 0x00000400
200 #define ISR_TXIDLE 0x00000200
201 #define ISR_TXERR 0x00000100
202 #define ISR_TXDESC 0x00000080
203 #define ISR_TXOK 0x00000040
204 #define ISR_RXORN 0x00000020
205 #define ISR_RXIDLE 0x00000010
206 #define ISR_RXEARLY 0x00000008
207 #define ISR_RXERR 0x00000004
208 #define ISR_RXDESC 0x00000002
209 #define ISR_RXOK 0x00000001
210
211 #define TXCFG_CSI 0x80000000
212 #define TXCFG_HBI 0x40000000
213 #define TXCFG_MLB 0x20000000
214 #define TXCFG_ATP 0x10000000
215 #define TXCFG_ECRETRY 0x00800000
216 #define TXCFG_BRST_DIS 0x00080000
217 #define TXCFG_MXDMA1024 0x00000000
218 #define TXCFG_MXDMA512 0x00700000
219 #define TXCFG_MXDMA256 0x00600000
220 #define TXCFG_MXDMA128 0x00500000
221 #define TXCFG_MXDMA64 0x00400000
222 #define TXCFG_MXDMA32 0x00300000
223 #define TXCFG_MXDMA16 0x00200000
224 #define TXCFG_MXDMA8 0x00100000
225
226 #define CFG_LNKSTS 0x80000000
227 #define CFG_SPDSTS 0x60000000
228 #define CFG_SPDSTS1 0x40000000
229 #define CFG_SPDSTS0 0x20000000
230 #define CFG_DUPSTS 0x10000000
231 #define CFG_TBI_EN 0x01000000
232 #define CFG_MODE_1000 0x00400000
233 /* Ramit : Dont' ever use AUTO_1000, it never works and is buggy.
234 * Read the Phy response and then configure the MAC accordingly */
235 #define CFG_AUTO_1000 0x00200000
236 #define CFG_PINT_CTL 0x001c0000
237 #define CFG_PINT_DUPSTS 0x00100000
238 #define CFG_PINT_LNKSTS 0x00080000
239 #define CFG_PINT_SPDSTS 0x00040000
240 #define CFG_TMRTEST 0x00020000
241 #define CFG_MRM_DIS 0x00010000
242 #define CFG_MWI_DIS 0x00008000
243 #define CFG_T64ADDR 0x00004000
244 #define CFG_PCI64_DET 0x00002000
245 #define CFG_DATA64_EN 0x00001000
246 #define CFG_M64ADDR 0x00000800
247 #define CFG_PHY_RST 0x00000400
248 #define CFG_PHY_DIS 0x00000200
249 #define CFG_EXTSTS_EN 0x00000100
250 #define CFG_REQALG 0x00000080
251 #define CFG_SB 0x00000040
252 #define CFG_POW 0x00000020
253 #define CFG_EXD 0x00000010
254 #define CFG_PESEL 0x00000008
255 #define CFG_BROM_DIS 0x00000004
256 #define CFG_EXT_125 0x00000002
257 #define CFG_BEM 0x00000001
258
259 #define EXTSTS_UDPPKT 0x00200000
260 #define EXTSTS_TCPPKT 0x00080000
261 #define EXTSTS_IPPKT 0x00020000
262
263 #define SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0))
264
265 #define MIBC_MIBS 0x00000008
266 #define MIBC_ACLR 0x00000004
267 #define MIBC_FRZ 0x00000002
268 #define MIBC_WRN 0x00000001
269
270 #define PCR_PSEN (1 << 31)
271 #define PCR_PS_MCAST (1 << 30)
272 #define PCR_PS_DA (1 << 29)
273 #define PCR_STHI_8 (3 << 23)
274 #define PCR_STLO_4 (1 << 23)
275 #define PCR_FFHI_8K (3 << 21)
276 #define PCR_FFLO_4K (1 << 21)
277 #define PCR_PAUSE_CNT 0xFFFE
278
279 #define RXCFG_AEP 0x80000000
280 #define RXCFG_ARP 0x40000000
281 #define RXCFG_STRIPCRC 0x20000000
282 #define RXCFG_RX_FD 0x10000000
283 #define RXCFG_ALP 0x08000000
284 #define RXCFG_AIRL 0x04000000
285 #define RXCFG_MXDMA512 0x00700000
286 #define RXCFG_DRTH 0x0000003e
287 #define RXCFG_DRTH0 0x00000002
288
289 #define RFCR_RFEN 0x80000000
290 #define RFCR_AAB 0x40000000
291 #define RFCR_AAM 0x20000000
292 #define RFCR_AAU 0x10000000
293 #define RFCR_APM 0x08000000
294 #define RFCR_APAT 0x07800000
295 #define RFCR_APAT3 0x04000000
296 #define RFCR_APAT2 0x02000000
297 #define RFCR_APAT1 0x01000000
298 #define RFCR_APAT0 0x00800000
299 #define RFCR_AARP 0x00400000
300 #define RFCR_MHEN 0x00200000
301 #define RFCR_UHEN 0x00100000
302 #define RFCR_ULM 0x00080000
303
304 #define VRCR_RUDPE 0x00000080
305 #define VRCR_RTCPE 0x00000040
306 #define VRCR_RIPE 0x00000020
307 #define VRCR_IPEN 0x00000010
308 #define VRCR_DUTF 0x00000008
309 #define VRCR_DVTF 0x00000004
310 #define VRCR_VTREN 0x00000002
311 #define VRCR_VTDEN 0x00000001
312
313 #define VTCR_PPCHK 0x00000008
314 #define VTCR_GCHK 0x00000004
315 #define VTCR_VPPTI 0x00000002
316 #define VTCR_VGTI 0x00000001
317
318 #define CR 0x00
319 #define CFG 0x04
320 #define MEAR 0x08
321 #define PTSCR 0x0c
322 #define ISR 0x10
323 #define IMR 0x14
324 #define IER 0x18
325 #define IHR 0x1c
326 #define TXDP 0x20
327 #define TXDP_HI 0x24
328 #define TXCFG 0x28
329 #define GPIOR 0x2c
330 #define RXDP 0x30
331 #define RXDP_HI 0x34
332 #define RXCFG 0x38
333 #define PQCR 0x3c
334 #define WCSR 0x40
335 #define PCR 0x44
336 #define RFCR 0x48
337 #define RFDR 0x4c
338
339 #define SRR 0x58
340
341 #define VRCR 0xbc
342 #define VTCR 0xc0
343 #define VDR 0xc4
344 #define CCSR 0xcc
345
346 #define TBICR 0xe0
347 #define TBISR 0xe4
348 #define TANAR 0xe8
349 #define TANLPAR 0xec
350 #define TANER 0xf0
351 #define TESR 0xf4
352
353 #define TBICR_MR_AN_ENABLE 0x00001000
354 #define TBICR_MR_RESTART_AN 0x00000200
355
356 #define TBISR_MR_LINK_STATUS 0x00000020
357 #define TBISR_MR_AN_COMPLETE 0x00000004
358
359 #define TANAR_PS2 0x00000100
360 #define TANAR_PS1 0x00000080
361 #define TANAR_HALF_DUP 0x00000040
362 #define TANAR_FULL_DUP 0x00000020
363
364 #define GPIOR_GP5_OE 0x00000200
365 #define GPIOR_GP4_OE 0x00000100
366 #define GPIOR_GP3_OE 0x00000080
367 #define GPIOR_GP2_OE 0x00000040
368 #define GPIOR_GP1_OE 0x00000020
369 #define GPIOR_GP3_OUT 0x00000004
370 #define GPIOR_GP1_OUT 0x00000001
371
372 #define LINK_AUTONEGOTIATE 0x01
373 #define LINK_DOWN 0x02
374 #define LINK_UP 0x04
375
376 #define __kick_rx(dev) writel(CR_RXE, dev->base + CR)
377
378 #define kick_rx(dev) do { \
379 dprintk("kick_rx: maybe kicking\n"); \
380 if (test_and_clear_bit(0, &dev->rx_info.idle)) { \
381 dprintk("actually kicking\n"); \
382 writel(dev->rx_info.phy_descs + (4 * DESC_SIZE * dev->rx_info.next_rx), dev->base + RXDP); \
383 if (dev->rx_info.next_rx == dev->rx_info.next_empty) \
384 printk(KERN_DEBUG "%s: uh-oh: next_rx == next_empty???\n", dev->net_dev.name);\
385 __kick_rx(dev); \
386 } \
387 } while(0)
388
389 #ifdef USE_64BIT_ADDR
390 #define HW_ADDR_LEN 8
391 #define desc_addr_set(desc, addr) \
392 do { \
393 u64 __addr = (addr); \
394 (desc)[0] = cpu_to_le32(__addr); \
395 (desc)[1] = cpu_to_le32(__addr >> 32); \
396 } while(0)
397 #define desc_addr_get(desc) \
398 (((u64)le32_to_cpu((desc)[1]) << 32) \
399 | le32_to_cpu((desc)[0]))
400 #else
401 #define HW_ADDR_LEN 4
402 #define desc_addr_set(desc, addr) ((desc)[0] = cpu_to_le32(addr))
403 #define desc_addr_get(desc) (le32_to_cpu((desc)[0]))
404 #endif
405
406 #define DESC_LINK 0
407 #define DESC_BUFPTR (DESC_LINK + HW_ADDR_LEN/4)
408 #define DESC_CMDSTS (DESC_BUFPTR + HW_ADDR_LEN/4)
409 #define DESC_EXTSTS (DESC_CMDSTS + 4/4)
410
411 #define CMDSTS_OWN 0x80000000
412 #define CMDSTS_MORE 0x40000000
413 #define CMDSTS_INTR 0x20000000
414 #define CMDSTS_ERR 0x10000000
415 #define CMDSTS_OK 0x08000000
416 #define CMDSTS_LEN_MASK 0x0000ffff
417
418 #define CMDSTS_DEST_MASK 0x01800000
419 #define CMDSTS_DEST_SELF 0x00800000
420 #define CMDSTS_DEST_MULTI 0x01000000
421
422 #define DESC_SIZE 8 /* Should be cache line sized */
423
424 struct rx_info {
425 spinlock_t lock;
426 int up;
427 long idle;
428
429 struct sk_buff *skbs[NR_RX_DESC];
430
431 u32 *next_rx_desc;
432 u16 next_rx, next_empty;
433
434 u32 *descs;
435 dma_addr_t phy_descs;
436 };
437
438
439 struct ns83820 {
440 struct net_device net_dev;
441 struct net_device_stats stats;
442 u8 *base;
443
444 struct pci_dev *pci_dev;
445
446 struct rx_info rx_info;
447 struct tasklet_struct rx_tasklet;
448
449 unsigned ihr;
450 struct tq_struct tq_refill;
451
452 /* protects everything below. irqsave when using. */
453 spinlock_t misc_lock;
454
455 u32 CFG_cache;
456
457 u32 MEAR_cache;
458 u32 IMR_cache;
459 struct eeprom ee;
460
461 unsigned linkstate;
462
463 spinlock_t tx_lock;
464
465 u16 tx_done_idx;
466 u16 tx_idx;
467 volatile u16 tx_free_idx; /* idx of free desc chain */
468 u16 tx_intr_idx;
469
470 atomic_t nr_tx_skbs;
471 struct sk_buff *tx_skbs[NR_TX_DESC];
472
473 char pad[16] __attribute__((aligned(16)));
474 u32 *tx_descs;
475 dma_addr_t tx_phy_descs;
476
477 struct timer_list tx_watchdog;
478 };
479
480 //free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC
481 #define start_tx_okay(dev) \
482 (((NR_TX_DESC-2 + dev->tx_done_idx - dev->tx_free_idx) % NR_TX_DESC) > MIN_TX_DESC_FREE)
483
484
485 /* Packet Receiver
486 *
487 * The hardware supports linked lists of receive descriptors for
488 * which ownership is transfered back and forth by means of an
489 * ownership bit. While the hardware does support the use of a
490 * ring for receive descriptors, we only make use of a chain in
491 * an attempt to reduce bus traffic under heavy load scenarios.
492 * This will also make bugs a bit more obvious. The current code
493 * only makes use of a single rx chain; I hope to implement
494 * priority based rx for version 1.0. Goal: even under overload
495 * conditions, still route realtime traffic with as low jitter as
496 * possible.
497 */
build_rx_desc(struct ns83820 * dev,u32 * desc,dma_addr_t link,dma_addr_t buf,u32 cmdsts,u32 extsts)498 static inline void build_rx_desc(struct ns83820 *dev, u32 *desc, dma_addr_t link, dma_addr_t buf, u32 cmdsts, u32 extsts)
499 {
500 desc_addr_set(desc + DESC_LINK, link);
501 desc_addr_set(desc + DESC_BUFPTR, buf);
502 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
503 mb();
504 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
505 }
506
507 #define nr_rx_empty(dev) ((NR_RX_DESC-2 + dev->rx_info.next_rx - dev->rx_info.next_empty) % NR_RX_DESC)
ns83820_add_rx_skb(struct ns83820 * dev,struct sk_buff * skb)508 static inline int ns83820_add_rx_skb(struct ns83820 *dev, struct sk_buff *skb)
509 {
510 unsigned next_empty;
511 u32 cmdsts;
512 u32 *sg;
513 dma_addr_t buf;
514
515 next_empty = dev->rx_info.next_empty;
516
517 /* don't overrun last rx marker */
518 if (unlikely(nr_rx_empty(dev) <= 2)) {
519 kfree_skb(skb);
520 return 1;
521 }
522
523 #if 0
524 dprintk("next_empty[%d] nr_used[%d] next_rx[%d]\n",
525 dev->rx_info.next_empty,
526 dev->rx_info.nr_used,
527 dev->rx_info.next_rx
528 );
529 #endif
530
531 sg = dev->rx_info.descs + (next_empty * DESC_SIZE);
532 if (unlikely(NULL != dev->rx_info.skbs[next_empty]))
533 BUG();
534 dev->rx_info.skbs[next_empty] = skb;
535
536 dev->rx_info.next_empty = (next_empty + 1) % NR_RX_DESC;
537 cmdsts = REAL_RX_BUF_SIZE | CMDSTS_INTR;
538 buf = pci_map_single(dev->pci_dev, skb->tail,
539 REAL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
540 build_rx_desc(dev, sg, 0, buf, cmdsts, 0);
541 /* update link of previous rx */
542 if (likely(next_empty != dev->rx_info.next_rx))
543 dev->rx_info.descs[((NR_RX_DESC + next_empty - 1) % NR_RX_DESC) * DESC_SIZE] = cpu_to_le32(dev->rx_info.phy_descs + (next_empty * DESC_SIZE * 4));
544
545 return 0;
546 }
547
rx_refill(struct ns83820 * dev,int gfp)548 static inline int rx_refill(struct ns83820 *dev, int gfp)
549 {
550 unsigned i;
551 long flags = 0;
552
553 if (unlikely(nr_rx_empty(dev) <= 2))
554 return 0;
555
556 dprintk("rx_refill(%p)\n", dev);
557 if (gfp == GFP_ATOMIC)
558 spin_lock_irqsave(&dev->rx_info.lock, flags);
559 for (i=0; i<NR_RX_DESC; i++) {
560 struct sk_buff *skb;
561 long res;
562 /* extra 16 bytes for alignment */
563 skb = __dev_alloc_skb(REAL_RX_BUF_SIZE+16, gfp);
564 if (unlikely(!skb))
565 break;
566
567 res = (long)skb->tail & 0xf;
568 res = 0x10 - res;
569 res &= 0xf;
570 skb_reserve(skb, res);
571
572 skb->dev = &dev->net_dev;
573 if (gfp != GFP_ATOMIC)
574 spin_lock_irqsave(&dev->rx_info.lock, flags);
575 res = ns83820_add_rx_skb(dev, skb);
576 if (gfp != GFP_ATOMIC)
577 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
578 if (res) {
579 i = 1;
580 break;
581 }
582 }
583 if (gfp == GFP_ATOMIC)
584 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
585
586 return i ? 0 : -ENOMEM;
587 }
588
589 static void FASTCALL(rx_refill_atomic(struct ns83820 *dev));
rx_refill_atomic(struct ns83820 * dev)590 static void fastcall rx_refill_atomic(struct ns83820 *dev)
591 {
592 rx_refill(dev, GFP_ATOMIC);
593 }
594
595 /* REFILL */
queue_refill(void * _dev)596 static inline void queue_refill(void *_dev)
597 {
598 struct ns83820 *dev = _dev;
599
600 rx_refill(dev, GFP_KERNEL);
601 if (dev->rx_info.up)
602 kick_rx(dev);
603 }
604
clear_rx_desc(struct ns83820 * dev,unsigned i)605 static inline void clear_rx_desc(struct ns83820 *dev, unsigned i)
606 {
607 build_rx_desc(dev, dev->rx_info.descs + (DESC_SIZE * i), 0, 0, CMDSTS_OWN, 0);
608 }
609
610 static void FASTCALL(phy_intr(struct ns83820 *dev));
phy_intr(struct ns83820 * dev)611 static void fastcall phy_intr(struct ns83820 *dev)
612 {
613 static char *speeds[] = { "10", "100", "1000", "1000(?)", "1000F" };
614 u32 cfg, new_cfg;
615 u32 tbisr, tanar, tanlpar;
616 int speed, fullduplex, newlinkstate;
617
618 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
619
620 if (dev->CFG_cache & CFG_TBI_EN) {
621 /* we have an optical transceiver */
622 tbisr = readl(dev->base + TBISR);
623 tanar = readl(dev->base + TANAR);
624 tanlpar = readl(dev->base + TANLPAR);
625 dprintk("phy_intr: tbisr=%08x, tanar=%08x, tanlpar=%08x\n",
626 tbisr, tanar, tanlpar);
627
628 if ( (fullduplex = (tanlpar & TANAR_FULL_DUP)
629 && (tanar & TANAR_FULL_DUP)) ) {
630
631 /* both of us are full duplex */
632 writel(readl(dev->base + TXCFG)
633 | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP,
634 dev->base + TXCFG);
635 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
636 dev->base + RXCFG);
637 /* Light up full duplex LED */
638 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
639 dev->base + GPIOR);
640
641 } else if(((tanlpar & TANAR_HALF_DUP)
642 && (tanar & TANAR_HALF_DUP))
643 || ((tanlpar & TANAR_FULL_DUP)
644 && (tanar & TANAR_HALF_DUP))
645 || ((tanlpar & TANAR_HALF_DUP)
646 && (tanar & TANAR_FULL_DUP))) {
647
648 /* one or both of us are half duplex */
649 writel((readl(dev->base + TXCFG)
650 & ~(TXCFG_CSI | TXCFG_HBI)) | TXCFG_ATP,
651 dev->base + TXCFG);
652 writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD,
653 dev->base + RXCFG);
654 /* Turn off full duplex LED */
655 writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT,
656 dev->base + GPIOR);
657 }
658
659 speed = 4; /* 1000F */
660
661 } else {
662 /* we have a copper transceiver */
663 new_cfg = dev->CFG_cache & ~(CFG_SB | CFG_MODE_1000 | CFG_SPDSTS);
664
665 if (cfg & CFG_SPDSTS1)
666 new_cfg |= CFG_MODE_1000;
667 else
668 new_cfg &= ~CFG_MODE_1000;
669
670 speed = ((cfg / CFG_SPDSTS0) & 3);
671 fullduplex = (cfg & CFG_DUPSTS);
672
673 if (fullduplex)
674 new_cfg |= CFG_SB;
675
676 if ((cfg & CFG_LNKSTS) &&
677 ((new_cfg ^ dev->CFG_cache) & CFG_MODE_1000)) {
678 writel(new_cfg, dev->base + CFG);
679 dev->CFG_cache = new_cfg;
680 }
681
682 dev->CFG_cache &= ~CFG_SPDSTS;
683 dev->CFG_cache |= cfg & CFG_SPDSTS;
684 }
685
686 newlinkstate = (cfg & CFG_LNKSTS) ? LINK_UP : LINK_DOWN;
687
688 if (newlinkstate & LINK_UP
689 && dev->linkstate != newlinkstate) {
690 netif_start_queue(&dev->net_dev);
691 netif_wake_queue(&dev->net_dev);
692 printk(KERN_INFO "%s: link now %s mbps, %s duplex and up.\n",
693 dev->net_dev.name,
694 speeds[speed],
695 fullduplex ? "full" : "half");
696 } else if (newlinkstate & LINK_DOWN
697 && dev->linkstate != newlinkstate) {
698 netif_stop_queue(&dev->net_dev);
699 printk(KERN_INFO "%s: link now down.\n", dev->net_dev.name);
700 }
701
702 dev->linkstate = newlinkstate;
703 }
704
ns83820_setup_rx(struct ns83820 * dev)705 static int ns83820_setup_rx(struct ns83820 *dev)
706 {
707 unsigned i;
708 int ret;
709
710 dprintk("ns83820_setup_rx(%p)\n", dev);
711
712 dev->rx_info.idle = 1;
713 dev->rx_info.next_rx = 0;
714 dev->rx_info.next_rx_desc = dev->rx_info.descs;
715 dev->rx_info.next_empty = 0;
716
717 for (i=0; i<NR_RX_DESC; i++)
718 clear_rx_desc(dev, i);
719
720 writel(0, dev->base + RXDP_HI);
721 writel(dev->rx_info.phy_descs, dev->base + RXDP);
722
723 ret = rx_refill(dev, GFP_KERNEL);
724 if (!ret) {
725 dprintk("starting receiver\n");
726 /* prevent the interrupt handler from stomping on us */
727 spin_lock_irq(&dev->rx_info.lock);
728
729 writel(0x0001, dev->base + CCSR);
730 writel(0, dev->base + RFCR);
731 writel(0x7fc00000, dev->base + RFCR);
732 writel(0xffc00000, dev->base + RFCR);
733
734 dev->rx_info.up = 1;
735
736 phy_intr(dev);
737
738 /* Okay, let it rip */
739 spin_lock_irq(&dev->misc_lock);
740 dev->IMR_cache |= ISR_PHY;
741 dev->IMR_cache |= ISR_RXRCMP;
742 //dev->IMR_cache |= ISR_RXERR;
743 //dev->IMR_cache |= ISR_RXOK;
744 dev->IMR_cache |= ISR_RXORN;
745 dev->IMR_cache |= ISR_RXSOVR;
746 dev->IMR_cache |= ISR_RXDESC;
747 dev->IMR_cache |= ISR_RXIDLE;
748 dev->IMR_cache |= ISR_TXDESC;
749 dev->IMR_cache |= ISR_TXIDLE;
750
751 writel(dev->IMR_cache, dev->base + IMR);
752 writel(1, dev->base + IER);
753 spin_unlock_irq(&dev->misc_lock);
754
755 kick_rx(dev);
756
757 spin_unlock_irq(&dev->rx_info.lock);
758 }
759 return ret;
760 }
761
ns83820_cleanup_rx(struct ns83820 * dev)762 static void ns83820_cleanup_rx(struct ns83820 *dev)
763 {
764 unsigned i;
765 long flags;
766
767 dprintk("ns83820_cleanup_rx(%p)\n", dev);
768
769 /* disable receive interrupts */
770 spin_lock_irqsave(&dev->misc_lock, flags);
771 dev->IMR_cache &= ~(ISR_RXOK | ISR_RXDESC | ISR_RXERR | ISR_RXEARLY | ISR_RXIDLE);
772 writel(dev->IMR_cache, dev->base + IMR);
773 spin_unlock_irqrestore(&dev->misc_lock, flags);
774
775 /* synchronize with the interrupt handler and kill it */
776 dev->rx_info.up = 0;
777 synchronize_irq();
778
779 /* touch the pci bus... */
780 readl(dev->base + IMR);
781
782 /* assumes the transmitter is already disabled and reset */
783 writel(0, dev->base + RXDP_HI);
784 writel(0, dev->base + RXDP);
785
786 for (i=0; i<NR_RX_DESC; i++) {
787 struct sk_buff *skb = dev->rx_info.skbs[i];
788 dev->rx_info.skbs[i] = NULL;
789 clear_rx_desc(dev, i);
790 if (skb)
791 kfree_skb(skb);
792 }
793 }
794
795 static void FASTCALL(ns83820_rx_kick(struct ns83820 *dev));
ns83820_rx_kick(struct ns83820 * dev)796 static void fastcall ns83820_rx_kick(struct ns83820 *dev)
797 {
798 /*if (nr_rx_empty(dev) >= NR_RX_DESC/4)*/ {
799 if (dev->rx_info.up) {
800 rx_refill_atomic(dev);
801 kick_rx(dev);
802 }
803 }
804
805 if (dev->rx_info.up && nr_rx_empty(dev) > NR_RX_DESC*3/4)
806 schedule_task(&dev->tq_refill);
807 else
808 kick_rx(dev);
809 if (dev->rx_info.idle)
810 printk(KERN_DEBUG "%s: BAD\n", dev->net_dev.name);
811 }
812
813 /* rx_irq
814 *
815 */
816 static void FASTCALL(rx_irq(struct ns83820 *dev));
rx_irq(struct ns83820 * dev)817 static void fastcall rx_irq(struct ns83820 *dev)
818 {
819 struct rx_info *info = &dev->rx_info;
820 unsigned next_rx;
821 u32 cmdsts, *desc;
822 long flags;
823 int nr = 0;
824
825 dprintk("rx_irq(%p)\n", dev);
826 dprintk("rxdp: %08x, descs: %08lx next_rx[%d]: %p next_empty[%d]: %p\n",
827 readl(dev->base + RXDP),
828 (long)(dev->rx_info.phy_descs),
829 (int)dev->rx_info.next_rx,
830 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_rx)),
831 (int)dev->rx_info.next_empty,
832 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_empty))
833 );
834
835 spin_lock_irqsave(&info->lock, flags);
836 if (!info->up)
837 goto out;
838
839 dprintk("walking descs\n");
840 next_rx = info->next_rx;
841 desc = info->next_rx_desc;
842 while ((CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) &&
843 (cmdsts != CMDSTS_OWN)) {
844 struct sk_buff *skb;
845 u32 extsts = le32_to_cpu(desc[DESC_EXTSTS]);
846 dma_addr_t bufptr = desc_addr_get(desc + DESC_BUFPTR);
847
848 dprintk("cmdsts: %08x\n", cmdsts);
849 dprintk("link: %08x\n", cpu_to_le32(desc[DESC_LINK]));
850 dprintk("extsts: %08x\n", extsts);
851
852 skb = info->skbs[next_rx];
853 info->skbs[next_rx] = NULL;
854 info->next_rx = (next_rx + 1) % NR_RX_DESC;
855
856 mb();
857 clear_rx_desc(dev, next_rx);
858
859 pci_unmap_single(dev->pci_dev, bufptr,
860 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
861 if (likely(CMDSTS_OK & cmdsts)) {
862 int len = cmdsts & 0xffff;
863 skb_put(skb, len);
864 if (unlikely(!skb))
865 goto netdev_mangle_me_harder_failed;
866 if (cmdsts & CMDSTS_DEST_MULTI)
867 dev->stats.multicast ++;
868 dev->stats.rx_packets ++;
869 dev->stats.rx_bytes += len;
870 if ((extsts & 0x002a0000) && !(extsts & 0x00540000)) {
871 skb->ip_summed = CHECKSUM_UNNECESSARY;
872 } else {
873 skb->ip_summed = CHECKSUM_NONE;
874 }
875 skb->protocol = eth_type_trans(skb, &dev->net_dev);
876 if (NET_RX_DROP == netif_rx(skb)) {
877 netdev_mangle_me_harder_failed:
878 dev->stats.rx_dropped ++;
879 }
880 } else {
881 kfree_skb(skb);
882 }
883
884 nr++;
885 next_rx = info->next_rx;
886 desc = info->descs + (DESC_SIZE * next_rx);
887 }
888 info->next_rx = next_rx;
889 info->next_rx_desc = info->descs + (DESC_SIZE * next_rx);
890
891 out:
892 if (0 && !nr) {
893 Dprintk("dazed: cmdsts_f: %08x\n", cmdsts);
894 }
895
896 spin_unlock_irqrestore(&info->lock, flags);
897 }
898
rx_action(unsigned long _dev)899 static void rx_action(unsigned long _dev)
900 {
901 struct ns83820 *dev = (void *)_dev;
902 rx_irq(dev);
903 writel(ihr, dev->base + IHR);
904
905 spin_lock_irq(&dev->misc_lock);
906 dev->IMR_cache |= ISR_RXDESC;
907 writel(dev->IMR_cache, dev->base + IMR);
908 spin_unlock_irq(&dev->misc_lock);
909
910 rx_irq(dev);
911 ns83820_rx_kick(dev);
912 }
913
914 /* Packet Transmit code
915 */
kick_tx(struct ns83820 * dev)916 static inline void kick_tx(struct ns83820 *dev)
917 {
918 dprintk("kick_tx(%p): tx_idx=%d free_idx=%d\n",
919 dev, dev->tx_idx, dev->tx_free_idx);
920 writel(CR_TXE, dev->base + CR);
921 }
922
923 /* No spinlock needed on the transmit irq path as the interrupt handler is
924 * serialized.
925 */
do_tx_done(struct ns83820 * dev)926 static void do_tx_done(struct ns83820 *dev)
927 {
928 u32 cmdsts, tx_done_idx, *desc;
929
930 spin_lock_irq(&dev->tx_lock);
931
932 dprintk("do_tx_done(%p)\n", dev);
933 tx_done_idx = dev->tx_done_idx;
934 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
935
936 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
937 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
938 while ((tx_done_idx != dev->tx_free_idx) &&
939 !(CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) ) {
940 struct sk_buff *skb;
941 unsigned len;
942 dma_addr_t addr;
943
944 if (cmdsts & CMDSTS_ERR)
945 dev->stats.tx_errors ++;
946 if (cmdsts & CMDSTS_OK)
947 dev->stats.tx_packets ++;
948 if (cmdsts & CMDSTS_OK)
949 dev->stats.tx_bytes += cmdsts & 0xffff;
950
951 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
952 tx_done_idx, dev->tx_free_idx, cmdsts);
953 skb = dev->tx_skbs[tx_done_idx];
954 dev->tx_skbs[tx_done_idx] = NULL;
955 dprintk("done(%p)\n", skb);
956
957 len = cmdsts & CMDSTS_LEN_MASK;
958 addr = desc_addr_get(desc + DESC_BUFPTR);
959 if (skb) {
960 pci_unmap_single(dev->pci_dev,
961 addr,
962 len,
963 PCI_DMA_TODEVICE);
964 dev_kfree_skb_irq(skb);
965 atomic_dec(&dev->nr_tx_skbs);
966 } else
967 pci_unmap_page(dev->pci_dev,
968 addr,
969 len,
970 PCI_DMA_TODEVICE);
971
972 tx_done_idx = (tx_done_idx + 1) % NR_TX_DESC;
973 dev->tx_done_idx = tx_done_idx;
974 desc[DESC_CMDSTS] = cpu_to_le32(0);
975 mb();
976 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
977 }
978
979 /* Allow network stack to resume queueing packets after we've
980 * finished transmitting at least 1/4 of the packets in the queue.
981 */
982 if (netif_queue_stopped(&dev->net_dev) && start_tx_okay(dev)) {
983 dprintk("start_queue(%p)\n", dev);
984 netif_start_queue(&dev->net_dev);
985 netif_wake_queue(&dev->net_dev);
986 }
987 spin_unlock_irq(&dev->tx_lock);
988 }
989
ns83820_cleanup_tx(struct ns83820 * dev)990 static void ns83820_cleanup_tx(struct ns83820 *dev)
991 {
992 unsigned i;
993
994 for (i=0; i<NR_TX_DESC; i++) {
995 struct sk_buff *skb = dev->tx_skbs[i];
996 dev->tx_skbs[i] = NULL;
997 if (skb) {
998 u32 *desc = dev->tx_descs + (i * DESC_SIZE);
999 pci_unmap_single(dev->pci_dev,
1000 desc_addr_get(desc + DESC_BUFPTR),
1001 le32_to_cpu(desc[DESC_CMDSTS]) & CMDSTS_LEN_MASK,
1002 PCI_DMA_TODEVICE);
1003 dev_kfree_skb_irq(skb);
1004 atomic_dec(&dev->nr_tx_skbs);
1005 }
1006 }
1007
1008 memset(dev->tx_descs, 0, NR_TX_DESC * DESC_SIZE * 4);
1009 }
1010
1011 /* transmit routine. This code relies on the network layer serializing
1012 * its calls in, but will run happily in parallel with the interrupt
1013 * handler. This code currently has provisions for fragmenting tx buffers
1014 * while trying to track down a bug in either the zero copy code or
1015 * the tx fifo (hence the MAX_FRAG_LEN).
1016 */
ns83820_hard_start_xmit(struct sk_buff * skb,struct net_device * _dev)1017 static int ns83820_hard_start_xmit(struct sk_buff *skb, struct net_device *_dev)
1018 {
1019 struct ns83820 *dev = (struct ns83820 *)_dev;
1020 u32 free_idx, cmdsts, extsts;
1021 int nr_free, nr_frags;
1022 unsigned tx_done_idx, last_idx;
1023 dma_addr_t buf;
1024 unsigned len;
1025 skb_frag_t *frag;
1026 int stopped = 0;
1027 int do_intr = 0;
1028 volatile u32 *first_desc;
1029
1030 dprintk("ns83820_hard_start_xmit\n");
1031
1032 nr_frags = skb_shinfo(skb)->nr_frags;
1033 again:
1034 if (unlikely(dev->CFG_cache & CFG_LNKSTS)) {
1035 netif_stop_queue(&dev->net_dev);
1036 if (unlikely(dev->CFG_cache & CFG_LNKSTS))
1037 return 1;
1038 netif_start_queue(&dev->net_dev);
1039 }
1040
1041 last_idx = free_idx = dev->tx_free_idx;
1042 tx_done_idx = dev->tx_done_idx;
1043 nr_free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC;
1044 nr_free -= 1;
1045 if (nr_free <= nr_frags) {
1046 dprintk("stop_queue - not enough(%p)\n", dev);
1047 netif_stop_queue(&dev->net_dev);
1048
1049 /* Check again: we may have raced with a tx done irq */
1050 if (dev->tx_done_idx != tx_done_idx) {
1051 dprintk("restart queue(%p)\n", dev);
1052 netif_start_queue(&dev->net_dev);
1053 goto again;
1054 }
1055 return 1;
1056 }
1057
1058 if (free_idx == dev->tx_intr_idx) {
1059 do_intr = 1;
1060 dev->tx_intr_idx = (dev->tx_intr_idx + NR_TX_DESC/4) % NR_TX_DESC;
1061 }
1062
1063 nr_free -= nr_frags;
1064 if (nr_free < MIN_TX_DESC_FREE) {
1065 dprintk("stop_queue - last entry(%p)\n", dev);
1066 netif_stop_queue(&dev->net_dev);
1067 stopped = 1;
1068 }
1069
1070 frag = skb_shinfo(skb)->frags;
1071 if (!nr_frags)
1072 frag = 0;
1073 extsts = 0;
1074 if (skb->ip_summed == CHECKSUM_HW) {
1075 extsts |= EXTSTS_IPPKT;
1076 if (IPPROTO_TCP == skb->nh.iph->protocol)
1077 extsts |= EXTSTS_TCPPKT;
1078 else if (IPPROTO_UDP == skb->nh.iph->protocol)
1079 extsts |= EXTSTS_UDPPKT;
1080 }
1081
1082 len = skb->len;
1083 if (nr_frags)
1084 len -= skb->data_len;
1085 buf = pci_map_single(dev->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
1086
1087 first_desc = dev->tx_descs + (free_idx * DESC_SIZE);
1088
1089 for (;;) {
1090 volatile u32 *desc = dev->tx_descs + (free_idx * DESC_SIZE);
1091 u32 residue = 0;
1092
1093 dprintk("frag[%3u]: %4u @ 0x%08Lx\n", free_idx, len,
1094 (unsigned long long)buf);
1095 last_idx = free_idx;
1096 free_idx = (free_idx + 1) % NR_TX_DESC;
1097 desc[DESC_LINK] = cpu_to_le32(dev->tx_phy_descs + (free_idx * DESC_SIZE * 4));
1098 desc_addr_set(desc + DESC_BUFPTR, buf);
1099 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
1100
1101 cmdsts = ((nr_frags|residue) ? CMDSTS_MORE : do_intr ? CMDSTS_INTR : 0);
1102 cmdsts |= (desc == first_desc) ? 0 : CMDSTS_OWN;
1103 cmdsts |= len;
1104 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
1105
1106 if (residue) {
1107 buf += len;
1108 len = residue;
1109 continue;
1110 }
1111
1112 if (!nr_frags)
1113 break;
1114
1115 buf = pci_map_page(dev->pci_dev, frag->page,
1116 frag->page_offset,
1117 frag->size, PCI_DMA_TODEVICE);
1118 dprintk("frag: buf=%08Lx page=%08lx offset=%08lx\n",
1119 (long long)buf, (long)(frag->page - mem_map),
1120 frag->page_offset);
1121 len = frag->size;
1122 frag++;
1123 nr_frags--;
1124 }
1125 dprintk("done pkt\n");
1126
1127 spin_lock_irq(&dev->tx_lock);
1128 dev->tx_skbs[last_idx] = skb;
1129 first_desc[DESC_CMDSTS] |= cpu_to_le32(CMDSTS_OWN);
1130 dev->tx_free_idx = free_idx;
1131 atomic_inc(&dev->nr_tx_skbs);
1132 spin_unlock_irq(&dev->tx_lock);
1133
1134 kick_tx(dev);
1135
1136 /* Check again: we may have raced with a tx done irq */
1137 if (stopped && (dev->tx_done_idx != tx_done_idx) && start_tx_okay(dev))
1138 netif_start_queue(&dev->net_dev);
1139
1140 /* set the transmit start time to catch transmit timeouts */
1141 dev->net_dev.trans_start = jiffies;
1142 return 0;
1143 }
1144
ns83820_update_stats(struct ns83820 * dev)1145 static void ns83820_update_stats(struct ns83820 *dev)
1146 {
1147 u8 *base = dev->base;
1148
1149 /* the DP83820 will freeze counters, so we need to read all of them */
1150 dev->stats.rx_errors += readl(base + 0x60) & 0xffff;
1151 dev->stats.rx_crc_errors += readl(base + 0x64) & 0xffff;
1152 dev->stats.rx_missed_errors += readl(base + 0x68) & 0xffff;
1153 dev->stats.rx_frame_errors += readl(base + 0x6c) & 0xffff;
1154 /*dev->stats.rx_symbol_errors +=*/ readl(base + 0x70);
1155 dev->stats.rx_length_errors += readl(base + 0x74) & 0xffff;
1156 dev->stats.rx_length_errors += readl(base + 0x78) & 0xffff;
1157 /*dev->stats.rx_badopcode_errors += */ readl(base + 0x7c);
1158 /*dev->stats.rx_pause_count += */ readl(base + 0x80);
1159 /*dev->stats.tx_pause_count += */ readl(base + 0x84);
1160 dev->stats.tx_carrier_errors += readl(base + 0x88) & 0xff;
1161 }
1162
ns83820_get_stats(struct net_device * _dev)1163 static struct net_device_stats *ns83820_get_stats(struct net_device *_dev)
1164 {
1165 struct ns83820 *dev = (void *)_dev;
1166
1167 /* somewhat overkill */
1168 spin_lock_irq(&dev->misc_lock);
1169 ns83820_update_stats(dev);
1170 spin_unlock_irq(&dev->misc_lock);
1171
1172 return &dev->stats;
1173 }
1174
ns83820_ethtool_ioctl(struct ns83820 * dev,void * useraddr)1175 static int ns83820_ethtool_ioctl (struct ns83820 *dev, void *useraddr)
1176 {
1177 u32 ethcmd;
1178
1179 if (copy_from_user(ðcmd, useraddr, sizeof (ethcmd)))
1180 return -EFAULT;
1181
1182 switch (ethcmd) {
1183 case ETHTOOL_GDRVINFO:
1184 {
1185 struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO };
1186 strcpy(info.driver, "ns83820");
1187 strcpy(info.version, VERSION);
1188 strcpy(info.bus_info, dev->pci_dev->slot_name);
1189 if (copy_to_user(useraddr, &info, sizeof (info)))
1190 return -EFAULT;
1191 return 0;
1192 }
1193
1194 /* get link status */
1195 case ETHTOOL_GLINK: {
1196 struct ethtool_value edata = { ETHTOOL_GLINK };
1197 u32 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1198
1199 if (cfg & CFG_LNKSTS)
1200 edata.data = 1;
1201 else
1202 edata.data = 0;
1203 if (copy_to_user(useraddr, &edata, sizeof(edata)))
1204 return -EFAULT;
1205 return 0;
1206 }
1207
1208 default:
1209 break;
1210 }
1211
1212 return -EOPNOTSUPP;
1213 }
1214
ns83820_ioctl(struct net_device * _dev,struct ifreq * rq,int cmd)1215 static int ns83820_ioctl(struct net_device *_dev, struct ifreq *rq, int cmd)
1216 {
1217 struct ns83820 *dev = (struct ns83820 *)_dev;
1218
1219 switch(cmd) {
1220 case SIOCETHTOOL:
1221 return ns83820_ethtool_ioctl(dev, (void *) rq->ifr_data);
1222
1223 default:
1224 return -EOPNOTSUPP;
1225 }
1226 }
1227
ns83820_mib_isr(struct ns83820 * dev)1228 static void ns83820_mib_isr(struct ns83820 *dev)
1229 {
1230 spin_lock(&dev->misc_lock);
1231 ns83820_update_stats(dev);
1232 spin_unlock(&dev->misc_lock);
1233 }
1234
1235 static void ns83820_do_isr(struct ns83820 *dev, u32 isr);
ns83820_irq(int foo,void * data,struct pt_regs * regs)1236 static void ns83820_irq(int foo, void *data, struct pt_regs *regs)
1237 {
1238 struct ns83820 *dev = data;
1239 u32 isr;
1240 dprintk("ns83820_irq(%p)\n", dev);
1241
1242 dev->ihr = 0;
1243
1244 isr = readl(dev->base + ISR);
1245 dprintk("irq: %08x\n", isr);
1246 ns83820_do_isr(dev, isr);
1247 }
1248
ns83820_do_isr(struct ns83820 * dev,u32 isr)1249 static void ns83820_do_isr(struct ns83820 *dev, u32 isr)
1250 {
1251 #ifdef DEBUG
1252 if (isr & ~(ISR_PHY | ISR_RXDESC | ISR_RXEARLY | ISR_RXOK | ISR_RXERR | ISR_TXIDLE | ISR_TXOK | ISR_TXDESC))
1253 Dprintk("odd isr? 0x%08x\n", isr);
1254 #endif
1255
1256 if (ISR_RXIDLE & isr) {
1257 dev->rx_info.idle = 1;
1258 Dprintk("oh dear, we are idle\n");
1259 ns83820_rx_kick(dev);
1260 }
1261
1262 if ((ISR_RXDESC | ISR_RXOK) & isr) {
1263 prefetch(dev->rx_info.next_rx_desc);
1264
1265 spin_lock_irq(&dev->misc_lock);
1266 dev->IMR_cache &= ~(ISR_RXDESC | ISR_RXOK);
1267 writel(dev->IMR_cache, dev->base + IMR);
1268 spin_unlock_irq(&dev->misc_lock);
1269
1270 tasklet_schedule(&dev->rx_tasklet);
1271 //rx_irq(dev);
1272 //writel(4, dev->base + IHR);
1273 }
1274
1275 if ((ISR_RXIDLE | ISR_RXORN | ISR_RXDESC | ISR_RXOK | ISR_RXERR) & isr)
1276 ns83820_rx_kick(dev);
1277
1278 if (unlikely(ISR_RXSOVR & isr)) {
1279 //printk("overrun: rxsovr\n");
1280 dev->stats.rx_fifo_errors ++;
1281 }
1282
1283 if (unlikely(ISR_RXORN & isr)) {
1284 //printk("overrun: rxorn\n");
1285 dev->stats.rx_fifo_errors ++;
1286 }
1287
1288 if ((ISR_RXRCMP & isr) && dev->rx_info.up)
1289 writel(CR_RXE, dev->base + CR);
1290
1291 if (ISR_TXIDLE & isr) {
1292 u32 txdp;
1293 txdp = readl(dev->base + TXDP);
1294 dprintk("txdp: %08x\n", txdp);
1295 txdp -= dev->tx_phy_descs;
1296 dev->tx_idx = txdp / (DESC_SIZE * 4);
1297 if (dev->tx_idx >= NR_TX_DESC) {
1298 printk(KERN_ALERT "%s: BUG -- txdp out of range\n", dev->net_dev.name);
1299 dev->tx_idx = 0;
1300 }
1301 /* The may have been a race between a pci originated read
1302 * and the descriptor update from the cpu. Just in case,
1303 * kick the transmitter if the hardware thinks it is on a
1304 * different descriptor than we are.
1305 */
1306 if (dev->tx_idx != dev->tx_free_idx)
1307 kick_tx(dev);
1308 }
1309
1310 /* Defer tx ring processing until more than a minimum amount of
1311 * work has accumulated
1312 */
1313 if ((ISR_TXDESC | ISR_TXIDLE | ISR_TXOK | ISR_TXERR) & isr) {
1314 do_tx_done(dev);
1315
1316 /* Disable TxOk if there are no outstanding tx packets.
1317 */
1318 if ((dev->tx_done_idx == dev->tx_free_idx) &&
1319 (dev->IMR_cache & ISR_TXOK)) {
1320 spin_lock_irq(&dev->misc_lock);
1321 dev->IMR_cache &= ~ISR_TXOK;
1322 writel(dev->IMR_cache, dev->base + IMR);
1323 spin_unlock_irq(&dev->misc_lock);
1324 }
1325 }
1326
1327 /* The TxIdle interrupt can come in before the transmit has
1328 * completed. Normally we reap packets off of the combination
1329 * of TxDesc and TxIdle and leave TxOk disabled (since it
1330 * occurs on every packet), but when no further irqs of this
1331 * nature are expected, we must enable TxOk.
1332 */
1333 if ((ISR_TXIDLE & isr) && (dev->tx_done_idx != dev->tx_free_idx)) {
1334 spin_lock_irq(&dev->misc_lock);
1335 dev->IMR_cache |= ISR_TXOK;
1336 writel(dev->IMR_cache, dev->base + IMR);
1337 spin_unlock_irq(&dev->misc_lock);
1338 }
1339
1340 /* MIB interrupt: one of the statistics counters is about to overflow */
1341 if (unlikely(ISR_MIB & isr))
1342 ns83820_mib_isr(dev);
1343
1344 /* PHY: Link up/down/negotiation state change */
1345 if (unlikely(ISR_PHY & isr))
1346 phy_intr(dev);
1347
1348 #if 0 /* Still working on the interrupt mitigation strategy */
1349 if (dev->ihr)
1350 writel(dev->ihr, dev->base + IHR);
1351 #endif
1352 }
1353
ns83820_do_reset(struct ns83820 * dev,u32 which)1354 static void ns83820_do_reset(struct ns83820 *dev, u32 which)
1355 {
1356 Dprintk("resetting chip...\n");
1357 writel(which, dev->base + CR);
1358 do {
1359 schedule();
1360 } while (readl(dev->base + CR) & which);
1361 Dprintk("okay!\n");
1362 }
1363
ns83820_stop(struct net_device * _dev)1364 static int ns83820_stop(struct net_device *_dev)
1365 {
1366 struct ns83820 *dev = (struct ns83820 *)_dev;
1367
1368 /* FIXME: protect against interrupt handler? */
1369 del_timer_sync(&dev->tx_watchdog);
1370
1371 /* disable interrupts */
1372 writel(0, dev->base + IMR);
1373 writel(0, dev->base + IER);
1374 readl(dev->base + IER);
1375
1376 dev->rx_info.up = 0;
1377 synchronize_irq();
1378
1379 ns83820_do_reset(dev, CR_RST);
1380
1381 synchronize_irq();
1382
1383 spin_lock_irq(&dev->misc_lock);
1384 dev->IMR_cache &= ~(ISR_TXURN | ISR_TXIDLE | ISR_TXERR | ISR_TXDESC | ISR_TXOK);
1385 spin_unlock_irq(&dev->misc_lock);
1386
1387 ns83820_cleanup_rx(dev);
1388 ns83820_cleanup_tx(dev);
1389
1390 return 0;
1391 }
1392
1393 static void ns83820_do_isr(struct ns83820 *dev, u32 isr);
ns83820_tx_timeout(struct net_device * _dev)1394 static void ns83820_tx_timeout(struct net_device *_dev)
1395 {
1396 struct ns83820 *dev = (struct ns83820 *)_dev;
1397 u32 tx_done_idx, *desc;
1398 long flags;
1399
1400 __save_flags(flags);
1401 __cli();
1402
1403 tx_done_idx = dev->tx_done_idx;
1404 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1405
1406 printk(KERN_INFO "%s: tx_timeout: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1407 dev->net_dev.name,
1408 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1409
1410 #if defined(DEBUG)
1411 {
1412 u32 isr;
1413 isr = readl(dev->base + ISR);
1414 printk("irq: %08x imr: %08x\n", isr, dev->IMR_cache);
1415 ns83820_do_isr(dev, isr);
1416 }
1417 #endif
1418
1419 do_tx_done(dev);
1420
1421 tx_done_idx = dev->tx_done_idx;
1422 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1423
1424 printk(KERN_INFO "%s: after: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1425 dev->net_dev.name,
1426 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1427
1428 __restore_flags(flags);
1429 }
1430
ns83820_tx_watch(unsigned long data)1431 static void ns83820_tx_watch(unsigned long data)
1432 {
1433 struct ns83820 *dev = (void *)data;
1434
1435 #if defined(DEBUG)
1436 printk("ns83820_tx_watch: %u %u %d\n",
1437 dev->tx_done_idx, dev->tx_free_idx, atomic_read(&dev->nr_tx_skbs)
1438 );
1439 #endif
1440
1441 if (time_after(jiffies, dev->net_dev.trans_start + 1*HZ) &&
1442 dev->tx_done_idx != dev->tx_free_idx) {
1443 printk(KERN_DEBUG "%s: ns83820_tx_watch: %u %u %d\n",
1444 dev->net_dev.name,
1445 dev->tx_done_idx, dev->tx_free_idx,
1446 atomic_read(&dev->nr_tx_skbs));
1447 ns83820_tx_timeout(&dev->net_dev);
1448 }
1449
1450 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1451 }
1452
ns83820_open(struct net_device * _dev)1453 static int ns83820_open(struct net_device *_dev)
1454 {
1455 struct ns83820 *dev = (struct ns83820 *)_dev;
1456 unsigned i;
1457 u32 desc;
1458 int ret;
1459
1460 dprintk("ns83820_open\n");
1461
1462 writel(0, dev->base + PQCR);
1463
1464 ret = ns83820_setup_rx(dev);
1465 if (ret)
1466 goto failed;
1467
1468 memset(dev->tx_descs, 0, 4 * NR_TX_DESC * DESC_SIZE);
1469 for (i=0; i<NR_TX_DESC; i++) {
1470 dev->tx_descs[(i * DESC_SIZE) + DESC_LINK]
1471 = cpu_to_le32(
1472 dev->tx_phy_descs
1473 + ((i+1) % NR_TX_DESC) * DESC_SIZE * 4);
1474 }
1475
1476 dev->tx_idx = 0;
1477 dev->tx_done_idx = 0;
1478 desc = dev->tx_phy_descs;
1479 writel(0, dev->base + TXDP_HI);
1480 writel(desc, dev->base + TXDP);
1481
1482 init_timer(&dev->tx_watchdog);
1483 dev->tx_watchdog.data = (unsigned long)dev;
1484 dev->tx_watchdog.function = ns83820_tx_watch;
1485 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1486
1487 netif_start_queue(&dev->net_dev); /* FIXME: wait for phy to come up */
1488
1489 return 0;
1490
1491 failed:
1492 ns83820_stop(_dev);
1493 return ret;
1494 }
1495
ns83820_getmac(struct ns83820 * dev,u8 * mac)1496 static void ns83820_getmac(struct ns83820 *dev, u8 *mac)
1497 {
1498 unsigned i;
1499 for (i=0; i<3; i++) {
1500 u32 data;
1501 #if 0 /* I've left this in as an example of how to use eeprom.h */
1502 data = eeprom_readw(&dev->ee, 0xa + 2 - i);
1503 #else
1504 /* Read from the perfect match memory: this is loaded by
1505 * the chip from the EEPROM via the EELOAD self test.
1506 */
1507 writel(i*2, dev->base + RFCR);
1508 data = readl(dev->base + RFDR);
1509 #endif
1510 *mac++ = data;
1511 *mac++ = data >> 8;
1512 }
1513 }
1514
ns83820_change_mtu(struct net_device * _dev,int new_mtu)1515 static int ns83820_change_mtu(struct net_device *_dev, int new_mtu)
1516 {
1517 if (new_mtu > RX_BUF_SIZE)
1518 return -EINVAL;
1519 _dev->mtu = new_mtu;
1520 return 0;
1521 }
1522
ns83820_set_multicast(struct net_device * _dev)1523 static void ns83820_set_multicast(struct net_device *_dev)
1524 {
1525 struct ns83820 *dev = (void *)_dev;
1526 u8 *rfcr = dev->base + RFCR;
1527 u32 and_mask = 0xffffffff;
1528 u32 or_mask = 0;
1529 u32 val;
1530
1531 if (dev->net_dev.flags & IFF_PROMISC)
1532 or_mask |= RFCR_AAU | RFCR_AAM;
1533 else
1534 and_mask &= ~(RFCR_AAU | RFCR_AAM);
1535
1536 if (dev->net_dev.flags & IFF_ALLMULTI)
1537 or_mask |= RFCR_AAM;
1538 else
1539 and_mask &= ~RFCR_AAM;
1540
1541 spin_lock_irq(&dev->misc_lock);
1542 val = (readl(rfcr) & and_mask) | or_mask;
1543 /* Ramit : RFCR Write Fix doc says RFEN must be 0 modify other bits */
1544 writel(val & ~RFCR_RFEN, rfcr);
1545 writel(val, rfcr);
1546 spin_unlock_irq(&dev->misc_lock);
1547 }
1548
ns83820_run_bist(struct ns83820 * dev,const char * name,u32 enable,u32 done,u32 fail)1549 static void ns83820_run_bist(struct ns83820 *dev, const char *name, u32 enable, u32 done, u32 fail)
1550 {
1551 int timed_out = 0;
1552 long start;
1553 u32 status;
1554 int loops = 0;
1555
1556 dprintk("%s: start %s\n", dev->net_dev.name, name);
1557
1558 start = jiffies;
1559
1560 writel(enable, dev->base + PTSCR);
1561 for (;;) {
1562 loops++;
1563 status = readl(dev->base + PTSCR);
1564 if (!(status & enable))
1565 break;
1566 if (status & done)
1567 break;
1568 if (status & fail)
1569 break;
1570 if ((jiffies - start) >= HZ) {
1571 timed_out = 1;
1572 break;
1573 }
1574 set_current_state(TASK_UNINTERRUPTIBLE);
1575 schedule_timeout(1);
1576 }
1577
1578 if (status & fail)
1579 printk(KERN_INFO "%s: %s failed! (0x%08x & 0x%08x)\n",
1580 dev->net_dev.name, name, status, fail);
1581 else if (timed_out)
1582 printk(KERN_INFO "%s: run_bist %s timed out! (%08x)\n",
1583 dev->net_dev.name, name, status);
1584
1585 dprintk("%s: done %s in %d loops\n", dev->net_dev.name, name, loops);
1586 }
1587
1588 #ifdef PHY_CODE_IS_FINISHED
ns83820_mii_write_bit(struct ns83820 * dev,int bit)1589 static void ns83820_mii_write_bit(struct ns83820 *dev, int bit)
1590 {
1591 /* drive MDC low */
1592 dev->MEAR_cache &= ~MEAR_MDC;
1593 writel(dev->MEAR_cache, dev->base + MEAR);
1594 readl(dev->base + MEAR);
1595
1596 /* enable output, set bit */
1597 dev->MEAR_cache |= MEAR_MDDIR;
1598 if (bit)
1599 dev->MEAR_cache |= MEAR_MDIO;
1600 else
1601 dev->MEAR_cache &= ~MEAR_MDIO;
1602
1603 /* set the output bit */
1604 writel(dev->MEAR_cache, dev->base + MEAR);
1605 readl(dev->base + MEAR);
1606
1607 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1608 udelay(1);
1609
1610 /* drive MDC high causing the data bit to be latched */
1611 dev->MEAR_cache |= MEAR_MDC;
1612 writel(dev->MEAR_cache, dev->base + MEAR);
1613 readl(dev->base + MEAR);
1614
1615 /* Wait again... */
1616 udelay(1);
1617 }
1618
ns83820_mii_read_bit(struct ns83820 * dev)1619 static int ns83820_mii_read_bit(struct ns83820 *dev)
1620 {
1621 int bit;
1622
1623 /* drive MDC low, disable output */
1624 dev->MEAR_cache &= ~MEAR_MDC;
1625 dev->MEAR_cache &= ~MEAR_MDDIR;
1626 writel(dev->MEAR_cache, dev->base + MEAR);
1627 readl(dev->base + MEAR);
1628
1629 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1630 udelay(1);
1631
1632 /* drive MDC high causing the data bit to be latched */
1633 bit = (readl(dev->base + MEAR) & MEAR_MDIO) ? 1 : 0;
1634 dev->MEAR_cache |= MEAR_MDC;
1635 writel(dev->MEAR_cache, dev->base + MEAR);
1636
1637 /* Wait again... */
1638 udelay(1);
1639
1640 return bit;
1641 }
1642
ns83820_mii_read_reg(struct ns83820 * dev,unsigned phy,unsigned reg)1643 static unsigned ns83820_mii_read_reg(struct ns83820 *dev, unsigned phy, unsigned reg)
1644 {
1645 unsigned data = 0;
1646 int i;
1647
1648 /* read some garbage so that we eventually sync up */
1649 for (i=0; i<64; i++)
1650 ns83820_mii_read_bit(dev);
1651
1652 ns83820_mii_write_bit(dev, 0); /* start */
1653 ns83820_mii_write_bit(dev, 1);
1654 ns83820_mii_write_bit(dev, 1); /* opcode read */
1655 ns83820_mii_write_bit(dev, 0);
1656
1657 /* write out the phy address: 5 bits, msb first */
1658 for (i=0; i<5; i++)
1659 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1660
1661 /* write out the register address, 5 bits, msb first */
1662 for (i=0; i<5; i++)
1663 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1664
1665 ns83820_mii_read_bit(dev); /* turn around cycles */
1666 ns83820_mii_read_bit(dev);
1667
1668 /* read in the register data, 16 bits msb first */
1669 for (i=0; i<16; i++) {
1670 data <<= 1;
1671 data |= ns83820_mii_read_bit(dev);
1672 }
1673
1674 return data;
1675 }
1676
ns83820_mii_write_reg(struct ns83820 * dev,unsigned phy,unsigned reg,unsigned data)1677 static unsigned ns83820_mii_write_reg(struct ns83820 *dev, unsigned phy, unsigned reg, unsigned data)
1678 {
1679 int i;
1680
1681 /* read some garbage so that we eventually sync up */
1682 for (i=0; i<64; i++)
1683 ns83820_mii_read_bit(dev);
1684
1685 ns83820_mii_write_bit(dev, 0); /* start */
1686 ns83820_mii_write_bit(dev, 1);
1687 ns83820_mii_write_bit(dev, 0); /* opcode read */
1688 ns83820_mii_write_bit(dev, 1);
1689
1690 /* write out the phy address: 5 bits, msb first */
1691 for (i=0; i<5; i++)
1692 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1693
1694 /* write out the register address, 5 bits, msb first */
1695 for (i=0; i<5; i++)
1696 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1697
1698 ns83820_mii_read_bit(dev); /* turn around cycles */
1699 ns83820_mii_read_bit(dev);
1700
1701 /* read in the register data, 16 bits msb first */
1702 for (i=0; i<16; i++)
1703 ns83820_mii_write_bit(dev, (data >> (15 - i)) & 1);
1704
1705 return data;
1706 }
1707
ns83820_probe_phy(struct ns83820 * dev)1708 static void ns83820_probe_phy(struct ns83820 *dev)
1709 {
1710 static int first;
1711 int i;
1712 #define MII_PHYIDR1 0x02
1713 #define MII_PHYIDR2 0x03
1714
1715 #if 0
1716 if (!first) {
1717 unsigned tmp;
1718 ns83820_mii_read_reg(dev, 1, 0x09);
1719 ns83820_mii_write_reg(dev, 1, 0x10, 0x0d3e);
1720
1721 tmp = ns83820_mii_read_reg(dev, 1, 0x00);
1722 ns83820_mii_write_reg(dev, 1, 0x00, tmp | 0x8000);
1723 udelay(1300);
1724 ns83820_mii_read_reg(dev, 1, 0x09);
1725 }
1726 #endif
1727 first = 1;
1728
1729 for (i=1; i<2; i++) {
1730 int j;
1731 unsigned a, b;
1732 a = ns83820_mii_read_reg(dev, i, MII_PHYIDR1);
1733 b = ns83820_mii_read_reg(dev, i, MII_PHYIDR2);
1734
1735 //printk("%s: phy %d: 0x%04x 0x%04x\n",
1736 // dev->net_dev.name, i, a, b);
1737
1738 for (j=0; j<0x16; j+=4) {
1739 dprintk("%s: [0x%02x] %04x %04x %04x %04x\n",
1740 dev->net_dev.name, j,
1741 ns83820_mii_read_reg(dev, i, 0 + j),
1742 ns83820_mii_read_reg(dev, i, 1 + j),
1743 ns83820_mii_read_reg(dev, i, 2 + j),
1744 ns83820_mii_read_reg(dev, i, 3 + j)
1745 );
1746 }
1747 }
1748 {
1749 unsigned a, b;
1750 /* read firmware version: memory addr is 0x8402 and 0x8403 */
1751 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1752 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1753 a = ns83820_mii_read_reg(dev, 1, 0x1d);
1754
1755 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1756 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1757 b = ns83820_mii_read_reg(dev, 1, 0x1d);
1758 dprintk("version: 0x%04x 0x%04x\n", a, b);
1759 }
1760 }
1761 #endif
1762
ns83820_init_one(struct pci_dev * pci_dev,const struct pci_device_id * id)1763 static int __devinit ns83820_init_one(struct pci_dev *pci_dev, const struct pci_device_id *id)
1764 {
1765 struct ns83820 *dev;
1766 long addr;
1767 int err;
1768 int using_dac = 0;
1769
1770 /* See if we can set the dma mask early on; failure is fatal. */
1771 if (TRY_DAC && !pci_set_dma_mask(pci_dev, 0xffffffffffffffffULL)) {
1772 using_dac = 1;
1773 } else if (!pci_set_dma_mask(pci_dev, 0xffffffff)) {
1774 using_dac = 0;
1775 } else {
1776 printk(KERN_WARNING "ns83820.c: pci_set_dma_mask failed!\n");
1777 return -ENODEV;
1778 }
1779
1780 dev = (struct ns83820 *)alloc_etherdev((sizeof *dev) - (sizeof dev->net_dev));
1781 err = -ENOMEM;
1782 if (!dev)
1783 goto out;
1784
1785 spin_lock_init(&dev->rx_info.lock);
1786 spin_lock_init(&dev->tx_lock);
1787 spin_lock_init(&dev->misc_lock);
1788 dev->pci_dev = pci_dev;
1789
1790 dev->ee.cache = &dev->MEAR_cache;
1791 dev->ee.lock = &dev->misc_lock;
1792 dev->net_dev.owner = THIS_MODULE;
1793 dev->net_dev.priv = dev;
1794
1795 INIT_TQUEUE(&dev->tq_refill, queue_refill, dev);
1796 tasklet_init(&dev->rx_tasklet, rx_action, (unsigned long)dev);
1797
1798 err = pci_enable_device(pci_dev);
1799 if (err) {
1800 printk(KERN_INFO "ns83820: pci_enable_dev failed: %d\n", err);
1801 goto out_free;
1802 }
1803
1804 pci_set_master(pci_dev);
1805 addr = pci_resource_start(pci_dev, 1);
1806 dev->base = ioremap_nocache(addr, PAGE_SIZE);
1807 dev->tx_descs = pci_alloc_consistent(pci_dev,
1808 4 * DESC_SIZE * NR_TX_DESC, &dev->tx_phy_descs);
1809 dev->rx_info.descs = pci_alloc_consistent(pci_dev,
1810 4 * DESC_SIZE * NR_RX_DESC, &dev->rx_info.phy_descs);
1811 err = -ENOMEM;
1812 if (!dev->base || !dev->tx_descs || !dev->rx_info.descs)
1813 goto out_disable;
1814
1815 dprintk("%p: %08lx %p: %08lx\n",
1816 dev->tx_descs, (long)dev->tx_phy_descs,
1817 dev->rx_info.descs, (long)dev->rx_info.phy_descs);
1818
1819 /* disable interrupts */
1820 writel(0, dev->base + IMR);
1821 writel(0, dev->base + IER);
1822 readl(dev->base + IER);
1823
1824 dev->IMR_cache = 0;
1825
1826 setup_ee_mem_bitbanger(&dev->ee, (long)dev->base + MEAR, 3, 2, 1, 0,
1827 0);
1828
1829 err = request_irq(pci_dev->irq, ns83820_irq, SA_SHIRQ,
1830 dev->net_dev.name, dev);
1831 if (err) {
1832 printk(KERN_INFO "ns83820: unable to register irq %d\n",
1833 pci_dev->irq);
1834 goto out_unmap;
1835 }
1836
1837 err = register_netdev(&dev->net_dev);
1838 if (err) {
1839 printk(KERN_INFO "ns83820: unable to register netdev: %d\n", err);
1840 goto out_unmap;
1841 }
1842
1843 printk("%s: ns83820.c: 0x22c: %08x, subsystem: %04x:%04x\n",
1844 dev->net_dev.name, le32_to_cpu(readl(dev->base + 0x22c)),
1845 pci_dev->subsystem_vendor, pci_dev->subsystem_device);
1846
1847 dev->net_dev.open = ns83820_open;
1848 dev->net_dev.stop = ns83820_stop;
1849 dev->net_dev.hard_start_xmit = ns83820_hard_start_xmit;
1850 dev->net_dev.get_stats = ns83820_get_stats;
1851 dev->net_dev.change_mtu = ns83820_change_mtu;
1852 dev->net_dev.set_multicast_list = ns83820_set_multicast;
1853 dev->net_dev.do_ioctl = ns83820_ioctl;
1854 dev->net_dev.tx_timeout = ns83820_tx_timeout;
1855 dev->net_dev.watchdog_timeo = 5 * HZ;
1856
1857 pci_set_drvdata(pci_dev, dev);
1858
1859 ns83820_do_reset(dev, CR_RST);
1860
1861 /* Must reset the ram bist before running it */
1862 writel(PTSCR_RBIST_RST, dev->base + PTSCR);
1863 ns83820_run_bist(dev, "sram bist", PTSCR_RBIST_EN,
1864 PTSCR_RBIST_DONE, PTSCR_RBIST_FAIL);
1865 ns83820_run_bist(dev, "eeprom bist", PTSCR_EEBIST_EN, 0,
1866 PTSCR_EEBIST_FAIL);
1867 ns83820_run_bist(dev, "eeprom load", PTSCR_EELOAD_EN, 0, 0);
1868
1869 /* I love config registers */
1870 dev->CFG_cache = readl(dev->base + CFG);
1871
1872 if ((dev->CFG_cache & CFG_PCI64_DET)) {
1873 printk(KERN_INFO "%s: detected 64 bit PCI data bus.\n",
1874 dev->net_dev.name);
1875 /*dev->CFG_cache |= CFG_DATA64_EN;*/
1876 if (!(dev->CFG_cache & CFG_DATA64_EN))
1877 printk(KERN_INFO "%s: EEPROM did not enable 64 bit bus. Disabled.\n",
1878 dev->net_dev.name);
1879 } else
1880 dev->CFG_cache &= ~(CFG_DATA64_EN);
1881
1882 dev->CFG_cache &= (CFG_TBI_EN | CFG_MRM_DIS | CFG_MWI_DIS |
1883 CFG_T64ADDR | CFG_DATA64_EN | CFG_EXT_125 |
1884 CFG_M64ADDR);
1885 dev->CFG_cache |= CFG_PINT_DUPSTS | CFG_PINT_LNKSTS | CFG_PINT_SPDSTS |
1886 CFG_EXTSTS_EN | CFG_EXD | CFG_PESEL;
1887 dev->CFG_cache |= CFG_REQALG;
1888 dev->CFG_cache |= CFG_POW;
1889 dev->CFG_cache |= CFG_TMRTEST;
1890
1891 /* When compiled with 64 bit addressing, we must always enable
1892 * the 64 bit descriptor format.
1893 */
1894 #ifdef USE_64BIT_ADDR
1895 dev->CFG_cache |= CFG_M64ADDR;
1896 #endif
1897 if (using_dac)
1898 dev->CFG_cache |= CFG_T64ADDR;
1899
1900 /* Big endian mode does not seem to do what the docs suggest */
1901 dev->CFG_cache &= ~CFG_BEM;
1902
1903 /* setup optical transceiver if we have one */
1904 if (dev->CFG_cache & CFG_TBI_EN) {
1905 printk(KERN_INFO "%s: enabling optical transceiver\n",
1906 dev->net_dev.name);
1907 writel(readl(dev->base + GPIOR) | 0x3e8, dev->base + GPIOR);
1908
1909 /* setup auto negotiation feature advertisement */
1910 writel(readl(dev->base + TANAR)
1911 | TANAR_HALF_DUP | TANAR_FULL_DUP,
1912 dev->base + TANAR);
1913
1914 /* start auto negotiation */
1915 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
1916 dev->base + TBICR);
1917 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
1918 dev->linkstate = LINK_AUTONEGOTIATE;
1919
1920 dev->CFG_cache |= CFG_MODE_1000;
1921 }
1922
1923 writel(dev->CFG_cache, dev->base + CFG);
1924 dprintk("CFG: %08x\n", dev->CFG_cache);
1925
1926 if (reset_phy) {
1927 printk(KERN_INFO "%s: resetting phy\n", dev->net_dev.name);
1928 writel(dev->CFG_cache | CFG_PHY_RST, dev->base + CFG);
1929 set_current_state(TASK_UNINTERRUPTIBLE);
1930 schedule_timeout((HZ+99)/100);
1931 writel(dev->CFG_cache, dev->base + CFG);
1932 }
1933
1934 #if 0 /* Huh? This sets the PCI latency register. Should be done via
1935 * the PCI layer. FIXME.
1936 */
1937 if (readl(dev->base + SRR))
1938 writel(readl(dev->base+0x20c) | 0xfe00, dev->base + 0x20c);
1939 #endif
1940
1941 /* Note! The DMA burst size interacts with packet
1942 * transmission, such that the largest packet that
1943 * can be transmitted is 8192 - FLTH - burst size.
1944 * If only the transmit fifo was larger...
1945 */
1946 /* Ramit : 1024 DMA is not a good idea, it ends up banging
1947 * some DELL and COMPAQ SMP systems */
1948 writel(TXCFG_CSI | TXCFG_HBI | TXCFG_ATP | TXCFG_MXDMA512
1949 | ((1600 / 32) * 0x100),
1950 dev->base + TXCFG);
1951
1952 /* Flush the interrupt holdoff timer */
1953 writel(0x000, dev->base + IHR);
1954 writel(0x100, dev->base + IHR);
1955 writel(0x000, dev->base + IHR);
1956
1957 /* Set Rx to full duplex, don't accept runt, errored, long or length
1958 * range errored packets. Use 512 byte DMA.
1959 */
1960 /* Ramit : 1024 DMA is not a good idea, it ends up banging
1961 * some DELL and COMPAQ SMP systems
1962 * Turn on ALP, only we are accpeting Jumbo Packets */
1963 writel(RXCFG_AEP | RXCFG_ARP | RXCFG_AIRL | RXCFG_RX_FD
1964 | RXCFG_STRIPCRC
1965 //| RXCFG_ALP
1966 | (RXCFG_MXDMA512) | 0, dev->base + RXCFG);
1967
1968 /* Disable priority queueing */
1969 writel(0, dev->base + PQCR);
1970
1971 /* Enable IP checksum validation and detetion of VLAN headers.
1972 * Note: do not set the reject options as at least the 0x102
1973 * revision of the chip does not properly accept IP fragments
1974 * at least for UDP.
1975 */
1976 /* Ramit : Be sure to turn on RXCFG_ARP if VLAN's are enabled, since
1977 * the MAC it calculates the packetsize AFTER stripping the VLAN
1978 * header, and if a VLAN Tagged packet of 64 bytes is received (like
1979 * a ping with a VLAN header) then the card, strips the 4 byte VLAN
1980 * tag and then checks the packet size, so if RXCFG_ARP is not enabled,
1981 * it discrards it!. These guys......
1982 */
1983 writel(VRCR_IPEN | VRCR_VTDEN, dev->base + VRCR);
1984
1985 /* Enable per-packet TCP/UDP/IP checksumming */
1986 writel(VTCR_PPCHK, dev->base + VTCR);
1987
1988 /* Ramit : Enable async and sync pause frames */
1989 /* writel(0, dev->base + PCR); */
1990 writel((PCR_PS_MCAST | PCR_PS_DA | PCR_PSEN | PCR_FFLO_4K |
1991 PCR_FFHI_8K | PCR_STLO_4 | PCR_STHI_8 | PCR_PAUSE_CNT),
1992 dev->base + PCR);
1993
1994 /* Disable Wake On Lan */
1995 writel(0, dev->base + WCSR);
1996
1997 ns83820_getmac(dev, dev->net_dev.dev_addr);
1998
1999 /* Yes, we support dumb IP checksum on transmit */
2000 dev->net_dev.features |= NETIF_F_SG;
2001 dev->net_dev.features |= NETIF_F_IP_CSUM;
2002
2003 if (using_dac) {
2004 printk(KERN_INFO "%s: using 64 bit addressing.\n",
2005 dev->net_dev.name);
2006 dev->net_dev.features |= NETIF_F_HIGHDMA;
2007 }
2008
2009 printk(KERN_INFO "%s: ns83820 v" VERSION ": DP83820 v%u.%u: %02x:%02x:%02x:%02x:%02x:%02x io=0x%08lx irq=%d f=%s\n",
2010 dev->net_dev.name,
2011 (unsigned)readl(dev->base + SRR) >> 8,
2012 (unsigned)readl(dev->base + SRR) & 0xff,
2013 dev->net_dev.dev_addr[0], dev->net_dev.dev_addr[1],
2014 dev->net_dev.dev_addr[2], dev->net_dev.dev_addr[3],
2015 dev->net_dev.dev_addr[4], dev->net_dev.dev_addr[5],
2016 addr, pci_dev->irq,
2017 (dev->net_dev.features & NETIF_F_HIGHDMA) ? "h,sg" : "sg"
2018 );
2019
2020 #ifdef PHY_CODE_IS_FINISHED
2021 ns83820_probe_phy(dev);
2022 #endif
2023
2024 return 0;
2025
2026 out_unmap:
2027 iounmap(dev->base);
2028 out_disable:
2029 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_TX_DESC, dev->tx_descs, dev->tx_phy_descs);
2030 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_RX_DESC, dev->rx_info.descs, dev->rx_info.phy_descs);
2031 pci_disable_device(pci_dev);
2032 out_free:
2033 kfree(dev);
2034 pci_set_drvdata(pci_dev, NULL);
2035 out:
2036 return err;
2037 }
2038
ns83820_remove_one(struct pci_dev * pci_dev)2039 static void __devexit ns83820_remove_one(struct pci_dev *pci_dev)
2040 {
2041 struct ns83820 *dev = pci_get_drvdata(pci_dev);
2042
2043 if (!dev) /* paranoia */
2044 return;
2045
2046 writel(0, dev->base + IMR); /* paranoia */
2047 writel(0, dev->base + IER);
2048 readl(dev->base + IER);
2049
2050 unregister_netdev(&dev->net_dev);
2051 free_irq(dev->pci_dev->irq, dev);
2052 iounmap(dev->base);
2053 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_TX_DESC,
2054 dev->tx_descs, dev->tx_phy_descs);
2055 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_RX_DESC,
2056 dev->rx_info.descs, dev->rx_info.phy_descs);
2057 pci_disable_device(dev->pci_dev);
2058 kfree(dev);
2059 pci_set_drvdata(pci_dev, NULL);
2060 }
2061
2062 static struct pci_device_id ns83820_pci_tbl[] __devinitdata = {
2063 { 0x100b, 0x0022, PCI_ANY_ID, PCI_ANY_ID, 0, .driver_data = 0, },
2064 { 0, },
2065 };
2066
2067 static struct pci_driver driver = {
2068 name: "ns83820",
2069 id_table: ns83820_pci_tbl,
2070 probe: ns83820_init_one,
2071 remove: __devexit_p(ns83820_remove_one),
2072 #if 0 /* FIXME: implement */
2073 suspend: ,
2074 resume: ,
2075 #endif
2076 };
2077
2078
ns83820_init(void)2079 static int __init ns83820_init(void)
2080 {
2081 printk(KERN_INFO "ns83820.c: National Semiconductor DP83820 10/100/1000 driver.\n");
2082 return pci_module_init(&driver);
2083 }
2084
ns83820_exit(void)2085 static void __exit ns83820_exit(void)
2086 {
2087 pci_unregister_driver(&driver);
2088 }
2089
2090 MODULE_AUTHOR("Benjamin LaHaise <bcrl@redhat.com>");
2091 MODULE_DESCRIPTION("National Semiconductor DP83820 10/100/1000 driver");
2092 MODULE_LICENSE("GPL");
2093
2094 MODULE_DEVICE_TABLE(pci, ns83820_pci_tbl);
2095
2096 MODULE_PARM(lnksts, "i");
2097 MODULE_PARM_DESC(lnksts, "Polarity of LNKSTS bit");
2098
2099 MODULE_PARM(ihr, "i");
2100 MODULE_PARM_DESC(ihr, "Time in 100 us increments to delay interrupts (range 0-127)");
2101
2102 MODULE_PARM(reset_phy, "i");
2103 MODULE_PARM_DESC(reset_phy, "Set to 1 to reset the PHY on startup");
2104
2105 module_init(ns83820_init);
2106 module_exit(ns83820_exit);
2107