1 /*
2 *
3 * Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200 and G400
4 *
5 * (c) 1998-2002 Petr Vandrovec <vandrove@vc.cvut.cz>
6 *
7 * Portions Copyright (c) 2001 Matrox Graphics Inc.
8 *
9 * Version: 1.64 2002/06/10
10 *
11 * MTRR stuff: 1998 Tom Rini <trini@kernel.crashing.org>
12 *
13 * Contributors: "menion?" <menion@mindless.com>
14 * Betatesting, fixes, ideas
15 *
16 * "Kurt Garloff" <garloff@suse.de>
17 * Betatesting, fixes, ideas, videomodes, videomodes timmings
18 *
19 * "Tom Rini" <trini@kernel.crashing.org>
20 * MTRR stuff, PPC cleanups, betatesting, fixes, ideas
21 *
22 * "Bibek Sahu" <scorpio@dodds.net>
23 * Access device through readb|w|l and write b|w|l
24 * Extensive debugging stuff
25 *
26 * "Daniel Haun" <haund@usa.net>
27 * Testing, hardware cursor fixes
28 *
29 * "Scott Wood" <sawst46+@pitt.edu>
30 * Fixes
31 *
32 * "Gerd Knorr" <kraxel@goldbach.isdn.cs.tu-berlin.de>
33 * Betatesting
34 *
35 * "Kelly French" <targon@hazmat.com>
36 * "Fernando Herrera" <fherrera@eurielec.etsit.upm.es>
37 * Betatesting, bug reporting
38 *
39 * "Pablo Bianucci" <pbian@pccp.com.ar>
40 * Fixes, ideas, betatesting
41 *
42 * "Inaky Perez Gonzalez" <inaky@peloncho.fis.ucm.es>
43 * Fixes, enhandcements, ideas, betatesting
44 *
45 * "Ryuichi Oikawa" <roikawa@rr.iiij4u.or.jp>
46 * PPC betatesting, PPC support, backward compatibility
47 *
48 * "Paul Womar" <Paul@pwomar.demon.co.uk>
49 * "Owen Waller" <O.Waller@ee.qub.ac.uk>
50 * PPC betatesting
51 *
52 * "Thomas Pornin" <pornin@bolet.ens.fr>
53 * Alpha betatesting
54 *
55 * "Pieter van Leuven" <pvl@iae.nl>
56 * "Ulf Jaenicke-Roessler" <ujr@physik.phy.tu-dresden.de>
57 * G100 testing
58 *
59 * "H. Peter Arvin" <hpa@transmeta.com>
60 * Ideas
61 *
62 * "Cort Dougan" <cort@cs.nmt.edu>
63 * CHRP fixes and PReP cleanup
64 *
65 * "Mark Vojkovich" <mvojkovi@ucsd.edu>
66 * G400 support
67 *
68 * (following author is not in any relation with this code, but his code
69 * is included in this driver)
70 *
71 * Based on framebuffer driver for VBE 2.0 compliant graphic boards
72 * (c) 1998 Gerd Knorr <kraxel@cs.tu-berlin.de>
73 *
74 * (following author is not in any relation with this code, but his ideas
75 * were used when writting this driver)
76 *
77 * FreeVBE/AF (Matrox), "Shawn Hargreaves" <shawn@talula.demon.co.uk>
78 *
79 */
80
81 /* make checkconfig does not verify included files... */
82 #include <linux/config.h>
83
84 #include "matroxfb_Ti3026.h"
85 #include "matroxfb_misc.h"
86 #include "matroxfb_accel.h"
87 #include <linux/matroxfb.h>
88
89 #ifdef CONFIG_FB_MATROX_MILLENIUM
90 #define outTi3026 matroxfb_DAC_out
91 #define inTi3026 matroxfb_DAC_in
92
93 #define TVP3026_INDEX 0x00
94 #define TVP3026_PALWRADD 0x00
95 #define TVP3026_PALDATA 0x01
96 #define TVP3026_PIXRDMSK 0x02
97 #define TVP3026_PALRDADD 0x03
98 #define TVP3026_CURCOLWRADD 0x04
99 #define TVP3026_CLOVERSCAN 0x00
100 #define TVP3026_CLCOLOR0 0x01
101 #define TVP3026_CLCOLOR1 0x02
102 #define TVP3026_CLCOLOR2 0x03
103 #define TVP3026_CURCOLDATA 0x05
104 #define TVP3026_CURCOLRDADD 0x07
105 #define TVP3026_CURCTRL 0x09
106 #define TVP3026_X_DATAREG 0x0A
107 #define TVP3026_CURRAMDATA 0x0B
108 #define TVP3026_CURPOSXL 0x0C
109 #define TVP3026_CURPOSXH 0x0D
110 #define TVP3026_CURPOSYL 0x0E
111 #define TVP3026_CURPOSYH 0x0F
112
113 #define TVP3026_XSILICONREV 0x01
114 #define TVP3026_XCURCTRL 0x06
115 #define TVP3026_XCURCTRL_DIS 0x00 /* transparent, transparent, transparent, transparent */
116 #define TVP3026_XCURCTRL_3COLOR 0x01 /* transparent, 0, 1, 2 */
117 #define TVP3026_XCURCTRL_XGA 0x02 /* 0, 1, transparent, complement */
118 #define TVP3026_XCURCTRL_XWIN 0x03 /* transparent, transparent, 0, 1 */
119 #define TVP3026_XCURCTRL_BLANK2048 0x00
120 #define TVP3026_XCURCTRL_BLANK4096 0x10
121 #define TVP3026_XCURCTRL_INTERLACED 0x20
122 #define TVP3026_XCURCTRL_ODD 0x00 /* ext.signal ODD/\EVEN */
123 #define TVP3026_XCURCTRL_EVEN 0x40 /* ext.signal EVEN/\ODD */
124 #define TVP3026_XCURCTRL_INDIRECT 0x00
125 #define TVP3026_XCURCTRL_DIRECT 0x80
126 #define TVP3026_XLATCHCTRL 0x0F
127 #define TVP3026_XLATCHCTRL_1_1 0x06
128 #define TVP3026_XLATCHCTRL_2_1 0x07
129 #define TVP3026_XLATCHCTRL_4_1 0x06
130 #define TVP3026_XLATCHCTRL_8_1 0x06
131 #define TVP3026_XLATCHCTRL_16_1 0x06
132 #define TVP3026A_XLATCHCTRL_4_3 0x06 /* ??? do not understand... but it works... !!! */
133 #define TVP3026A_XLATCHCTRL_8_3 0x07
134 #define TVP3026B_XLATCHCTRL_4_3 0x08
135 #define TVP3026B_XLATCHCTRL_8_3 0x06 /* ??? do not understand... but it works... !!! */
136 #define TVP3026_XTRUECOLORCTRL 0x18
137 #define TVP3026_XTRUECOLORCTRL_VRAM_SHIFT_ACCEL 0x00
138 #define TVP3026_XTRUECOLORCTRL_VRAM_SHIFT_TVP 0x20
139 #define TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR 0x80
140 #define TVP3026_XTRUECOLORCTRL_TRUECOLOR 0x40 /* paletized */
141 #define TVP3026_XTRUECOLORCTRL_DIRECTCOLOR 0x00
142 #define TVP3026_XTRUECOLORCTRL_24_ALTERNATE 0x08 /* 5:4/5:2 instead of 4:3/8:3 */
143 #define TVP3026_XTRUECOLORCTRL_RGB_888 0x16 /* 4:3/8:3 (or 5:4/5:2) */
144 #define TVP3026_XTRUECOLORCTRL_BGR_888 0x17
145 #define TVP3026_XTRUECOLORCTRL_ORGB_8888 0x06
146 #define TVP3026_XTRUECOLORCTRL_BGRO_8888 0x07
147 #define TVP3026_XTRUECOLORCTRL_RGB_565 0x05
148 #define TVP3026_XTRUECOLORCTRL_ORGB_1555 0x04
149 #define TVP3026_XTRUECOLORCTRL_RGB_664 0x03
150 #define TVP3026_XTRUECOLORCTRL_RGBO_4444 0x01
151 #define TVP3026_XMUXCTRL 0x19
152 #define TVP3026_XMUXCTRL_MEMORY_8BIT 0x01 /* - */
153 #define TVP3026_XMUXCTRL_MEMORY_16BIT 0x02 /* - */
154 #define TVP3026_XMUXCTRL_MEMORY_32BIT 0x03 /* 2MB RAM, 512K * 4 */
155 #define TVP3026_XMUXCTRL_MEMORY_64BIT 0x04 /* >2MB RAM, 512K * 8 & more */
156 #define TVP3026_XMUXCTRL_PIXEL_4BIT 0x40 /* L0,H0,L1,H1... */
157 #define TVP3026_XMUXCTRL_PIXEL_4BIT_SWAPPED 0x60 /* H0,L0,H1,L1... */
158 #define TVP3026_XMUXCTRL_PIXEL_8BIT 0x48
159 #define TVP3026_XMUXCTRL_PIXEL_16BIT 0x50
160 #define TVP3026_XMUXCTRL_PIXEL_32BIT 0x58
161 #define TVP3026_XMUXCTRL_VGA 0x98 /* VGA MEMORY, 8BIT PIXEL */
162 #define TVP3026_XCLKCTRL 0x1A
163 #define TVP3026_XCLKCTRL_DIV1 0x00
164 #define TVP3026_XCLKCTRL_DIV2 0x10
165 #define TVP3026_XCLKCTRL_DIV4 0x20
166 #define TVP3026_XCLKCTRL_DIV8 0x30
167 #define TVP3026_XCLKCTRL_DIV16 0x40
168 #define TVP3026_XCLKCTRL_DIV32 0x50
169 #define TVP3026_XCLKCTRL_DIV64 0x60
170 #define TVP3026_XCLKCTRL_CLKSTOPPED 0x70
171 #define TVP3026_XCLKCTRL_SRC_CLK0 0x00
172 #define TVP3026_XCLKCTRL_SRC_CLK1 0x01
173 #define TVP3026_XCLKCTRL_SRC_CLK2 0x02 /* CLK2 is TTL source*/
174 #define TVP3026_XCLKCTRL_SRC_NCLK2 0x03 /* not CLK2 is TTL source */
175 #define TVP3026_XCLKCTRL_SRC_ECLK2 0x04 /* CLK2 and not CLK2 is ECL source */
176 #define TVP3026_XCLKCTRL_SRC_PLL 0x05
177 #define TVP3026_XCLKCTRL_SRC_DIS 0x06 /* disable & poweroff internal clock */
178 #define TVP3026_XCLKCTRL_SRC_CLK0VGA 0x07
179 #define TVP3026_XPALETTEPAGE 0x1C
180 #define TVP3026_XGENCTRL 0x1D
181 #define TVP3026_XGENCTRL_HSYNC_POS 0x00
182 #define TVP3026_XGENCTRL_HSYNC_NEG 0x01
183 #define TVP3026_XGENCTRL_VSYNC_POS 0x00
184 #define TVP3026_XGENCTRL_VSYNC_NEG 0x02
185 #define TVP3026_XGENCTRL_LITTLE_ENDIAN 0x00
186 #define TVP3026_XGENCTRL_BIG_ENDIAN 0x08
187 #define TVP3026_XGENCTRL_BLACK_0IRE 0x00
188 #define TVP3026_XGENCTRL_BLACK_75IRE 0x10
189 #define TVP3026_XGENCTRL_NO_SYNC_ON_GREEN 0x00
190 #define TVP3026_XGENCTRL_SYNC_ON_GREEN 0x20
191 #define TVP3026_XGENCTRL_OVERSCAN_DIS 0x00
192 #define TVP3026_XGENCTRL_OVERSCAN_EN 0x40
193 #define TVP3026_XMISCCTRL 0x1E
194 #define TVP3026_XMISCCTRL_DAC_PUP 0x00
195 #define TVP3026_XMISCCTRL_DAC_PDOWN 0x01
196 #define TVP3026_XMISCCTRL_DAC_EXT 0x00 /* or 8, bit 3 is ignored */
197 #define TVP3026_XMISCCTRL_DAC_6BIT 0x04
198 #define TVP3026_XMISCCTRL_DAC_8BIT 0x0C
199 #define TVP3026_XMISCCTRL_PSEL_DIS 0x00
200 #define TVP3026_XMISCCTRL_PSEL_EN 0x10
201 #define TVP3026_XMISCCTRL_PSEL_LOW 0x00 /* PSEL high selects directcolor */
202 #define TVP3026_XMISCCTRL_PSEL_HIGH 0x20 /* PSEL high selects truecolor or pseudocolor */
203 #define TVP3026_XGENIOCTRL 0x2A
204 #define TVP3026_XGENIODATA 0x2B
205 #define TVP3026_XPLLADDR 0x2C
206 #define TVP3026_XPLLADDR_X(LOOP,MCLK,PIX) (((LOOP)<<4) | ((MCLK)<<2) | (PIX))
207 #define TVP3026_XPLLDATA_N 0x00
208 #define TVP3026_XPLLDATA_M 0x01
209 #define TVP3026_XPLLDATA_P 0x02
210 #define TVP3026_XPLLDATA_STAT 0x03
211 #define TVP3026_XPIXPLLDATA 0x2D
212 #define TVP3026_XMEMPLLDATA 0x2E
213 #define TVP3026_XLOOPPLLDATA 0x2F
214 #define TVP3026_XCOLKEYOVRMIN 0x30
215 #define TVP3026_XCOLKEYOVRMAX 0x31
216 #define TVP3026_XCOLKEYREDMIN 0x32
217 #define TVP3026_XCOLKEYREDMAX 0x33
218 #define TVP3026_XCOLKEYGREENMIN 0x34
219 #define TVP3026_XCOLKEYGREENMAX 0x35
220 #define TVP3026_XCOLKEYBLUEMIN 0x36
221 #define TVP3026_XCOLKEYBLUEMAX 0x37
222 #define TVP3026_XCOLKEYCTRL 0x38
223 #define TVP3026_XCOLKEYCTRL_OVR_EN 0x01
224 #define TVP3026_XCOLKEYCTRL_RED_EN 0x02
225 #define TVP3026_XCOLKEYCTRL_GREEN_EN 0x04
226 #define TVP3026_XCOLKEYCTRL_BLUE_EN 0x08
227 #define TVP3026_XCOLKEYCTRL_NEGATE 0x10
228 #define TVP3026_XCOLKEYCTRL_ZOOM1 0x00
229 #define TVP3026_XCOLKEYCTRL_ZOOM2 0x20
230 #define TVP3026_XCOLKEYCTRL_ZOOM4 0x40
231 #define TVP3026_XCOLKEYCTRL_ZOOM8 0x60
232 #define TVP3026_XCOLKEYCTRL_ZOOM16 0x80
233 #define TVP3026_XCOLKEYCTRL_ZOOM32 0xA0
234 #define TVP3026_XMEMPLLCTRL 0x39
235 #define TVP3026_XMEMPLLCTRL_DIV(X) (((X)-1)>>1) /* 2,4,6,8,10,12,14,16, division applied to LOOP PLL after divide by 2^P */
236 #define TVP3026_XMEMPLLCTRL_STROBEMKC4 0x08
237 #define TVP3026_XMEMPLLCTRL_MCLK_DOTCLOCK 0x00 /* MKC4 */
238 #define TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL 0x10 /* MKC4 */
239 #define TVP3026_XMEMPLLCTRL_RCLK_PIXPLL 0x00
240 #define TVP3026_XMEMPLLCTRL_RCLK_LOOPPLL 0x20
241 #define TVP3026_XMEMPLLCTRL_RCLK_DOTDIVN 0x40 /* dot clock divided by loop pclk N prescaler */
242 #define TVP3026_XSENSETEST 0x3A
243 #define TVP3026_XTESTMODEDATA 0x3B
244 #define TVP3026_XCRCREML 0x3C
245 #define TVP3026_XCRCREMH 0x3D
246 #define TVP3026_XCRCBITSEL 0x3E
247 #define TVP3026_XID 0x3F
248
249 static const unsigned char DACseq[] =
250 { TVP3026_XLATCHCTRL, TVP3026_XTRUECOLORCTRL,
251 TVP3026_XMUXCTRL, TVP3026_XCLKCTRL,
252 TVP3026_XPALETTEPAGE,
253 TVP3026_XGENCTRL,
254 TVP3026_XMISCCTRL,
255 TVP3026_XGENIOCTRL,
256 TVP3026_XGENIODATA,
257 TVP3026_XCOLKEYOVRMIN, TVP3026_XCOLKEYOVRMAX, TVP3026_XCOLKEYREDMIN, TVP3026_XCOLKEYREDMAX,
258 TVP3026_XCOLKEYGREENMIN, TVP3026_XCOLKEYGREENMAX, TVP3026_XCOLKEYBLUEMIN, TVP3026_XCOLKEYBLUEMAX,
259 TVP3026_XCOLKEYCTRL,
260 TVP3026_XMEMPLLCTRL, TVP3026_XSENSETEST, TVP3026_XCURCTRL };
261
262 #define POS3026_XLATCHCTRL 0
263 #define POS3026_XTRUECOLORCTRL 1
264 #define POS3026_XMUXCTRL 2
265 #define POS3026_XCLKCTRL 3
266 #define POS3026_XGENCTRL 5
267 #define POS3026_XMISCCTRL 6
268 #define POS3026_XMEMPLLCTRL 18
269 #define POS3026_XCURCTRL 20
270
271 static const unsigned char MGADACbpp32[] =
272 { TVP3026_XLATCHCTRL_2_1, TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_ORGB_8888,
273 0x00, TVP3026_XCLKCTRL_DIV1 | TVP3026_XCLKCTRL_SRC_PLL,
274 0x00,
275 TVP3026_XGENCTRL_HSYNC_POS | TVP3026_XGENCTRL_VSYNC_POS | TVP3026_XGENCTRL_LITTLE_ENDIAN | TVP3026_XGENCTRL_BLACK_0IRE | TVP3026_XGENCTRL_NO_SYNC_ON_GREEN | TVP3026_XGENCTRL_OVERSCAN_DIS,
276 TVP3026_XMISCCTRL_DAC_PUP | TVP3026_XMISCCTRL_DAC_8BIT | TVP3026_XMISCCTRL_PSEL_DIS | TVP3026_XMISCCTRL_PSEL_HIGH,
277 0x00,
278 0x1E,
279 0xFF, 0xFF, 0xFF, 0xFF,
280 0xFF, 0xFF, 0xFF, 0xFF,
281 TVP3026_XCOLKEYCTRL_ZOOM1,
282 0x00, 0x00, TVP3026_XCURCTRL_DIS };
283
matroxfb_ti3026_flashcursor(unsigned long ptr)284 static void matroxfb_ti3026_flashcursor(unsigned long ptr) {
285 unsigned long flags;
286
287 #define minfo ((struct matrox_fb_info*)ptr)
288 matroxfb_DAC_lock_irqsave(flags);
289 outTi3026(PMINFO TVP3026_XCURCTRL, inTi3026(PMINFO TVP3026_XCURCTRL) ^ TVP3026_XCURCTRL_DIS ^ TVP3026_XCURCTRL_XGA);
290 ACCESS_FBINFO(cursor.timer.expires) = jiffies + HZ/2;
291 add_timer(&ACCESS_FBINFO(cursor.timer));
292 matroxfb_DAC_unlock_irqrestore(flags);
293 #undef minfo
294 }
295
matroxfb_ti3026_createcursor(WPMINFO struct display * p)296 static void matroxfb_ti3026_createcursor(WPMINFO struct display* p) {
297 unsigned long flags;
298 u_int32_t xline;
299 unsigned int i;
300 unsigned int to;
301
302 if (ACCESS_FBINFO(currcon_display) != p)
303 return;
304
305 DBG("matroxfb_ti3026_createcursor");
306
307 matroxfb_createcursorshape(PMINFO p, p->var.vmode);
308
309 xline = (~0) << (32 - ACCESS_FBINFO(cursor.w));
310 matroxfb_DAC_lock_irqsave(flags);
311 mga_outb(M_RAMDAC_BASE+TVP3026_INDEX, 0);
312 to = ACCESS_FBINFO(cursor.u);
313 for (i = 0; i < to; i++) {
314 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
315 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
316 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
317 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
318 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
319 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
320 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
321 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
322 }
323 to = ACCESS_FBINFO(cursor.d);
324 for (; i < to; i++) {
325 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, xline >> 24);
326 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, xline >> 16);
327 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, xline >> 8);
328 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, xline);
329 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
330 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
331 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
332 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
333 }
334 for (; i < 64; i++) {
335 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
336 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
337 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
338 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
339 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
340 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
341 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
342 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0);
343 }
344 for (i = 0; i < 512; i++)
345 mga_outb(M_RAMDAC_BASE+TVP3026_CURRAMDATA, 0xFF);
346 matroxfb_DAC_unlock_irqrestore(flags);
347 }
348
matroxfb_ti3026_cursor(struct display * p,int mode,int x,int y)349 static void matroxfb_ti3026_cursor(struct display* p, int mode, int x, int y) {
350 unsigned long flags;
351 MINFO_FROM_DISP(p);
352
353 DBG("matroxfb_ti3026_cursor")
354
355 if (ACCESS_FBINFO(currcon_display) != p)
356 return;
357
358 if (mode == CM_ERASE) {
359 if (ACCESS_FBINFO(cursor.state) != CM_ERASE) {
360 del_timer_sync(&ACCESS_FBINFO(cursor.timer));
361 matroxfb_DAC_lock_irqsave(flags);
362 ACCESS_FBINFO(cursor.state) = CM_ERASE;
363 outTi3026(PMINFO TVP3026_XCURCTRL, ACCESS_FBINFO(hw.DACreg[POS3026_XCURCTRL]));
364 matroxfb_DAC_unlock_irqrestore(flags);
365 }
366 return;
367 }
368 if ((p->conp->vc_cursor_type & CUR_HWMASK) != ACCESS_FBINFO(cursor.type))
369 matroxfb_ti3026_createcursor(PMINFO p);
370 x *= fontwidth(p);
371 y *= fontheight(p);
372 y -= p->var.yoffset;
373 if (p->var.vmode & FB_VMODE_DOUBLE)
374 y *= 2;
375 del_timer_sync(&ACCESS_FBINFO(cursor.timer));
376 matroxfb_DAC_lock_irqsave(flags);
377 if ((x != ACCESS_FBINFO(cursor.x)) || (y != ACCESS_FBINFO(cursor.y)) || ACCESS_FBINFO(cursor.redraw)) {
378 ACCESS_FBINFO(cursor.redraw) = 0;
379 ACCESS_FBINFO(cursor.x) = x;
380 ACCESS_FBINFO(cursor.y) = y;
381 x += 64;
382 y += 64;
383 outTi3026(PMINFO TVP3026_XCURCTRL, ACCESS_FBINFO(hw.DACreg[POS3026_XCURCTRL]));
384 mga_outb(M_RAMDAC_BASE+TVP3026_CURPOSXL, x);
385 mga_outb(M_RAMDAC_BASE+TVP3026_CURPOSXH, x >> 8);
386 mga_outb(M_RAMDAC_BASE+TVP3026_CURPOSYL, y);
387 mga_outb(M_RAMDAC_BASE+TVP3026_CURPOSYH, y >> 8);
388 }
389 ACCESS_FBINFO(cursor.state) = CM_DRAW;
390 if (ACCESS_FBINFO(devflags.blink))
391 mod_timer(&ACCESS_FBINFO(cursor.timer), jiffies + HZ/2);
392 outTi3026(PMINFO TVP3026_XCURCTRL, ACCESS_FBINFO(hw.DACreg[POS3026_XCURCTRL]) | TVP3026_XCURCTRL_XGA);
393 matroxfb_DAC_unlock_irqrestore(flags);
394 }
395
matroxfb_ti3026_setfont(struct display * p,int width,int height)396 static int matroxfb_ti3026_setfont(struct display* p, int width, int height) {
397
398 DBG("matrox_ti3026_setfont");
399
400 if (p && p->conp)
401 matroxfb_ti3026_createcursor(PMXINFO(p) p);
402 return 0;
403 }
404
matroxfb_ti3026_selhwcursor(WPMINFO struct display * p)405 static int matroxfb_ti3026_selhwcursor(WPMINFO struct display* p) {
406 ACCESS_FBINFO(dispsw.cursor) = matroxfb_ti3026_cursor;
407 ACCESS_FBINFO(dispsw.set_font) = matroxfb_ti3026_setfont;
408 return 0;
409 }
410
Ti3026_calcclock(CPMINFO unsigned int freq,unsigned int fmax,int * in,int * feed,int * post)411 static int Ti3026_calcclock(CPMINFO unsigned int freq, unsigned int fmax, int* in, int* feed, int* post) {
412 unsigned int fvco;
413 unsigned int lin, lfeed, lpost;
414
415 DBG("Ti3026_calcclock")
416
417 fvco = PLL_calcclock(PMINFO freq, fmax, &lin, &lfeed, &lpost);
418 fvco >>= (*post = lpost);
419 *in = 64 - lin;
420 *feed = 64 - lfeed;
421 return fvco;
422 }
423
Ti3026_setpclk(WPMINFO int clk,struct display * p)424 static int Ti3026_setpclk(WPMINFO int clk, struct display* p) {
425 unsigned int f_pll;
426 unsigned int pixfeed, pixin, pixpost;
427 struct matrox_hw_state* hw = &ACCESS_FBINFO(hw);
428
429 DBG("Ti3026_setpclk")
430
431 f_pll = Ti3026_calcclock(PMINFO clk, ACCESS_FBINFO(max_pixel_clock), &pixin, &pixfeed, &pixpost);
432
433 hw->DACclk[0] = pixin | 0xC0;
434 hw->DACclk[1] = pixfeed;
435 hw->DACclk[2] = pixpost | 0xB0;
436
437 if (p->type == FB_TYPE_TEXT) {
438 hw->DACreg[POS3026_XMEMPLLCTRL] = TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL | TVP3026_XMEMPLLCTRL_RCLK_PIXPLL;
439 hw->DACclk[3] = 0xFD;
440 hw->DACclk[4] = 0x3D;
441 hw->DACclk[5] = 0x70;
442 } else {
443 unsigned int loopfeed, loopin, looppost, loopdiv, z;
444 unsigned int Bpp;
445
446 Bpp = ACCESS_FBINFO(curr.final_bppShift);
447
448 if (p->var.bits_per_pixel == 24) {
449 loopfeed = 3; /* set lm to any possible value */
450 loopin = 3 * 32 / Bpp;
451 } else {
452 loopfeed = 4;
453 loopin = 4 * 32 / Bpp;
454 }
455 z = (110000 * loopin) / (f_pll * loopfeed);
456 loopdiv = 0; /* div 2 */
457 if (z < 2)
458 looppost = 0;
459 else if (z < 4)
460 looppost = 1;
461 else if (z < 8)
462 looppost = 2;
463 else {
464 looppost = 3;
465 loopdiv = z/16;
466 }
467 if (p->var.bits_per_pixel == 24) {
468 hw->DACclk[3] = ((65 - loopin) & 0x3F) | 0xC0;
469 hw->DACclk[4] = (65 - loopfeed) | 0x80;
470 if (ACCESS_FBINFO(accel.ramdac_rev) > 0x20) {
471 if (isInterleave(MINFO))
472 hw->DACreg[POS3026_XLATCHCTRL] = TVP3026B_XLATCHCTRL_8_3;
473 else {
474 hw->DACclk[4] &= ~0xC0;
475 hw->DACreg[POS3026_XLATCHCTRL] = TVP3026B_XLATCHCTRL_4_3;
476 }
477 } else {
478 if (isInterleave(MINFO))
479 ; /* default... */
480 else {
481 hw->DACclk[4] ^= 0xC0; /* change from 0x80 to 0x40 */
482 hw->DACreg[POS3026_XLATCHCTRL] = TVP3026A_XLATCHCTRL_4_3;
483 }
484 }
485 hw->DACclk[5] = looppost | 0xF8;
486 if (ACCESS_FBINFO(devflags.mga_24bpp_fix))
487 hw->DACclk[5] ^= 0x40;
488 } else {
489 hw->DACclk[3] = ((65 - loopin) & 0x3F) | 0xC0;
490 hw->DACclk[4] = 65 - loopfeed;
491 hw->DACclk[5] = looppost | 0xF0;
492 }
493 hw->DACreg[POS3026_XMEMPLLCTRL] = loopdiv | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL | TVP3026_XMEMPLLCTRL_RCLK_LOOPPLL;
494 }
495 return 0;
496 }
497
Ti3026_init(WPMINFO struct my_timming * m,struct display * p)498 static int Ti3026_init(WPMINFO struct my_timming* m, struct display* p) {
499 u_int8_t muxctrl = isInterleave(MINFO) ? TVP3026_XMUXCTRL_MEMORY_64BIT : TVP3026_XMUXCTRL_MEMORY_32BIT;
500 struct matrox_hw_state* hw = &ACCESS_FBINFO(hw);
501
502 DBG("Ti3026_init")
503
504 memcpy(hw->DACreg, MGADACbpp32, sizeof(hw->DACreg));
505 if (p->type == FB_TYPE_TEXT) {
506 hw->DACreg[POS3026_XLATCHCTRL] = TVP3026_XLATCHCTRL_8_1;
507 hw->DACreg[POS3026_XTRUECOLORCTRL] = TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR;
508 hw->DACreg[POS3026_XMUXCTRL] = TVP3026_XMUXCTRL_VGA;
509 hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL |
510 TVP3026_XCLKCTRL_DIV4;
511 hw->DACreg[POS3026_XMISCCTRL] = TVP3026_XMISCCTRL_DAC_PUP | TVP3026_XMISCCTRL_DAC_6BIT | TVP3026_XMISCCTRL_PSEL_DIS | TVP3026_XMISCCTRL_PSEL_LOW;
512 } else {
513 switch (p->var.bits_per_pixel) {
514 case 4: hw->DACreg[POS3026_XLATCHCTRL] = TVP3026_XLATCHCTRL_16_1; /* or _8_1, they are same */
515 hw->DACreg[POS3026_XTRUECOLORCTRL] = TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR;
516 hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_4BIT;
517 hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV8;
518 hw->DACreg[POS3026_XMISCCTRL] = TVP3026_XMISCCTRL_DAC_PUP | TVP3026_XMISCCTRL_DAC_8BIT | TVP3026_XMISCCTRL_PSEL_DIS | TVP3026_XMISCCTRL_PSEL_LOW;
519 break;
520 case 8: hw->DACreg[POS3026_XLATCHCTRL] = TVP3026_XLATCHCTRL_8_1; /* or _4_1, they are same */
521 hw->DACreg[POS3026_XTRUECOLORCTRL] = TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR;
522 hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_8BIT;
523 hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV4;
524 hw->DACreg[POS3026_XMISCCTRL] = TVP3026_XMISCCTRL_DAC_PUP | TVP3026_XMISCCTRL_DAC_8BIT | TVP3026_XMISCCTRL_PSEL_DIS | TVP3026_XMISCCTRL_PSEL_LOW;
525 break;
526 case 16:
527 /* XLATCHCTRL should be _4_1 / _2_1... Why is not? (_2_1 is used everytime) */
528 hw->DACreg[POS3026_XTRUECOLORCTRL] = (p->var.green.length == 5)? (TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_ORGB_1555 ) : (TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_RGB_565);
529 hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_16BIT;
530 hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV2;
531 break;
532 case 24:
533 /* XLATCHCTRL is: for (A) use _4_3 (?_8_3 is same? TBD), for (B) it is set in setpclk */
534 hw->DACreg[POS3026_XTRUECOLORCTRL] = TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_RGB_888;
535 hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_32BIT;
536 hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV4;
537 break;
538 case 32:
539 /* XLATCHCTRL should be _2_1 / _1_1... Why is not? (_2_1 is used everytime) */
540 hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_32BIT;
541 break;
542 default:
543 return 1; /* TODO: failed */
544 }
545 }
546 if (matroxfb_vgaHWinit(PMINFO m, p)) return 1;
547
548 /* set SYNC */
549 hw->MiscOutReg = 0xCB;
550 if (m->sync & FB_SYNC_HOR_HIGH_ACT)
551 hw->DACreg[POS3026_XGENCTRL] |= TVP3026_XGENCTRL_HSYNC_NEG;
552 if (m->sync & FB_SYNC_VERT_HIGH_ACT)
553 hw->DACreg[POS3026_XGENCTRL] |= TVP3026_XGENCTRL_VSYNC_NEG;
554 if (m->sync & FB_SYNC_ON_GREEN)
555 hw->DACreg[POS3026_XGENCTRL] |= TVP3026_XGENCTRL_SYNC_ON_GREEN;
556
557 /* set DELAY */
558 if (ACCESS_FBINFO(video.len) < 0x400000)
559 hw->CRTCEXT[3] |= 0x08;
560 else if (ACCESS_FBINFO(video.len) > 0x400000)
561 hw->CRTCEXT[3] |= 0x10;
562
563 /* set HWCURSOR */
564 if (m->interlaced) {
565 hw->DACreg[POS3026_XCURCTRL] |= TVP3026_XCURCTRL_INTERLACED;
566 }
567 if (m->HTotal >= 1536)
568 hw->DACreg[POS3026_XCURCTRL] |= TVP3026_XCURCTRL_BLANK4096;
569
570 /* set interleaving */
571 hw->MXoptionReg &= ~0x00001000;
572 if ((p->type != FB_TYPE_TEXT) && isInterleave(MINFO)) hw->MXoptionReg |= 0x00001000;
573
574 /* set DAC */
575 Ti3026_setpclk(PMINFO m->pixclock, p);
576 return 0;
577 }
578
ti3026_setMCLK(WPMINFO int fout)579 static void ti3026_setMCLK(WPMINFO int fout){
580 unsigned int f_pll;
581 unsigned int pclk_m, pclk_n, pclk_p;
582 unsigned int mclk_m, mclk_n, mclk_p;
583 unsigned int rfhcnt, mclk_ctl;
584 int tmout;
585
586 DBG("ti3026_setMCLK")
587
588 f_pll = Ti3026_calcclock(PMINFO fout, ACCESS_FBINFO(max_pixel_clock), &mclk_n, &mclk_m, &mclk_p);
589
590 /* save pclk */
591 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFC);
592 pclk_n = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
593 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFD);
594 pclk_m = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
595 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFE);
596 pclk_p = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
597
598 /* stop pclk */
599 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFE);
600 outTi3026(PMINFO TVP3026_XPIXPLLDATA, 0x00);
601
602 /* set pclk to new mclk */
603 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFC);
604 outTi3026(PMINFO TVP3026_XPIXPLLDATA, mclk_n | 0xC0);
605 outTi3026(PMINFO TVP3026_XPIXPLLDATA, mclk_m);
606 outTi3026(PMINFO TVP3026_XPIXPLLDATA, mclk_p | 0xB0);
607
608 /* wait for PLL to lock */
609 for (tmout = 500000; tmout; tmout--) {
610 if (inTi3026(PMINFO TVP3026_XPIXPLLDATA) & 0x40)
611 break;
612 udelay(10);
613 };
614 if (!tmout)
615 printk(KERN_ERR "matroxfb: Temporary pixel PLL not locked after 5 secs\n");
616
617 /* output pclk on mclk pin */
618 mclk_ctl = inTi3026(PMINFO TVP3026_XMEMPLLCTRL);
619 outTi3026(PMINFO TVP3026_XMEMPLLCTRL, mclk_ctl & 0xE7);
620 outTi3026(PMINFO TVP3026_XMEMPLLCTRL, (mclk_ctl & 0xE7) | TVP3026_XMEMPLLCTRL_STROBEMKC4);
621
622 /* stop MCLK */
623 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFB);
624 outTi3026(PMINFO TVP3026_XMEMPLLDATA, 0x00);
625
626 /* set mclk to new freq */
627 outTi3026(PMINFO TVP3026_XPLLADDR, 0xF3);
628 outTi3026(PMINFO TVP3026_XMEMPLLDATA, mclk_n | 0xC0);
629 outTi3026(PMINFO TVP3026_XMEMPLLDATA, mclk_m);
630 outTi3026(PMINFO TVP3026_XMEMPLLDATA, mclk_p | 0xB0);
631
632 /* wait for PLL to lock */
633 for (tmout = 500000; tmout; tmout--) {
634 if (inTi3026(PMINFO TVP3026_XMEMPLLDATA) & 0x40)
635 break;
636 udelay(10);
637 }
638 if (!tmout)
639 printk(KERN_ERR "matroxfb: Memory PLL not locked after 5 secs\n");
640
641 f_pll = f_pll * 333 / (10000 << mclk_p);
642 if (isMilleniumII(MINFO)) {
643 rfhcnt = (f_pll - 128) / 256;
644 if (rfhcnt > 15)
645 rfhcnt = 15;
646 } else {
647 rfhcnt = (f_pll - 64) / 128;
648 if (rfhcnt > 15)
649 rfhcnt = 0;
650 }
651 ACCESS_FBINFO(hw).MXoptionReg = (ACCESS_FBINFO(hw).MXoptionReg & ~0x000F0000) | (rfhcnt << 16);
652 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, ACCESS_FBINFO(hw).MXoptionReg);
653
654 /* output MCLK to MCLK pin */
655 outTi3026(PMINFO TVP3026_XMEMPLLCTRL, (mclk_ctl & 0xE7) | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL);
656 outTi3026(PMINFO TVP3026_XMEMPLLCTRL, (mclk_ctl ) | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL | TVP3026_XMEMPLLCTRL_STROBEMKC4);
657
658 /* stop PCLK */
659 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFE);
660 outTi3026(PMINFO TVP3026_XPIXPLLDATA, 0x00);
661
662 /* restore pclk */
663 outTi3026(PMINFO TVP3026_XPLLADDR, 0xFC);
664 outTi3026(PMINFO TVP3026_XPIXPLLDATA, pclk_n);
665 outTi3026(PMINFO TVP3026_XPIXPLLDATA, pclk_m);
666 outTi3026(PMINFO TVP3026_XPIXPLLDATA, pclk_p);
667
668 /* wait for PLL to lock */
669 for (tmout = 500000; tmout; tmout--) {
670 if (inTi3026(PMINFO TVP3026_XPIXPLLDATA) & 0x40)
671 break;
672 udelay(10);
673 }
674 if (!tmout)
675 printk(KERN_ERR "matroxfb: Pixel PLL not locked after 5 secs\n");
676 }
677
ti3026_ramdac_init(WPMINFO2)678 static void ti3026_ramdac_init(WPMINFO2) {
679
680 DBG("ti3026_ramdac_init")
681
682 ACCESS_FBINFO(features.pll.vco_freq_min) = 110000;
683 ACCESS_FBINFO(features.pll.ref_freq) = 114545;
684 ACCESS_FBINFO(features.pll.feed_div_min) = 2;
685 ACCESS_FBINFO(features.pll.feed_div_max) = 24;
686 ACCESS_FBINFO(features.pll.in_div_min) = 2;
687 ACCESS_FBINFO(features.pll.in_div_max) = 63;
688 ACCESS_FBINFO(features.pll.post_shift_max) = 3;
689 if (ACCESS_FBINFO(devflags.noinit))
690 return;
691 ti3026_setMCLK(PMINFO 60000);
692 }
693
Ti3026_restore(WPMINFO struct display * p)694 static void Ti3026_restore(WPMINFO struct display* p) {
695 int i;
696 unsigned char progdac[6];
697 struct matrox_hw_state* hw = &ACCESS_FBINFO(hw);
698 CRITFLAGS
699
700 DBG("Ti3026_restore")
701
702 #ifdef DEBUG
703 dprintk(KERN_INFO "EXTVGA regs: ");
704 for (i = 0; i < 6; i++)
705 dprintk("%02X:", hw->CRTCEXT[i]);
706 dprintk("\n");
707 #endif
708
709 CRITBEGIN
710
711 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, hw->MXoptionReg);
712
713 CRITEND
714
715 matroxfb_vgaHWrestore(PMINFO2);
716
717 CRITBEGIN
718
719 ACCESS_FBINFO(crtc1.panpos) = -1;
720 for (i = 0; i < 6; i++)
721 mga_setr(M_EXTVGA_INDEX, i, hw->CRTCEXT[i]);
722
723 for (i = 0; i < 21; i++) {
724 outTi3026(PMINFO DACseq[i], hw->DACreg[i]);
725 }
726
727 outTi3026(PMINFO TVP3026_XPLLADDR, 0x00);
728 progdac[0] = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
729 progdac[3] = inTi3026(PMINFO TVP3026_XLOOPPLLDATA);
730 outTi3026(PMINFO TVP3026_XPLLADDR, 0x15);
731 progdac[1] = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
732 progdac[4] = inTi3026(PMINFO TVP3026_XLOOPPLLDATA);
733 outTi3026(PMINFO TVP3026_XPLLADDR, 0x2A);
734 progdac[2] = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
735 progdac[5] = inTi3026(PMINFO TVP3026_XLOOPPLLDATA);
736
737 CRITEND
738 if (memcmp(hw->DACclk, progdac, 6)) {
739 /* agrhh... setting up PLL is very slow on Millennium... */
740 /* Mystique PLL is locked in few ms, but Millennium PLL lock takes about 0.15 s... */
741 /* Maybe even we should call schedule() ? */
742
743 CRITBEGIN
744 outTi3026(PMINFO TVP3026_XCLKCTRL, hw->DACreg[POS3026_XCLKCTRL]);
745 outTi3026(PMINFO TVP3026_XPLLADDR, 0x2A);
746 outTi3026(PMINFO TVP3026_XLOOPPLLDATA, 0);
747 outTi3026(PMINFO TVP3026_XPIXPLLDATA, 0);
748
749 outTi3026(PMINFO TVP3026_XPLLADDR, 0x00);
750 for (i = 0; i < 3; i++)
751 outTi3026(PMINFO TVP3026_XPIXPLLDATA, hw->DACclk[i]);
752 /* wait for PLL only if PLL clock requested (always for PowerMode, never for VGA) */
753 if (hw->MiscOutReg & 0x08) {
754 int tmout;
755 outTi3026(PMINFO TVP3026_XPLLADDR, 0x3F);
756 for (tmout = 500000; tmout; --tmout) {
757 if (inTi3026(PMINFO TVP3026_XPIXPLLDATA) & 0x40)
758 break;
759 udelay(10);
760 }
761
762 CRITEND
763
764 if (!tmout)
765 printk(KERN_ERR "matroxfb: Pixel PLL not locked after 5 secs\n");
766 else
767 dprintk(KERN_INFO "PixelPLL: %d\n", 500000-tmout);
768 CRITBEGIN
769 }
770 outTi3026(PMINFO TVP3026_XMEMPLLCTRL, hw->DACreg[POS3026_XMEMPLLCTRL]);
771 outTi3026(PMINFO TVP3026_XPLLADDR, 0x00);
772 for (i = 3; i < 6; i++)
773 outTi3026(PMINFO TVP3026_XLOOPPLLDATA, hw->DACclk[i]);
774 CRITEND
775 if ((hw->MiscOutReg & 0x08) && ((hw->DACclk[5] & 0x80) == 0x80)) {
776 int tmout;
777
778 CRITBEGIN
779 outTi3026(PMINFO TVP3026_XPLLADDR, 0x3F);
780 for (tmout = 500000; tmout; --tmout) {
781 if (inTi3026(PMINFO TVP3026_XLOOPPLLDATA) & 0x40)
782 break;
783 udelay(10);
784 }
785 CRITEND
786 if (!tmout)
787 printk(KERN_ERR "matroxfb: Loop PLL not locked after 5 secs\n");
788 else
789 dprintk(KERN_INFO "LoopPLL: %d\n", 500000-tmout);
790 }
791 }
792 matrox_init_putc(PMINFO p, matroxfb_ti3026_createcursor);
793
794 #ifdef DEBUG
795 dprintk(KERN_DEBUG "3026DACregs ");
796 for (i = 0; i < 21; i++) {
797 dprintk("R%02X=%02X ", DACseq[i], hw->DACreg[i]);
798 if ((i & 0x7) == 0x7) dprintk("\n" KERN_DEBUG "continuing... ");
799 }
800 dprintk("\n" KERN_DEBUG "DACclk ");
801 for (i = 0; i < 6; i++)
802 dprintk("C%02X=%02X ", i, hw->DACclk[i]);
803 dprintk("\n");
804 #endif
805 }
806
Ti3026_reset(WPMINFO2)807 static void Ti3026_reset(WPMINFO2) {
808
809 DBG("Ti3026_reset")
810
811 matroxfb_fastfont_init(MINFO);
812
813 ti3026_ramdac_init(PMINFO2);
814 }
815
816 static struct matrox_altout ti3026_output = {
817 .owner = THIS_MODULE,
818 .name = "Primary output",
819 };
820
Ti3026_preinit(WPMINFO2)821 static int Ti3026_preinit(WPMINFO2) {
822 static const int vxres_mill2[] = { 512, 640, 768, 800, 832, 960,
823 1024, 1152, 1280, 1600, 1664, 1920,
824 2048, 0};
825 static const int vxres_mill1[] = { 640, 768, 800, 960,
826 1024, 1152, 1280, 1600, 1920,
827 2048, 0};
828 struct matrox_hw_state* hw = &ACCESS_FBINFO(hw);
829
830 DBG("Ti3026_preinit")
831
832 ACCESS_FBINFO(millenium) = 1;
833 ACCESS_FBINFO(milleniumII) = (ACCESS_FBINFO(pcidev)->device != PCI_DEVICE_ID_MATROX_MIL);
834 ACCESS_FBINFO(capable.cfb4) = 1;
835 ACCESS_FBINFO(capable.text) = 1; /* isMilleniumII(MINFO); */
836 ACCESS_FBINFO(capable.vxres) = isMilleniumII(MINFO)?vxres_mill2:vxres_mill1;
837 ACCESS_FBINFO(cursor.timer.function) = matroxfb_ti3026_flashcursor;
838
839 ACCESS_FBINFO(outputs[0]).data = MINFO;
840 ACCESS_FBINFO(outputs[0]).output = &ti3026_output;
841 ACCESS_FBINFO(outputs[0]).src = MATROXFB_SRC_CRTC1;
842 ACCESS_FBINFO(outputs[0]).mode = MATROXFB_OUTPUT_MODE_MONITOR;
843
844 if (ACCESS_FBINFO(devflags.noinit))
845 return 0;
846 /* preserve VGA I/O, BIOS and PPC */
847 hw->MXoptionReg &= 0xC0000100;
848 hw->MXoptionReg |= 0x002C0000;
849 if (ACCESS_FBINFO(devflags.novga))
850 hw->MXoptionReg &= ~0x00000100;
851 if (ACCESS_FBINFO(devflags.nobios))
852 hw->MXoptionReg &= ~0x40000000;
853 if (ACCESS_FBINFO(devflags.nopciretry))
854 hw->MXoptionReg |= 0x20000000;
855 pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, hw->MXoptionReg);
856
857 ACCESS_FBINFO(accel.ramdac_rev) = inTi3026(PMINFO TVP3026_XSILICONREV);
858
859 outTi3026(PMINFO TVP3026_XCLKCTRL, TVP3026_XCLKCTRL_SRC_CLK0VGA | TVP3026_XCLKCTRL_CLKSTOPPED);
860 outTi3026(PMINFO TVP3026_XTRUECOLORCTRL, TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR);
861 outTi3026(PMINFO TVP3026_XMUXCTRL, TVP3026_XMUXCTRL_VGA);
862
863 outTi3026(PMINFO TVP3026_XPLLADDR, 0x2A);
864 outTi3026(PMINFO TVP3026_XLOOPPLLDATA, 0x00);
865 outTi3026(PMINFO TVP3026_XPIXPLLDATA, 0x00);
866
867 mga_outb(M_MISC_REG, 0x67);
868
869 outTi3026(PMINFO TVP3026_XMEMPLLCTRL, TVP3026_XMEMPLLCTRL_STROBEMKC4 | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL);
870
871 mga_outl(M_RESET, 1);
872 udelay(250);
873 mga_outl(M_RESET, 0);
874 udelay(250);
875 mga_outl(M_MACCESS, 0x00008000);
876 udelay(10);
877 return 0;
878 }
879
880 struct matrox_switch matrox_millennium = {
881 Ti3026_preinit, Ti3026_reset, Ti3026_init, Ti3026_restore, matroxfb_ti3026_selhwcursor
882 };
883 EXPORT_SYMBOL(matrox_millennium);
884 #endif
885 MODULE_LICENSE("GPL");
886