1 /* 2 * 3 * This file is subject to the terms and conditions of the GNU General Public 4 * License. See the file "COPYING" in the main directory of this archive 5 * for more details. 6 * 7 * Copyright (c) 2001-2003 Silicon Graphics, Inc. All rights reserved. 8 */ 9 10 #ifndef _ASM_IA64_SN_SN2_ADDRS_H 11 #define _ASM_IA64_SN_SN2_ADDRS_H 12 13 /* McKinley Address Format: 14 * 15 * 4 4 3 3 3 3 16 * 9 8 8 7 6 5 0 17 * +-+---------+----+--------------+ 18 * |0| Node ID | AS | Node Offset | 19 * +-+---------+----+--------------+ 20 * 21 * Node ID: If bit 38 = 1, is ICE, else is SHUB 22 * AS: Address Space Identifier. Used only if bit 38 = 0. 23 * b'00: Local Resources and MMR space 24 * bit 35 25 * 0: Local resources space 26 * node id: 27 * 0: IA64/NT compatibility space 28 * 2: Local MMR Space 29 * 4: Local memory, regardless of local node id 30 * 1: Global MMR space 31 * b'01: GET space. 32 * b'10: AMO space. 33 * b'11: Cacheable memory space. 34 * 35 * NodeOffset: byte offset 36 */ 37 38 #ifndef __ASSEMBLY__ 39 typedef union ia64_sn2_pa { 40 struct { 41 unsigned long off : 36; 42 unsigned long as : 2; 43 unsigned long nasid: 11; 44 unsigned long fill : 15; 45 } f; 46 unsigned long l; 47 void *p; 48 } ia64_sn2_pa_t; 49 #endif 50 51 #define TO_PHYS_MASK 0x0001ffcfffffffff /* Note - clear AS bits */ 52 53 54 /* Regions determined by AS */ 55 #define LOCAL_MMR_SPACE 0xc000008000000000 /* Local MMR space */ 56 #define LOCAL_PHYS_MMR_SPACE 0x8000008000000000 /* Local PhysicalMMR space */ 57 #define LOCAL_MEM_SPACE 0xc000010000000000 /* Local Memory space */ 58 #define GLOBAL_MMR_SPACE 0xc000000800000000 /* Global MMR space */ 59 #define GLOBAL_PHYS_MMR_SPACE 0x0000000800000000 /* Global Physical MMR space */ 60 #define GET_SPACE 0xe000001000000000 /* GET space */ 61 #define AMO_SPACE 0xc000002000000000 /* AMO space */ 62 #define CACHEABLE_MEM_SPACE 0xe000003000000000 /* Cacheable memory space */ 63 #define UNCACHED 0xc000000000000000 /* UnCacheable memory space */ 64 #define UNCACHED_PHYS 0x8000000000000000 /* UnCacheable physical memory space */ 65 66 #define PHYS_MEM_SPACE 0x0000003000000000 /* physical memory space */ 67 68 /* SN2 address macros */ 69 #define NID_SHFT 38 70 #define LOCAL_MMR_ADDR(a) (UNCACHED | LOCAL_MMR_SPACE | (a)) 71 #define LOCAL_MMR_PHYS_ADDR(a) (UNCACHED_PHYS | LOCAL_PHYS_MMR_SPACE | (a)) 72 #define LOCAL_MEM_ADDR(a) (LOCAL_MEM_SPACE | (a)) 73 #define REMOTE_ADDR(n,a) ((((unsigned long)(n))<<NID_SHFT) | (a)) 74 #define GLOBAL_MMR_ADDR(n,a) (UNCACHED | GLOBAL_MMR_SPACE | REMOTE_ADDR(n,a)) 75 #define GLOBAL_MMR_PHYS_ADDR(n,a) (UNCACHED_PHYS | GLOBAL_PHYS_MMR_SPACE | REMOTE_ADDR(n,a)) 76 #define GET_ADDR(n,a) (GET_SPACE | REMOTE_ADDR(n,a)) 77 #define AMO_ADDR(n,a) (UNCACHED | AMO_SPACE | REMOTE_ADDR(n,a)) 78 #define GLOBAL_MEM_ADDR(n,a) (CACHEABLE_MEM_SPACE | REMOTE_ADDR(n,a)) 79 80 /* non-II mmr's start at top of big window space (4G) */ 81 #define BWIN_TOP 0x0000000100000000 82 83 /* 84 * general address defines - for code common to SN0/SN1/SN2 85 */ 86 #define CAC_BASE CACHEABLE_MEM_SPACE /* cacheable memory space */ 87 #define IO_BASE (UNCACHED | GLOBAL_MMR_SPACE) /* lower 4G maps II's XIO space */ 88 #define AMO_BASE (UNCACHED | AMO_SPACE) /* fetch & op space */ 89 #define MSPEC_BASE AMO_BASE /* fetch & op space */ 90 #define UNCAC_BASE (UNCACHED | CACHEABLE_MEM_SPACE) /* uncached global memory */ 91 #define GET_BASE GET_SPACE /* momentarily coherent remote mem. */ 92 #define CALIAS_BASE LOCAL_CACHEABLE_BASE /* cached node-local memory */ 93 #define UALIAS_BASE (UNCACHED | LOCAL_CACHEABLE_BASE) /* uncached node-local memory */ 94 95 #define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) 96 #define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) 97 #define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) 98 #define TO_MSPEC(x) (MSPEC_BASE | ((x) & TO_PHYS_MASK)) 99 #define TO_GET(x) (GET_BASE | ((x) & TO_PHYS_MASK)) 100 #define TO_CALIAS(x) (CALIAS_BASE | TO_NODE_ADDRSPACE(x)) 101 #define TO_UALIAS(x) (UALIAS_BASE | TO_NODE_ADDRSPACE(x)) 102 #define NODE_SIZE_BITS 36 /* node offset : bits <35:0> */ 103 #define BWIN_SIZE_BITS 29 /* big window size: 512M */ 104 #define NASID_BITS 11 /* bits <48:38> */ 105 #define NASID_BITMASK (0x7ffULL) 106 #define NASID_SHFT NID_SHFT 107 #define NASID_META_BITS 0 /* ???? */ 108 #define NASID_LOCAL_BITS 7 /* same router as SN1 */ 109 110 #define NODE_ADDRSPACE_SIZE (UINT64_CAST 1 << NODE_SIZE_BITS) 111 #define NASID_MASK (UINT64_CAST NASID_BITMASK << NASID_SHFT) 112 #define NASID_GET(_pa) (int) ((UINT64_CAST (_pa) >> \ 113 NASID_SHFT) & NASID_BITMASK) 114 #define PHYS_TO_DMA(x) ( ((x & NASID_MASK) >> 2) | \ 115 (x & (NODE_ADDRSPACE_SIZE - 1)) ) 116 117 #define CHANGE_NASID(n,x) ({ia64_sn2_pa_t _v; _v.l = (long) (x); _v.f.nasid = n; _v.p;}) 118 119 /* 120 * Determine if a physical address should be referenced as cached or uncached. 121 * For now, assume all memory is cached and everything else is noncached. 122 * (Later, we may need to special case areas of memory to be reference uncached). 123 */ 124 #define IS_CACHED_ADDRESS(x) (((x) & PHYS_MEM_SPACE) == PHYS_MEM_SPACE) 125 126 127 #ifndef __ASSEMBLY__ 128 #define NODE_SWIN_BASE(nasid, widget) \ 129 ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \ 130 : RAW_NODE_SWIN_BASE(nasid, widget)) 131 #else 132 #define NODE_SWIN_BASE(nasid, widget) \ 133 (NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS)) 134 #define LOCAL_SWIN_BASE(widget) \ 135 (UNCACHED | LOCAL_MMR_SPACE | ((UINT64_CAST (widget) << SWIN_SIZE_BITS))) 136 #endif /* __ASSEMBLY__ */ 137 138 /* 139 * The following definitions pertain to the IO special address 140 * space. They define the location of the big and little windows 141 * of any given node. 142 */ 143 144 #define BWIN_INDEX_BITS 3 145 #define BWIN_SIZE (UINT64_CAST 1 << BWIN_SIZE_BITS) 146 #define BWIN_SIZEMASK (BWIN_SIZE - 1) 147 #define BWIN_WIDGET_MASK 0x7 148 #define NODE_BWIN_BASE0(nasid) (NODE_IO_BASE(nasid) + BWIN_SIZE) 149 #define NODE_BWIN_BASE(nasid, bigwin) (NODE_BWIN_BASE0(nasid) + \ 150 (UINT64_CAST (bigwin) << BWIN_SIZE_BITS)) 151 152 #define BWIN_WIDGETADDR(addr) ((addr) & BWIN_SIZEMASK) 153 #define BWIN_WINDOWNUM(addr) (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK) 154 155 /* 156 * Verify if addr belongs to large window address of node with "nasid" 157 * 158 * 159 * NOTE: "addr" is expected to be XKPHYS address, and NOT physical 160 * address 161 * 162 * 163 */ 164 165 #define NODE_BWIN_ADDR(nasid, addr) \ 166 (((addr) >= NODE_BWIN_BASE0(nasid)) && \ 167 ((addr) < (NODE_BWIN_BASE(nasid, HUB_NUM_BIG_WINDOW) + \ 168 BWIN_SIZE))) 169 170 #endif /* _ASM_IA64_SN_SN2_ADDRS_H */ 171