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Searched refs:TARGET_COMMAND_REG (Results 1 – 11 of 11) sorted by relevance

/linux-2.4.37.9/drivers/scsi/
Dmac_NCR5380.c911 NCR5380_write(TARGET_COMMAND_REG, 0); in NCR5380_init()
1440 NCR5380_write(TARGET_COMMAND_REG, 0); in NCR5380_select()
1757 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(p)); in NCR5380_transfer_pio()
1880 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(tmp)); in do_abort()
1950 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(p)); in NCR5380_transfer_dma()
2078 if (NCR5380_read(TARGET_COMMAND_REG) & TCR_LAST_BYTE_SENT) { in NCR5380_transfer_dma()
2090 while (!(NCR5380_read(TARGET_COMMAND_REG) & TCR_LAST_BYTE_SENT)); in NCR5380_transfer_dma()
2176 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(tmp)); in NCR5380_information_transfer()
2438 NCR5380_write(TARGET_COMMAND_REG, 0); in NCR5380_information_transfer()
2488 NCR5380_write(TARGET_COMMAND_REG, 0); in NCR5380_information_transfer()
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Dsun3_NCR5380.c890 NCR5380_write(TARGET_COMMAND_REG, 0); in NCR5380_init()
1426 NCR5380_write(TARGET_COMMAND_REG, 0); in NCR5380_select()
1745 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(p)); in NCR5380_transfer_pio()
1868 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(tmp)); in do_abort()
1940 NCR5380_write(TARGET_COMMAND_REG, 1); in NCR5380_transfer_dma()
1946 NCR5380_write(TARGET_COMMAND_REG, 0); in NCR5380_transfer_dma()
2039 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(tmp)); in NCR5380_information_transfer()
2299 NCR5380_write(TARGET_COMMAND_REG, 0); in NCR5380_information_transfer()
2349 NCR5380_write(TARGET_COMMAND_REG, 0); in NCR5380_information_transfer()
2568 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(PHASE_MSGIN)); in NCR5380_reselect()
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DNCR5380.c708 NCR5380_write(TARGET_COMMAND_REG, 0); in NCR5380_probe_irq()
1009 NCR5380_write(TARGET_COMMAND_REG, 0); in NCR5380_init()
1481 NCR5380_write(TARGET_COMMAND_REG, 0); in NCR5380_select()
1777 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(p)); in NCR5380_transfer_pio()
1895 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(NCR5380_read(STATUS_REG) & PHASE_MASK)); in do_reset()
1934 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(tmp)); in do_abort()
2007 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(p)); in NCR5380_transfer_dma()
2201 if (NCR5380_read(TARGET_COMMAND_REG) & TCR_LAST_BYTE_SENT) { in NCR5380_transfer_dma()
2208 while (!(NCR5380_read(TARGET_COMMAND_REG) & TCR_LAST_BYTE_SENT)); in NCR5380_transfer_dma()
2283 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(tmp));
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Datari_NCR5380.c885 NCR5380_write(TARGET_COMMAND_REG, 0); in NCR5380_init()
1436 NCR5380_write(TARGET_COMMAND_REG, 0); in NCR5380_select()
1753 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(p)); in NCR5380_transfer_pio()
1876 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(tmp)); in do_abort()
1944 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(p)); in NCR5380_transfer_dma()
2026 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(tmp)); in NCR5380_information_transfer()
2280 NCR5380_write(TARGET_COMMAND_REG, 0); in NCR5380_information_transfer()
2336 NCR5380_write(TARGET_COMMAND_REG, 0); in NCR5380_information_transfer()
2881 NCR5380_write( TARGET_COMMAND_REG, in NCR5380_reset()
2889 NCR5380_write( TARGET_COMMAND_REG, 0 ); in NCR5380_reset()
DNCR5380.h109 #define TARGET_COMMAND_REG 3 macro
Ddtc.c407 while (!(NCR5380_read(TARGET_COMMAND_REG) & TCR_LAST_BYTE_SENT)) in NCR5380_pwrite()
Dmac_scsi.c356 NCR5380_write( TARGET_COMMAND_REG, in mac_scsi_reset_boot()
Dsun3_scsi.c340 NCR5380_write( TARGET_COMMAND_REG, in sun3_scsi_reset_boot()
Dsun3_scsi_vme.c316 NCR5380_write( TARGET_COMMAND_REG, in sun3_scsi_reset_boot()
Datari_scsi.c880 NCR5380_write( TARGET_COMMAND_REG, in atari_scsi_reset_boot()
Dg_NCR5380.c702 while (!(NCR5380_read(TARGET_COMMAND_REG) & TCR_LAST_BYTE_SENT)) in NCR5380_pwrite()