1 #ifndef _INTELFBHW_H 2 #define _INTELFBHW_H 3 4 /* $DHD: intelfb/intelfbhw.h,v 1.3 2003/02/05 20:23:56 dawes Exp $ */ 5 /* $TG$ */ 6 7 8 /*** HW-specific data ***/ 9 10 /* Information about the 852GM/855GM variants */ 11 #define INTEL_85X_CAPID 0x44 12 #define INTEL_85X_VARIANT_MASK 0x7 13 #define INTEL_85X_VARIANT_SHIFT 5 14 #define INTEL_VAR_855GME 0x0 15 #define INTEL_VAR_855GM 0x4 16 #define INTEL_VAR_852GME 0x2 17 #define INTEL_VAR_852GM 0x5 18 19 /* 20 * The Bridge device's PCI config space has information about the 21 * fb aperture size and the amount of pre-reserved memory. 22 */ 23 #define INTEL_GMCH_CTRL 0x52 24 #define INTEL_GMCH_ENABLED 0x4 25 #define INTEL_GMCH_MEM_MASK 0x1 26 #define INTEL_GMCH_MEM_64M 0x1 27 #define INTEL_GMCH_MEM_128M 0 28 29 #define INTEL_830_GMCH_GMS_MASK (0x7 << 4) 30 #define INTEL_830_GMCH_GMS_DISABLED (0x0 << 4) 31 #define INTEL_830_GMCH_GMS_LOCAL (0x1 << 4) 32 #define INTEL_830_GMCH_GMS_STOLEN_512 (0x2 << 4) 33 #define INTEL_830_GMCH_GMS_STOLEN_1024 (0x3 << 4) 34 #define INTEL_830_GMCH_GMS_STOLEN_8192 (0x4 << 4) 35 36 #define INTEL_855_GMCH_GMS_MASK (0x7 << 4) 37 #define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4) 38 #define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4) 39 #define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4) 40 #define INTEL_855_GMCH_GMS_STOLEN_8M (0x3 << 4) 41 #define INTEL_855_GMCH_GMS_STOLEN_16M (0x4 << 4) 42 #define INTEL_855_GMCH_GMS_STOLEN_32M (0x5 << 4) 43 44 /* GTT page size */ 45 #define GTT_PAGE_SIZE 4096 46 47 /* HW registers */ 48 49 /* Fence registers */ 50 #define FENCE 0x2000 51 #define FENCE_NUM 8 52 53 /* Primary ring buffer */ 54 #define PRI_RING_TAIL 0x2030 55 #define RING_TAIL_MASK 0x001ffff8 56 #define RING_INUSE 0x1 57 58 #define PRI_RING_HEAD 0x2034 59 #define RING_HEAD_WRAP_MASK 0x7ff 60 #define RING_HEAD_WRAP_SHIFT 21 61 #define RING_HEAD_MASK 0x001ffffc 62 63 #define PRI_RING_START 0x2038 64 #define RING_START_MASK 0xfffff000 65 66 #define PRI_RING_LENGTH 0x203c 67 #define RING_LENGTH_MASK 0x001ff000 68 #define RING_REPORT_MASK (0x3 << 1) 69 #define RING_NO_REPORT (0x0 << 1) 70 #define RING_REPORT_64K (0x1 << 1) 71 #define RING_REPORT_4K (0x2 << 1) 72 #define RING_REPORT_128K (0x3 << 1) 73 #define RING_ENABLE 0x1 74 75 /* 76 * Tail can't wrap to any closer than RING_MIN_FREE bytes of the head, 77 * and the last RING_MIN_FREE bytes need to be padded with MI_NOOP 78 */ 79 #define RING_MIN_FREE 64 80 81 #define INSTDONE 0x2090 82 #define PRI_RING_EMPTY 1 83 84 #define INSTPM 0x20c0 85 #define SYNC_FLUSH_ENABLE (1 << 5) 86 87 #define MEM_MODE 0x20cc 88 89 #define MASK_SHIFT 16 90 91 #define FW_BLC_0 0x20d8 92 #define FW_DISPA_WM_SHIFT 0 93 #define FW_DISPA_WM_MASK 0x3f 94 #define FW_DISPA_BL_SHIFT 8 95 #define FW_DISPA_BL_MASK 0xf 96 #define FW_DISPB_WM_SHIFT 16 97 #define FW_DISPB_WM_MASK 0x1f 98 #define FW_DISPB_BL_SHIFT 24 99 #define FW_DISPB_BL_MASK 0x7 100 101 #define FW_BLC_1 0x20dc 102 #define FW_DISPC_WM_SHIFT 0 103 #define FW_DISPC_WM_MASK 0x1f 104 #define FW_DISPC_BL_SHIFT 8 105 #define FW_DISPC_BL_MASK 0x7 106 107 108 /* PLL registers */ 109 #define VGA0_DIVISOR 0x06000 110 #define VGA1_DIVISOR 0x06004 111 #define VGAPD 0x06010 112 #define VGAPD_0_P1_SHIFT 0 113 #define VGAPD_0_P1_FORCE_DIV2 (1 << 5) 114 #define VGAPD_0_P2_SHIFT 7 115 #define VGAPD_1_P1_SHIFT 8 116 #define VGAPD_1_P1_FORCE_DIV2 (1 << 13) 117 #define VGAPD_1_P2_SHIFT 15 118 119 #define DPLL_A 0x06014 120 #define DPLL_B 0x06018 121 #define DPLL_VCO_ENABLE (1 << 31) 122 #define DPLL_2X_CLOCK_ENABLE (1 << 30) 123 #define DPLL_SYNCLOCK_ENABLE (1 << 29) 124 #define DPLL_VGA_MODE_DISABLE (1 << 28) 125 #define DPLL_P2_MASK 1 126 #define DPLL_P2_SHIFT 23 127 #define DPLL_P1_FORCE_DIV2 (1 << 21) 128 #define DPLL_P1_MASK 0x1f 129 #define DPLL_P1_SHIFT 16 130 #define DPLL_REFERENCE_SELECT_MASK (0x3 << 13) 131 #define DPLL_REFERENCE_DEFAULT (0x0 << 13) 132 #define DPLL_REFERENCE_TVCLK (0x2 << 13) 133 #define DPLL_RATE_SELECT_MASK (1 << 8) 134 #define DPLL_RATE_SELECT_FP0 (0 << 8) 135 #define DPLL_RATE_SELECT_FP1 (1 << 8) 136 137 #define FPA0 0x06040 138 #define FPA1 0x06044 139 #define FPB0 0x06048 140 #define FPB1 0x0604c 141 #define FP_DIVISOR_MASK 0x3f 142 #define FP_N_DIVISOR_SHIFT 16 143 #define FP_M1_DIVISOR_SHIFT 8 144 #define FP_M2_DIVISOR_SHIFT 0 145 146 /* PLL parameters (these are for 852GM/855GM/865G, check earlier chips). */ 147 /* Clock values are in units of kHz */ 148 #define PLL_REFCLK 48000 149 #define MIN_VCO_FREQ 930000 150 #define MAX_VCO_FREQ 1400000 151 #define MIN_CLOCK 25000 152 #define MAX_CLOCK 350000 153 #define P_TRANSITION_CLOCK 165000 154 #define MIN_M 108 155 #define MAX_M 140 156 #define MIN_M1 18 157 #define MAX_M1 26 158 #define MIN_M2 6 159 #define MAX_M2 16 160 #define MIN_P 4 161 #define MAX_P 128 162 #define MIN_P1 0 163 #define MAX_P1 31 164 #define MIN_N 3 165 #define MAX_N 16 166 167 #define CALC_VCLOCK(m1, m2, n, p1, p2) \ 168 ((PLL_REFCLK * (5 * ((m1) + 2) + ((m2) + 2)) / ((n) + 2)) / \ 169 (((p1) + 2) * (1 << (p2 + 1)))) 170 171 #define CALC_VCLOCK3(m, n, p) ((PLL_REFCLK * (m) / (n)) / (p)) 172 173 /* Two pipes */ 174 #define PIPE_A 0 175 #define PIPE_B 1 176 #define PIPE_MASK 1 177 178 /* palette registers */ 179 #define PALETTE_A 0x0a000 180 #define PALETTE_B 0x0a800 181 #ifndef PALETTE_8_ENTRIES 182 #define PALETTE_8_ENTRIES 256 183 #endif 184 #define PALETTE_8_SIZE (PALETTE_8_ENTRIES * 4) 185 #define PALETTE_10_ENTRIES 128 186 #define PALETTE_10_SIZE (PALETTE_10_ENTRIES * 8) 187 #define PALETTE_8_MASK 0xff 188 #define PALETTE_8_RED_SHIFT 16 189 #define PALETTE_8_GREEN_SHIFT 8 190 #define PALETTE_8_BLUE_SHIFT 0 191 192 /* CRTC registers */ 193 #define HTOTAL_A 0x60000 194 #define HBLANK_A 0x60004 195 #define HSYNC_A 0x60008 196 #define VTOTAL_A 0x6000c 197 #define VBLANK_A 0x60010 198 #define VSYNC_A 0x60014 199 #define SRC_SIZE_A 0x6001c 200 #define BCLRPAT_A 0x60020 201 202 #define HTOTAL_B 0x61000 203 #define HBLANK_B 0x61004 204 #define HSYNC_B 0x61008 205 #define VTOTAL_B 0x6100c 206 #define VBLANK_B 0x61010 207 #define VSYNC_B 0x61014 208 #define SRC_SIZE_B 0x6101c 209 #define BCLRPAT_B 0x61020 210 211 #define HTOTAL_MASK 0xfff 212 #define HTOTAL_SHIFT 16 213 #define HACTIVE_MASK 0x7ff 214 #define HACTIVE_SHIFT 0 215 #define HBLANKEND_MASK 0xfff 216 #define HBLANKEND_SHIFT 16 217 #define HBLANKSTART_MASK 0xfff 218 #define HBLANKSTART_SHIFT 0 219 #define HSYNCEND_MASK 0xfff 220 #define HSYNCEND_SHIFT 16 221 #define HSYNCSTART_MASK 0xfff 222 #define HSYNCSTART_SHIFT 0 223 #define VTOTAL_MASK 0xfff 224 #define VTOTAL_SHIFT 16 225 #define VACTIVE_MASK 0x7ff 226 #define VACTIVE_SHIFT 0 227 #define VBLANKEND_MASK 0xfff 228 #define VBLANKEND_SHIFT 16 229 #define VBLANKSTART_MASK 0xfff 230 #define VBLANKSTART_SHIFT 0 231 #define VSYNCEND_MASK 0xfff 232 #define VSYNCEND_SHIFT 16 233 #define VSYNCSTART_MASK 0xfff 234 #define VSYNCSTART_SHIFT 0 235 #define SRC_SIZE_HORIZ_MASK 0x7ff 236 #define SRC_SIZE_HORIZ_SHIFT 16 237 #define SRC_SIZE_VERT_MASK 0x7ff 238 #define SRC_SIZE_VERT_SHIFT 0 239 240 #define ADPA 0x61100 241 #define ADPA_DAC_ENABLE (1 << 31) 242 #define ADPA_DAC_DISABLE 0 243 #define ADPA_PIPE_SELECT_SHIFT 30 244 #define ADPA_USE_VGA_HVPOLARITY (1 << 15) 245 #define ADPA_SETS_HVPOLARITY 0 246 #define ADPA_DPMS_CONTROL_MASK (0x3 << 10) 247 #define ADPA_DPMS_D0 (0x0 << 10) 248 #define ADPA_DPMS_D2 (0x1 << 10) 249 #define ADPA_DPMS_D1 (0x2 << 10) 250 #define ADPA_DPMS_D3 (0x3 << 10) 251 #define ADPA_VSYNC_ACTIVE_SHIFT 4 252 #define ADPA_HSYNC_ACTIVE_SHIFT 3 253 #define ADPA_SYNC_ACTIVE_MASK 1 254 #define ADPA_SYNC_ACTIVE_HIGH 1 255 #define ADPA_SYNC_ACTIVE_LOW 0 256 257 #define DVOA 0x61120 258 #define DVOB 0x61140 259 #define DVOC 0x61160 260 #define LVDS 0x61180 261 #define PORT_ENABLE (1 << 31) 262 263 #define DVOA_SRCDIM 0x61124 264 #define DVOB_SRCDIM 0x61144 265 #define DVOC_SRCDIM 0x61164 266 267 #define PIPEACONF 0x70008 268 #define PIPEBCONF 0x71008 269 #define PIPECONF_ENABLE (1 << 31) 270 #define PIPECONF_DISABLE 0 271 #define PIPECONF_DOUBLE_WIDE (1 << 30) 272 #define PIPECONF_SINGLE_WIDE 0 273 #define PIPECONF_LOCKED (1 << 25) 274 #define PIPECONF_UNLOCKED 0 275 #define PIPECONF_GAMMA (1 << 24) 276 #define PIPECONF_PALETTE 0 277 278 #define DISPARB 0x70030 279 #define DISPARB_AEND_MASK 0x1ff 280 #define DISPARB_AEND_SHIFT 0 281 #define DISPARB_BEND_MASK 0x3ff 282 #define DISPARB_BEND_SHIFT 9 283 284 /* Desktop HW cursor */ 285 #define CURSOR_CONTROL 0x70080 286 #define CURSOR_ENABLE (1 << 31) 287 #define CURSOR_GAMMA_ENABLE (1 << 30) 288 #define CURSOR_STRIDE_MASK (0x3 << 28) 289 #define CURSOR_STRIDE_256 (0x0 << 28) 290 #define CURSOR_STRIDE_512 (0x1 << 28) 291 #define CURSOR_STRIDE_1K (0x2 << 28) 292 #define CURSOR_STRIDE_2K (0x3 << 28) 293 #define CURSOR_FORMAT_MASK (0x7 << 24) 294 #define CURSOR_FORMAT_2C (0x0 << 24) 295 #define CURSOR_FORMAT_3C (0x1 << 24) 296 #define CURSOR_FORMAT_4C (0x2 << 24) 297 #define CURSOR_FORMAT_ARGB (0x4 << 24) 298 #define CURSOR_FORMAT_XRGB (0x5 << 24) 299 300 /* Mobile HW cursor (and i810) */ 301 #define CURSOR_A_CONTROL CURSOR_CONTROL 302 #define CURSOR_B_CONTROL 0x700c0 303 #define CURSOR_MODE_MASK 0x27 304 #define CURSOR_MODE_DISABLE 0 305 #define CURSOR_MODE_64_3C 0x04 306 #define CURSOR_MODE_64_4C_AX 0x05 307 #define CURSOR_MODE_64_4C 0x06 308 #define CURSOR_MODE_64_32B_AX 0x07 309 #define CURSOR_MODE_64_ARGB_AX 0x27 310 #define CURSOR_PIPE_SELECT_SHIFT 28 311 #define CURSOR_MOBILE_GAMMA_ENABLE (1 << 26) 312 #define CURSOR_MEM_TYPE_LOCAL (1 << 25) 313 314 /* All platforms (desktop has no pipe B) */ 315 #define CURSOR_A_BASEADDR 0x70084 316 #define CURSOR_B_BASEADDR 0x700c4 317 #define CURSOR_BASE_MASK 0xffffff00 318 319 #define CURSOR_A_POSITION 0x70088 320 #define CURSOR_B_POSITION 0x700c8 321 #define CURSOR_POS_SIGN (1 << 15) 322 #define CURSOR_POS_MASK 0x7ff 323 #define CURSOR_X_SHIFT 0 324 #define CURSOR_Y_SHIFT 16 325 326 #define CURSOR_A_PALETTE0 0x70090 327 #define CURSOR_A_PALETTE1 0x70094 328 #define CURSOR_A_PALETTE2 0x70098 329 #define CURSOR_A_PALETTE3 0x7009c 330 #define CURSOR_B_PALETTE0 0x700d0 331 #define CURSOR_B_PALETTE1 0x700d4 332 #define CURSOR_B_PALETTE2 0x700d8 333 #define CURSOR_B_PALETTE3 0x700dc 334 #define CURSOR_COLOR_MASK 0xff 335 #define CURSOR_RED_SHIFT 16 336 #define CURSOR_GREEN_SHIFT 8 337 #define CURSOR_BLUE_SHIFT 0 338 #define CURSOR_PALETTE_MASK 0xffffff 339 340 /* Desktop only */ 341 #define CURSOR_SIZE 0x700a0 342 #define CURSOR_SIZE_MASK 0x3ff 343 #define CURSOR_SIZE_H_SHIFT 0 344 #define CURSOR_SIZE_V_SHIFT 12 345 346 #define DSPACNTR 0x70180 347 #define DSPBCNTR 0x71180 348 #define DISPPLANE_PLANE_ENABLE (1 << 31) 349 #define DISPPLANE_PLANE_DISABLE 0 350 #define DISPPLANE_GAMMA_ENABLE (1<<30) 351 #define DISPPLANE_GAMMA_DISABLE 0 352 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26) 353 #define DISPPLANE_8BPP (0x2<<26) 354 #define DISPPLANE_15_16BPP (0x4<<26) 355 #define DISPPLANE_16BPP (0x5<<26) 356 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) 357 #define DISPPLANE_32BPP (0x7<<26) 358 #define DISPPLANE_STEREO_ENABLE (1<<25) 359 #define DISPPLANE_STEREO_DISABLE 0 360 #define DISPPLANE_SEL_PIPE_SHIFT 24 361 #define DISPPLANE_SRC_KEY_ENABLE (1<<22) 362 #define DISPPLANE_SRC_KEY_DISABLE 0 363 #define DISPPLANE_LINE_DOUBLE (1<<20) 364 #define DISPPLANE_NO_LINE_DOUBLE 0 365 #define DISPPLANE_STEREO_POLARITY_FIRST 0 366 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) 367 /* plane B only */ 368 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) 369 #define DISPPLANE_ALPHA_TRANS_DISABLE 0 370 #define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0 371 #define DISPPLANE_SPRITE_ABOVE_OVERLAY 1 372 373 #define DSPABASE 0x70184 374 #define DSPASTRIDE 0x70188 375 376 #define DSPBBASE 0x71184 377 #define DSPBSTRIDE 0x71188 378 379 #define VGACNTRL 0x71400 380 #define VGA_DISABLE (1 << 31) 381 #define VGA_ENABLE 0 382 #define VGA_PIPE_SELECT_SHIFT 29 383 #define VGA_PALETTE_READ_SELECT 23 384 #define VGA_PALETTE_A_WRITE_DISABLE (1 << 22) 385 #define VGA_PALETTE_B_WRITE_DISABLE (1 << 21) 386 #define VGA_LEGACY_PALETTE (1 << 20) 387 #define VGA_6BIT_DAC 0 388 #define VGA_8BIT_DAC (1 << 20) 389 390 #define ADD_ID 0x71408 391 #define ADD_ID_MASK 0xff 392 393 /* BIOS scratch area registers (830M and 845G). */ 394 #define SWF0 0x71410 395 #define SWF1 0x71414 396 #define SWF2 0x71418 397 #define SWF3 0x7141c 398 #define SWF4 0x71420 399 #define SWF5 0x71424 400 #define SWF6 0x71428 401 402 /* BIOS scratch area registers (852GM, 855GM, 865G). */ 403 #define SWF00 0x70410 404 #define SWF01 0x70414 405 #define SWF02 0x70418 406 #define SWF03 0x7041c 407 #define SWF04 0x70420 408 #define SWF05 0x70424 409 #define SWF06 0x70428 410 411 #define SWF10 SWF0 412 #define SWF11 SWF1 413 #define SWF12 SWF2 414 #define SWF13 SWF3 415 #define SWF14 SWF4 416 #define SWF15 SWF5 417 #define SWF16 SWF6 418 419 #define SWF30 0x72414 420 #define SWF31 0x72418 421 #define SWF32 0x7241c 422 423 /* Memory Commands */ 424 #define MI_NOOP (0x00 << 23) 425 #define MI_NOOP_WRITE_ID (1 << 22) 426 #define MI_NOOP_ID_MASK ((1 << 22) - 1) 427 428 #define MI_FLUSH (0x03 << 23) 429 #define MI_WRITE_DIRTY_STATE (1 << 4) 430 #define MI_END_SCENE (1 << 3) 431 #define MI_INHIBIT_RENDER_CACHE_FLUSH (1 << 2) 432 #define MI_INVALIDATE_MAP_CACHE (1 << 0) 433 434 #define MI_STORE_DWORD_IMM ((0x20 << 23) | 1) 435 436 /* 2D Commands */ 437 #define COLOR_BLT_CMD ((2 << 29) | (0x40 << 22) | 3) 438 #define XY_COLOR_BLT_CMD ((2 << 29) | (0x50 << 22) | 4) 439 #define XY_SETUP_CLIP_BLT_CMD ((2 << 29) | (0x03 << 22) | 1) 440 #define XY_SRC_COPY_BLT_CMD ((2 << 29) | (0x53 << 22) | 6) 441 #define SRC_COPY_BLT_CMD ((2 << 29) | (0x43 << 22) | 4) 442 #define XY_MONO_PAT_BLT_CMD ((2 << 29) | (0x52 << 22) | 7) 443 #define XY_MONO_SRC_BLT_CMD ((2 << 29) | (0x54 << 22) | 6) 444 #define XY_MONO_SRC_IMM_BLT_CMD ((2 << 29) | (0x71 << 22) | 5) 445 446 #define DW_LENGTH_MASK 0xff 447 448 #define WRITE_ALPHA (1 << 21) 449 #define WRITE_RGB (1 << 20) 450 #define VERT_SEED (3 << 8) 451 #define HORIZ_SEED (3 << 12) 452 453 #define COLOR_DEPTH_8 (0 << 24) 454 #define COLOR_DEPTH_16 (1 << 24) 455 #define COLOR_DEPTH_32 (3 << 24) 456 457 #define SRC_ROP_GXCOPY 0xcc 458 #define SRC_ROP_GXXOR 0x66 459 460 #define PITCH_SHIFT 0 461 #define ROP_SHIFT 16 462 #define WIDTH_SHIFT 0 463 #define HEIGHT_SHIFT 16 464 465 /* in bytes */ 466 #define MAX_MONO_IMM_SIZE 128 467 468 469 /*** Macros ***/ 470 471 /* I/O macros */ 472 #define INREG8(addr) readb(dinfo->mmio_base + (addr)) 473 #define INREG(addr) readl(dinfo->mmio_base + (addr)) 474 #define OUTREG8(addr, val) writeb((val), dinfo->mmio_base + (addr)) 475 #define OUTREG(addr, val) writel((val), dinfo->mmio_base + (addr)) 476 477 /* Ring buffer macros */ 478 #define OUT_RING(n) do { \ 479 writel((n), dinfo->ring_base + dinfo->ring_tail); \ 480 dinfo->ring_tail += 4; \ 481 dinfo->ring_tail &= dinfo->ring_tail_mask; \ 482 } while (0) 483 484 #define START_RING(n) do { \ 485 u32 needed; \ 486 needed = (n) * 4; \ 487 if (dinfo->ring_tail + needed > \ 488 dinfo->ring_tail_mask - RING_MIN_FREE) { \ 489 needed += dinfo->ring_tail_mask + 1 - dinfo->ring_tail; \ 490 } \ 491 if (dinfo->ring_space < needed) \ 492 wait_ring(dinfo, needed); \ 493 dinfo->ring_space -= needed; \ 494 while (needed > (n) * 4) { \ 495 OUT_RING(MI_NOOP); \ 496 needed -= 4; \ 497 } \ 498 } while (0) 499 500 #define ADVANCE_RING() do { \ 501 OUTREG(PRI_RING_TAIL, dinfo->ring_tail); \ 502 } while (0) 503 504 #define DO_RING_IDLE() do { \ 505 u32 head, tail; \ 506 do { \ 507 head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK; \ 508 tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK; \ 509 udelay(10); \ 510 } while (head != tail); \ 511 } while (0) 512 513 #endif /* _INTELFBHW_H */ 514