Searched refs:SR_INT (Results 1 – 5 of 5) sorted by relevance
57 #define SR_INT 0x04 /* Shift register full/empty */ macro151 via[IER] = IER_CLR | SR_INT; in maciisi_stfu()165 while (!(via[IFR] & SR_INT) && poll_timeout-- > 0) in maciisi_stfu()187 via[IER] = IER_SET | SR_INT; in maciisi_stfu()206 via[IER] = IER_SET | SR_INT; in maciisi_init_via()210 via[IFR] = SR_INT; in maciisi_init_via()406 if (via[IFR] & SR_INT) { in maciisi_poll()437 if (!(via[IFR] & SR_INT)) { in maciisi_interrupt()
76 #define SR_INT 0x04 /* Shift register full/empty */ macro178 out_8(&via[IER], IER_SET|SR_INT); /* enable interrupt from SR */ in find_via_cuda()281 WAIT_FOR(in_8(&via[IFR]) & SR_INT, "CUDA response to sync (2)"); in cuda_init_via()290 WAIT_FOR(in_8(&via[IFR]) & SR_INT, "CUDA response to sync (4)"); in cuda_init_via()455 if ((virq & SR_INT) == 0) { in cuda_interrupt()
67 #define SR_INT 0x04 /* Shift register full/empty */ macro300 if (via[IFR] & SR_INT) macii_interrupt(0, 0, 0); in macii_poll()
78 #define SR_INT 0x04 /* Shift register full/empty */ macro564 if (via1[IFR] & SR_INT) { in pmu_poll()565 via1[IFR] = SR_INT; in pmu_poll()
100 #define SR_INT 0x04 /* Shift register full/empty */ macro425 out_8(&via[IER], IER_SET | SR_INT | CB1_INT); in via_pmu_start()1299 out_8(&via[IFR], SR_INT); in pmu_sr_intr()1399 intr = in_8(&via[IFR]) & (SR_INT | CB1_INT); in via_pmu_interrupt()1411 if (intr & SR_INT) { in via_pmu_interrupt()2126 out_8(&via[IER], IER_SET | SR_INT | CB1_INT); in restore_via_state()