Searched refs:SPRN_DCCR (Results 1 – 3 of 3) sorted by relevance
95 mtspr(SPRN_DCCR, 0xF0000000); /* 512 MB of data space at 0x0. */ in MMU_init_hw()
176 #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ macro
199 #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ macro