1 /* -*- linux-c -*- */ 2 /* 3 * Copyright (C) 2001 By Joachim Martillo, Telford Tools, Inc. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 8 * 2 of the License, or (at your option) any later version. 9 * 10 **/ 11 12 #ifndef _SABIOCTL_H_ 13 #define _SABIOCTL_H_ 14 15 #include <linux/tty.h> 16 #include <asm/ioctl.h> 17 #include <linux/sockios.h> 18 #include "ring.h" 19 #include "Reg9050.h" 20 21 /* Channel Configuration Register 0 (CCR0) */ 22 #define SAB82532_CCR0_PU 0x80 23 #define SAB82532_CCR0_MCE 0x40 24 #define SAB82532_CCR0_SC_NRZ 0x00 25 #define SAB82532_CCR0_SC_NRZI 0x08 26 #define SAB82532_CCR0_SC_FM0 0x10 27 #define SAB82532_CCR0_SC_FM1 0x14 28 #define SAB82532_CCR0_SC_MANCH 0x18 29 #define SAB82532_CCR0_SM_HDLC 0x00 30 #define SAB82532_CCR0_SM_SDLC_LOOP 0x01 31 #define SAB82532_CCR0_SM_BISYNC 0x02 32 #define SAB82532_CCR0_SM_ASYNC 0x03 33 34 /* Channel Configuration Register 1 (CCR1) */ 35 #define SAB82532_CCR1_SFLG 0x80 36 #define SAB82532_CCR1_ODS 0x10 37 #define SAB82532_CCR1_BCR 0x08 38 #define SAB82532_CCR1_IFF 0x08 39 #define SAB82532_CCR1_ITF 0x00 40 #define SAB82532_CCR1_CM_MASK 0x07 41 42 /* Channel Configuration Register 2 (CCR2) */ 43 #define SAB82532_CCR2_SOC1 0x80 44 #define SAB82532_CCR2_SOC0 0x40 45 #define SAB82532_CCR2_BR9 0x80 46 #define SAB82532_CCR2_BR8 0x40 47 #define SAB82532_CCR2_BDF 0x20 48 #define SAB82532_CCR2_SSEL 0x10 49 #define SAB82532_CCR2_XCS0 0x20 50 #define SAB82532_CCR2_RCS0 0x10 51 #define SAB82532_CCR2_TOE 0x08 52 #define SAB82532_CCR2_RWX 0x04 53 #define SAB82532_CCR2_C32 0x02 54 #define SAB82532_CCR2_DIV 0x01 55 56 /* Channel Configuration Register 3 (CCR3) */ 57 #define SAB82532_CCR3_PSD 0x01 58 #define SAB82532_CCR3_RCRC 0x04 59 60 /* Channel Configuration Register 4 (CCR4) */ 61 #define SAB82532_CCR4_MCK4 0x80 62 #define SAB82532_CCR4_EBRG 0x40 63 #define SAB82532_CCR4_TST1 0x20 64 #define SAB82532_CCR4_ICD 0x10 65 #define SAB82532_CCR4_RF32 0x00 66 #define SAB82532_CCR4_RF16 0x01 67 #define SAB82532_CCR4_RF04 0x02 68 #define SAB82532_CCR4_RF02 0x03 69 70 /* Mode Register (MODE) */ 71 #define SAB82532_MODE_TM0 0x80 72 #define SAB82532_MODE_FRTS 0x40 73 #define SAB82532_MODE_FCTS 0x20 74 #define SAB82532_MODE_FLON 0x10 75 #define SAB82532_MODE_TCPU 0x10 76 #define SAB82532_MODE_RAC 0x08 77 #define SAB82532_MODE_RTS 0x04 78 #define SAB82532_MODE_TRS 0x02 79 #define SAB82532_MODE_TLP 0x01 80 81 struct channelcontrol 82 { 83 unsigned char ccr0; 84 unsigned char ccr1; 85 unsigned char ccr2; 86 unsigned char ccr3; 87 unsigned char ccr4; 88 unsigned char mode; 89 unsigned char rlcr; 90 }; 91 92 struct sep9050 93 { 94 unsigned short values[EPROM9050_SIZE]; 95 }; 96 97 /* EXTERNAL-CLOCKING */ 98 #define DEFAULT_CCR0 (SAB82532_CCR0_MCE | SAB82532_CCR0_SC_NRZ | SAB82532_CCR0_SM_HDLC) 99 #define DEFAULT_CCR1 (SAB82532_CCR1_SFLG | SAB82532_CCR1_ODS | SAB82532_CCR1_IFF) /* clock mode 0 */ 100 #define DEFAULT_CCR2 0 /*SAB82532_CCR2_SOC1*/ /* 0a -- RTS high*/ 101 #define DEFAULT_CCR3 SAB82532_CCR3_RCRC 102 #define DEFAULT_CCR4 0 103 #define DEFAULT_MODE (SAB82532_MODE_TM0 | SAB82532_MODE_RTS | SAB82532_MODE_RAC) 104 #define DEFAULT_RLCR ((RXSIZE/32) - 1) 105 106 #define DEFAULT_RLCR_NET ((RXSIZE/32) - 1) 107 108 /* Internal-Clocking */ 109 110 #define DCE_CCR0 (SAB82532_CCR0_MCE | SAB82532_CCR0_SC_NRZ | SAB82532_CCR0_SM_HDLC) 111 #define DCE_CCR1 (SAB82532_CCR1_SFLG | SAB82532_CCR1_ODS | SAB82532_CCR1_IFF | 6) /* clock mode 6 */ 112 #define DCE_CCR2 (SAB82532_CCR2_BDF | SAB82532_CCR2_SSEL | SAB82532_CCR2_TOE) /* 6b */ 113 #define DCE_CCR3 (SAB82532_CCR3_RCRC) 114 #define DCE_CCR4 (SAB82532_CCR4_MCK4|SAB82532_CCR4_EBRG) 115 #define DCE_MODE SAB82532_MODE_TM0 | SAB82532_MODE_RTS | SAB82532_MODE_RAC 116 #define DCE_RLCR ((RXSIZE/32) - 1) 117 118 #define ATIS_MAGIC_IOC 'A' 119 #define ATIS_IOCSPARAMS _IOW(ATIS_MAGIC_IOC,0,struct channelcontrol) 120 #define ATIS_IOCGPARAMS _IOR(ATIS_MAGIC_IOC,1,struct channelcontrol) 121 #define ATIS_IOCSSPEED _IOW(ATIS_MAGIC_IOC,2,unsigned long) 122 #define ATIS_IOCGSPEED _IOR(ATIS_MAGIC_IOC,3,unsigned long) 123 #define ATIS_IOCSSEP9050 _IOW(ATIS_MAGIC_IOC,4,struct sep9050) 124 #define ATIS_IOCGSEP9050 _IOR(ATIS_MAGIC_IOC,5,struct sep9050) 125 #define ATIS_IOCSSIGMODE _IOW(ATIS_MAGIC_IOC,6,unsigned int) 126 #define ATIS_IOCGSIGMODE _IOW(ATIS_MAGIC_IOC,7,unsigned int) 127 128 /* same order as the bytes in sp502.h and as the names in 8253xtty.c */ 129 130 #define SP502_OFF_MODE 0 131 #define SP502_RS232_MODE 1 132 #define SP502_V28_MODE SP502_RS232_MODE 133 #define SP502_RS422_MODE 2 134 #define SP502_V11_MODE SP502_RS422_MODE 135 #define SP502_X27_MODE SP502_RS422_MODE 136 #define SP502_RS485_MODE 3 137 #define SP502_RS449_MODE 4 138 #define SP502_EIA530_MODE 5 139 #define SP502_V35_MODE 6 140 141 #define SAB8253XCLEARCOUNTERS (SIOCDEVPRIVATE + 5 + 1) 142 143 #endif 144