1 /* 2 * Carsten Langgaard, carstenl@mips.com 3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 4 * 5 * ######################################################################## 6 * 7 * This program is free software; you can distribute it and/or modify it 8 * under the terms of the GNU General Public License (Version 2) as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, write to the Free Software Foundation, Inc., 18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 19 * 20 * ######################################################################## 21 * 22 * SAA9730 ethernet driver description. 23 * 24 */ 25 #ifndef _SAA9730_H 26 #define _SAA9730_H 27 28 29 /* Number of 6-byte entries in the CAM. */ 30 #define LAN_SAA9730_CAM_ENTRIES 10 31 #define LAN_SAA9730_CAM_DWORDS ((LAN_SAA9730_CAM_ENTRIES*6)/4) 32 33 /* TX and RX packet size: fixed to 2048 bytes, according to HW requirements. */ 34 #define LAN_SAA9730_PACKET_SIZE 2048 35 36 /* 37 * Number of TX buffers = number of RX buffers = 2, which is fixed according 38 * to HW requirements. 39 */ 40 #define LAN_SAA9730_BUFFERS 2 41 42 /* Number of RX packets per RX buffer. */ 43 #define LAN_SAA9730_RCV_Q_SIZE 15 44 45 /* Number of TX packets per TX buffer. */ 46 #define LAN_SAA9730_TXM_Q_SIZE 15 47 48 /* 49 * We get an interrupt for each LAN_SAA9730_DEFAULT_RCV_Q_INT_THRESHOLD 50 * packets received. 51 * If however we receive less than LAN_SAA9730_DEFAULT_RCV_Q_INT_THRESHOLD 52 * packets, the hardware can timeout after a certain time and still tell 53 * us packets have arrived. 54 * The timeout value in unit of 32 PCI clocks (33Mhz). 55 * The value 200 approximates 0.0002 seconds. 56 */ 57 #define LAN_SAA9730_RCV_Q_INT_THRESHOLD 1 58 #define LAN_SAA9730_DEFAULT_TIME_OUT_CNT 10 59 60 #define RXSF_NDIS 0 61 #define RXSF_READY 2 62 #define RXSF_HWDONE 3 63 64 #define TXSF_EMPTY 0 65 #define TXSF_READY 2 66 #define TXSF_HWDONE 3 67 68 #define LANEND_LITTLE 0 69 #define LANEND_BIG_2143 1 70 #define LANEND_BIG_4321 2 71 72 #define LANMB_ANY 0 73 #define LANMB_8 1 74 #define LANMB_32 2 75 #define LANMB_64 3 76 77 #define MACCM_AUTOMATIC 0 78 #define MACCM_10MB 1 79 #define MACCM_MII 2 80 81 /* 82 * PHY definitions for Basic registers of QS6612 (used on MIPS ATLAS board) 83 */ 84 #define PHY_CONTROL 0x0 85 #define PHY_STATUS 0x1 86 #define PHY_STATUS_LINK_UP 0x4 87 #define PHY_CONTROL_RESET 0x8000 88 #define PHY_CONTROL_AUTO_NEG 0x1000 89 #define PHY_CONTROL_RESTART_AUTO_NEG 0x0200 90 #define PHY_ADDRESS 0x0 91 92 /* PK_COUNT register. */ 93 #define PK_COUNT_TX_A_SHF 24 94 #define PK_COUNT_TX_A_MSK (0xff << PK_COUNT_TX_A_SHF) 95 #define PK_COUNT_TX_B_SHF 16 96 #define PK_COUNT_TX_B_MSK (0xff << PK_COUNT_TX_B_SHF) 97 #define PK_COUNT_RX_A_SHF 8 98 #define PK_COUNT_RX_A_MSK (0xff << PK_COUNT_RX_A_SHF) 99 #define PK_COUNT_RX_B_SHF 0 100 #define PK_COUNT_RX_B_MSK (0xff << PK_COUNT_RX_B_SHF) 101 102 /* OK2USE register. */ 103 #define OK2USE_TX_A 0x8 104 #define OK2USE_TX_B 0x4 105 #define OK2USE_RX_A 0x2 106 #define OK2USE_RX_B 0x1 107 108 /* LAN DMA CONTROL register. */ 109 #define DMA_CTL_BLK_INT 0x80000000 110 #define DMA_CTL_MAX_XFER_SHF 18 111 #define DMA_CTL_MAX_XFER_MSK (0x3 << LAN_DMA_CTL_MAX_XFER_SHF) 112 #define DMA_CTL_ENDIAN_SHF 16 113 #define DMA_CTL_ENDIAN_MSK (0x3 << LAN_DMA_CTL_ENDIAN_SHF) 114 #define DMA_CTL_RX_INT_COUNT_SHF 8 115 #define DMA_CTL_RX_INT_COUNT_MSK (0xff << LAN_DMA_CTL_RX_INT_COUNT_SHF) 116 #define DMA_CTL_EN_TX_DMA 0x00000080 117 #define DMA_CTL_EN_RX_DMA 0x00000040 118 #define DMA_CTL_RX_INT_BUFFUL_EN 0x00000020 119 #define DMA_CTL_RX_INT_TO_EN 0x00000010 120 #define DMA_CTL_RX_INT_EN 0x00000008 121 #define DMA_CTL_TX_INT_EN 0x00000004 122 #define DMA_CTL_MAC_TX_INT_EN 0x00000002 123 #define DMA_CTL_MAC_RX_INT_EN 0x00000001 124 125 /* DMA STATUS register. */ 126 #define DMA_STATUS_BAD_ADDR_SHF 16 127 #define DMA_STATUS_BAD_ADDR_MSK (0xf << DMA_STATUS_BAD_ADDR_SHF) 128 #define DMA_STATUS_RX_PKTS_RECEIVED_SHF 8 129 #define DMA_STATUS_RX_PKTS_RECEIVED_MSK (0xff << DMA_STATUS_RX_PKTS_RECEIVED_SHF) 130 #define DMA_STATUS_TX_EN_SYNC 0x00000080 131 #define DMA_STATUS_RX_BUF_A_FUL 0x00000040 132 #define DMA_STATUS_RX_BUF_B_FUL 0x00000020 133 #define DMA_STATUS_RX_TO_INT 0x00000010 134 #define DMA_STATUS_RX_INT 0x00000008 135 #define DMA_STATUS_TX_INT 0x00000004 136 #define DMA_STATUS_MAC_TX_INT 0x00000002 137 #define DMA_STATUS_MAC_RX_INT 0x00000001 138 139 /* DMA TEST/PANIC SWITHES register. */ 140 #define DMA_TEST_LOOPBACK 0x01000000 141 #define DMA_TEST_SW_RESET 0x00000001 142 143 /* MAC CONTROL register. */ 144 #define MAC_CONTROL_EN_MISS_ROLL 0x00002000 145 #define MAC_CONTROL_MISS_ROLL 0x00000400 146 #define MAC_CONTROL_LOOP10 0x00000080 147 #define MAC_CONTROL_CONN_SHF 5 148 #define MAC_CONTROL_CONN_MSK (0x3 << MAC_CONTROL_CONN_SHF) 149 #define MAC_CONTROL_MAC_LOOP 0x00000010 150 #define MAC_CONTROL_FULL_DUP 0x00000008 151 #define MAC_CONTROL_RESET 0x00000004 152 #define MAC_CONTROL_HALT_IMM 0x00000002 153 #define MAC_CONTROL_HALT_REQ 0x00000001 154 155 /* CAM CONTROL register. */ 156 #define CAM_CONTROL_COMP_EN 0x00000010 157 #define CAM_CONTROL_NEG_CAM 0x00000008 158 #define CAM_CONTROL_BROAD_ACC 0x00000004 159 #define CAM_CONTROL_GROUP_ACC 0x00000002 160 #define CAM_CONTROL_STATION_ACC 0x00000001 161 162 /* TRANSMIT CONTROL register. */ 163 #define TX_CTL_EN_COMP 0x00004000 164 #define TX_CTL_EN_TX_PAR 0x00002000 165 #define TX_CTL_EN_LATE_COLL 0x00001000 166 #define TX_CTL_EN_EX_COLL 0x00000800 167 #define TX_CTL_EN_L_CARR 0x00000400 168 #define TX_CTL_EN_EX_DEFER 0x00000200 169 #define TX_CTL_EN_UNDER 0x00000100 170 #define TX_CTL_MII10 0x00000080 171 #define TX_CTL_SD_PAUSE 0x00000040 172 #define TX_CTL_NO_EX_DEF0 0x00000020 173 #define TX_CTL_F_BACK 0x00000010 174 #define TX_CTL_NO_CRC 0x00000008 175 #define TX_CTL_NO_PAD 0x00000004 176 #define TX_CTL_TX_HALT 0x00000002 177 #define TX_CTL_TX_EN 0x00000001 178 179 /* TRANSMIT STATUS register. */ 180 #define TX_STATUS_SQ_ERR 0x00010000 181 #define TX_STATUS_TX_HALTED 0x00008000 182 #define TX_STATUS_COMP 0x00004000 183 #define TX_STATUS_TX_PAR 0x00002000 184 #define TX_STATUS_LATE_COLL 0x00001000 185 #define TX_STATUS_TX10_STAT 0x00000800 186 #define TX_STATUS_L_CARR 0x00000400 187 #define TX_STATUS_EX_DEFER 0x00000200 188 #define TX_STATUS_UNDER 0x00000100 189 #define TX_STATUS_IN_TX 0x00000080 190 #define TX_STATUS_PAUSED 0x00000040 191 #define TX_STATUS_TX_DEFERRED 0x00000020 192 #define TX_STATUS_EX_COLL 0x00000010 193 #define TX_STATUS_TX_COLL_SHF 0 194 #define TX_STATUS_TX_COLL_MSK (0xf << TX_STATUS_TX_COLL_SHF) 195 196 /* RECEIVE CONTROL register. */ 197 #define RX_CTL_EN_GOOD 0x00004000 198 #define RX_CTL_EN_RX_PAR 0x00002000 199 #define RX_CTL_EN_LONG_ERR 0x00000800 200 #define RX_CTL_EN_OVER 0x00000400 201 #define RX_CTL_EN_CRC_ERR 0x00000200 202 #define RX_CTL_EN_ALIGN 0x00000100 203 #define RX_CTL_IGNORE_CRC 0x00000040 204 #define RX_CTL_PASS_CTL 0x00000020 205 #define RX_CTL_STRIP_CRC 0x00000010 206 #define RX_CTL_SHORT_EN 0x00000008 207 #define RX_CTL_LONG_EN 0x00000004 208 #define RX_CTL_RX_HALT 0x00000002 209 #define RX_CTL_RX_EN 0x00000001 210 211 /* RECEIVE STATUS register. */ 212 #define RX_STATUS_RX_HALTED 0x00008000 213 #define RX_STATUS_GOOD 0x00004000 214 #define RX_STATUS_RX_PAR 0x00002000 215 #define RX_STATUS_LONG_ERR 0x00000800 216 #define RX_STATUS_OVERFLOW 0x00000400 217 #define RX_STATUS_CRC_ERR 0x00000200 218 #define RX_STATUS_ALIGN_ERR 0x00000100 219 #define RX_STATUS_RX10_STAT 0x00000080 220 #define RX_STATUS_INT_RX 0x00000040 221 #define RX_STATUS_CTL_RECD 0x00000020 222 223 /* MD_CA register. */ 224 #define MD_CA_PRE_SUP 0x00001000 225 #define MD_CA_BUSY 0x00000800 226 #define MD_CA_WR 0x00000400 227 #define MD_CA_PHY_SHF 5 228 #define MD_CA_PHY_MSK (0x1f << MD_CA_PHY_SHF) 229 #define MD_CA_ADDR_SHF 0 230 #define MD_CA_ADDR_MSK (0x1f << MD_CA_ADDR_SHF) 231 232 /* Tx Status/Control. */ 233 #define TX_STAT_CTL_OWNER_SHF 30 234 #define TX_STAT_CTL_OWNER_MSK (0x3 << TX_STAT_CTL_OWNER_SHF) 235 #define TX_STAT_CTL_FRAME_SHF 27 236 #define TX_STAT_CTL_FRAME_MSK (0x7 << TX_STAT_CTL_FRAME_SHF) 237 #define TX_STAT_CTL_STATUS_SHF 11 238 #define TX_STAT_CTL_STATUS_MSK (0x1ffff << TX_STAT_CTL_STATUS_SHF) 239 #define TX_STAT_CTL_LENGTH_SHF 0 240 #define TX_STAT_CTL_LENGTH_MSK (0x7ff << TX_STAT_CTL_LENGTH_SHF) 241 242 #define TX_STAT_CTL_ERROR_MSK ((TX_STATUS_SQ_ERR | \ 243 TX_STATUS_TX_HALTED | \ 244 TX_STATUS_TX_PAR | \ 245 TX_STATUS_LATE_COLL | \ 246 TX_STATUS_L_CARR | \ 247 TX_STATUS_EX_DEFER | \ 248 TX_STATUS_UNDER | \ 249 TX_STATUS_PAUSED | \ 250 TX_STATUS_TX_DEFERRED | \ 251 TX_STATUS_EX_COLL | \ 252 TX_STATUS_TX_COLL_MSK) \ 253 << TX_STAT_CTL_STATUS_SHF) 254 #define TX_STAT_CTL_INT_AFTER_TX 0x4 255 256 /* Rx Status/Control. */ 257 #define RX_STAT_CTL_OWNER_SHF 30 258 #define RX_STAT_CTL_OWNER_MSK (0x3 << RX_STAT_CTL_OWNER_SHF) 259 #define RX_STAT_CTL_STATUS_SHF 11 260 #define RX_STAT_CTL_STATUS_MSK (0xffff << RX_STAT_CTL_STATUS_SHF) 261 #define RX_STAT_CTL_LENGTH_SHF 0 262 #define RX_STAT_CTL_LENGTH_MSK (0x7ff << RX_STAT_CTL_LENGTH_SHF) 263 264 265 266 /* The SAA9730 (LAN) controller register map, as seen via the PCI-bus. */ 267 #define SAA9730_LAN_REGS_ADDR 0x20400 268 269 struct lan_saa9730_regmap { 270 volatile unsigned int TxBuffA; /* 0x20400 */ 271 volatile unsigned int TxBuffB; /* 0x20404 */ 272 volatile unsigned int RxBuffA; /* 0x20408 */ 273 volatile unsigned int RxBuffB; /* 0x2040c */ 274 volatile unsigned int PacketCount; /* 0x20410 */ 275 volatile unsigned int Ok2Use; /* 0x20414 */ 276 volatile unsigned int LanDmaCtl; /* 0x20418 */ 277 volatile unsigned int Timeout; /* 0x2041c */ 278 volatile unsigned int DmaStatus; /* 0x20420 */ 279 volatile unsigned int DmaTest; /* 0x20424 */ 280 volatile unsigned char filler20428[0x20430 - 0x20428]; 281 volatile unsigned int PauseCount; /* 0x20430 */ 282 volatile unsigned int RemotePauseCount; /* 0x20434 */ 283 volatile unsigned char filler20438[0x20440 - 0x20438]; 284 volatile unsigned int MacCtl; /* 0x20440 */ 285 volatile unsigned int CamCtl; /* 0x20444 */ 286 volatile unsigned int TxCtl; /* 0x20448 */ 287 volatile unsigned int TxStatus; /* 0x2044c */ 288 volatile unsigned int RxCtl; /* 0x20450 */ 289 volatile unsigned int RxStatus; /* 0x20454 */ 290 volatile unsigned int StationMgmtData; /* 0x20458 */ 291 volatile unsigned int StationMgmtCtl; /* 0x2045c */ 292 volatile unsigned int CamAddress; /* 0x20460 */ 293 volatile unsigned int CamData; /* 0x20464 */ 294 volatile unsigned int CamEnable; /* 0x20468 */ 295 volatile unsigned char filler2046c[0x20500 - 0x2046c]; 296 volatile unsigned int DebugPCIMasterAddr; /* 0x20500 */ 297 volatile unsigned int DebugLanTxStateMachine; /* 0x20504 */ 298 volatile unsigned int DebugLanRxStateMachine; /* 0x20508 */ 299 volatile unsigned int DebugLanTxFifoPointers; /* 0x2050c */ 300 volatile unsigned int DebugLanRxFifoPointers; /* 0x20510 */ 301 volatile unsigned int DebugLanCtlStateMachine; /* 0x20514 */ 302 }; 303 typedef volatile struct lan_saa9730_regmap t_lan_saa9730_regmap; 304 305 306 /* EVM interrupt control registers. */ 307 #define EVM_LAN_INT 0x00010000 308 #define EVM_MASTER_EN 0x00000001 309 310 /* The SAA9730 (EVM) controller register map, as seen via the PCI-bus. */ 311 #define SAA9730_EVM_REGS_ADDR 0x02000 312 313 struct evm_saa9730_regmap { 314 volatile unsigned int InterruptStatus1; /* 0x2000 */ 315 volatile unsigned int InterruptEnable1; /* 0x2004 */ 316 volatile unsigned int InterruptMonitor1; /* 0x2008 */ 317 volatile unsigned int Counter; /* 0x200c */ 318 volatile unsigned int CounterThreshold; /* 0x2010 */ 319 volatile unsigned int CounterControl; /* 0x2014 */ 320 volatile unsigned int GpioControl1; /* 0x2018 */ 321 volatile unsigned int InterruptStatus2; /* 0x201c */ 322 volatile unsigned int InterruptEnable2; /* 0x2020 */ 323 volatile unsigned int InterruptMonitor2; /* 0x2024 */ 324 volatile unsigned int GpioControl2; /* 0x2028 */ 325 volatile unsigned int InterruptBlock1; /* 0x202c */ 326 volatile unsigned int InterruptBlock2; /* 0x2030 */ 327 }; 328 typedef volatile struct evm_saa9730_regmap t_evm_saa9730_regmap; 329 330 331 struct lan_saa9730_private { 332 /* Pointer for the SAA9730 LAN controller register set. */ 333 t_lan_saa9730_regmap *lan_saa9730_regs; 334 335 /* Pointer to the SAA9730 EVM register. */ 336 t_evm_saa9730_regmap *evm_saa9730_regs; 337 338 /* TRUE if the next buffer to write is RxBuffA, FALSE if RxBuffB. */ 339 unsigned char NextRcvToUseIsA; 340 /* Rcv buffer Index. */ 341 unsigned char NextRcvPacketIndex; 342 343 /* Index of next packet to use in that buffer. */ 344 unsigned char NextTxmPacketIndex; 345 /* Next buffer index. */ 346 unsigned char NextTxmBufferIndex; 347 348 /* Index of first pending packet ready to send. */ 349 unsigned char PendingTxmPacketIndex; 350 /* Pending buffer index. */ 351 unsigned char PendingTxmBufferIndex; 352 353 unsigned char DmaRcvPackets; 354 unsigned char DmaTxmPackets; 355 356 unsigned char RcvAIndex; /* index into RcvBufferSpace[] for Blk A */ 357 unsigned char RcvBIndex; /* index into RcvBufferSpace[] for Blk B */ 358 359 unsigned int 360 TxmBuffer[LAN_SAA9730_BUFFERS][LAN_SAA9730_TXM_Q_SIZE]; 361 unsigned int 362 RcvBuffer[LAN_SAA9730_BUFFERS][LAN_SAA9730_RCV_Q_SIZE]; 363 unsigned int TxBufferFree[LAN_SAA9730_BUFFERS]; 364 365 unsigned char PhysicalAddress[LAN_SAA9730_CAM_ENTRIES][6]; 366 367 struct net_device_stats stats; 368 }; 369 370 #endif /* _SAA9730_H */ 371