1 /*
2  * ATI Mach64 Register Definitions
3  *
4  * Copyright (C) 1997 Michael AK Tesch
5  *  written with much help from Jon Howell
6  *
7  * Updated for 3D RAGE PRO and 3D RAGE Mobility by Geert Uytterhoeven
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License
11  * as published by the Free Software Foundation; either version
12  * 2 of the License, or (at your option) any later version.
13  */
14 
15 /*
16  * most of the rest of this file comes from ATI sample code
17  */
18 #ifndef REGMACH64_H
19 #define REGMACH64_H
20 
21 /* NON-GUI MEMORY MAPPED Registers - expressed in BYTE offsets */
22 
23 /* Accelerator CRTC */
24 #define CRTC_H_TOTAL_DISP	0x0000	/* Dword offset 0_00 */
25 #define CRTC2_H_TOTAL_DISP	0x0000	/* Dword offset 0_00 */
26 #define CRTC_H_SYNC_STRT_WID	0x0004	/* Dword offset 0_01 */
27 #define CRTC2_H_SYNC_STRT_WID	0x0004	/* Dword offset 0_01 */
28 #define CRTC_H_SYNC_STRT	0x0004
29 #define CRTC2_H_SYNC_STRT	0x0004
30 #define CRTC_H_SYNC_DLY		0x0005
31 #define CRTC2_H_SYNC_DLY	0x0005
32 #define CRTC_H_SYNC_WID		0x0006
33 #define CRTC2_H_SYNC_WID	0x0006
34 #define CRTC_V_TOTAL_DISP	0x0008	/* Dword offset 0_02 */
35 #define CRTC2_V_TOTAL_DISP	0x0008	/* Dword offset 0_02 */
36 #define CRTC_V_TOTAL		0x0008
37 #define CRTC2_V_TOTAL		0x0008
38 #define CRTC_V_DISP		0x000A
39 #define CRTC2_V_DISP		0x000A
40 #define CRTC_V_SYNC_STRT_WID	0x000C	/* Dword offset 0_03 */
41 #define CRTC2_V_SYNC_STRT_WID	0x000C	/* Dword offset 0_03 */
42 #define CRTC_V_SYNC_STRT	0x000C
43 #define CRTC2_V_SYNC_STRT	0x000C
44 #define CRTC_V_SYNC_WID		0x000E
45 #define CRTC2_V_SYNC_WID	0x000E
46 #define CRTC_VLINE_CRNT_VLINE	0x0010	/* Dword offset 0_04 */
47 #define CRTC2_VLINE_CRNT_VLINE	0x0010	/* Dword offset 0_04 */
48 #define CRTC_OFF_PITCH		0x0014	/* Dword offset 0_05 */
49 #define CRTC_OFFSET		0x0014
50 #define CRTC_PITCH		0x0016
51 #define CRTC_INT_CNTL		0x0018	/* Dword offset 0_06 */
52 #define CRTC_GEN_CNTL		0x001C	/* Dword offset 0_07 */
53 #define CRTC_PIX_WIDTH		0x001D
54 #define CRTC_FIFO		0x001E
55 #define CRTC_EXT_DISP		0x001F
56 
57 /* Memory Buffer Control */
58 #define DSP_CONFIG		0x0020	/* Dword offset 0_08 */
59 #define PM_DSP_CONFIG		0x0020	/* Dword offset 0_08 (Mobility Only) */
60 #define DSP_ON_OFF		0x0024	/* Dword offset 0_09 */
61 #define PM_DSP_ON_OFF		0x0024	/* Dword offset 0_09 (Mobility Only) */
62 #define TIMER_CONFIG		0x0028	/* Dword offset 0_0A */
63 #define MEM_BUF_CNTL		0x002C	/* Dword offset 0_0B */
64 #define MEM_ADDR_CONFIG		0x0034	/* Dword offset 0_0D */
65 
66 /* Accelerator CRTC */
67 #define CRT_TRAP		0x0038	/* Dword offset 0_0E */
68 
69 #define I2C_CNTL_0		0x003C	/* Dword offset 0_0F */
70 
71 /* Overscan */
72 #define OVR_CLR			0x0040	/* Dword offset 0_10 */
73 #define OVR2_CLR		0x0040	/* Dword offset 0_10 */
74 #define OVR_WID_LEFT_RIGHT	0x0044	/* Dword offset 0_11 */
75 #define OVR2_WID_LEFT_RIGHT	0x0044	/* Dword offset 0_11 */
76 #define OVR_WID_TOP_BOTTOM	0x0048	/* Dword offset 0_12 */
77 #define OVR2_WID_TOP_BOTTOM	0x0048	/* Dword offset 0_12 */
78 
79 /* Memory Buffer Control */
80 #define VGA_DSP_CONFIG		0x004C	/* Dword offset 0_13 */
81 #define PM_VGA_DSP_CONFIG	0x004C	/* Dword offset 0_13 (Mobility Only) */
82 #define VGA_DSP_ON_OFF		0x0050	/* Dword offset 0_14 */
83 #define PM_VGA_DSP_ON_OFF	0x0050	/* Dword offset 0_14 (Mobility Only) */
84 #define DSP2_CONFIG		0x0054	/* Dword offset 0_15 */
85 #define PM_DSP2_CONFIG		0x0054	/* Dword offset 0_15 (Mobility Only) */
86 #define DSP2_ON_OFF		0x0058	/* Dword offset 0_16 */
87 #define PM_DSP2_ON_OFF		0x0058	/* Dword offset 0_16 (Mobility Only) */
88 
89 /* Accelerator CRTC */
90 #define CRTC2_OFF_PITCH		0x005C	/* Dword offset 0_17 */
91 
92 /* Hardware Cursor */
93 #define CUR_CLR0		0x0060	/* Dword offset 0_18 */
94 #define CUR2_CLR0		0x0060	/* Dword offset 0_18 */
95 #define CUR_CLR1		0x0064	/* Dword offset 0_19 */
96 #define CUR2_CLR1		0x0064	/* Dword offset 0_19 */
97 #define CUR_OFFSET		0x0068	/* Dword offset 0_1A */
98 #define CUR2_OFFSET		0x0068	/* Dword offset 0_1A */
99 #define CUR_HORZ_VERT_POSN	0x006C	/* Dword offset 0_1B */
100 #define CUR2_HORZ_VERT_POSN	0x006C	/* Dword offset 0_1B */
101 #define CUR_HORZ_VERT_OFF	0x0070	/* Dword offset 0_1C */
102 #define CUR2_HORZ_VERT_OFF	0x0070	/* Dword offset 0_1C */
103 
104 #define CONFIG_PANEL_LG		0x0074	/* Dword offset 0_1D */
105 
106 /* General I/O Control */
107 #define GP_IO			0x0078	/* Dword offset 0_1E */
108 
109 /* Test and Debug */
110 #define HW_DEBUG		0x007C	/* Dword offset 0_1F */
111 
112 /* Scratch Pad and Test */
113 #define SCRATCH_REG0		0x0080	/* Dword offset 0_20 */
114 #define SCRATCH_REG1		0x0084	/* Dword offset 0_21 */
115 #define SCRATCH_REG2		0x0088	/* Dword offset 0_22 */
116 #define SCRATCH_REG3		0x008C	/* Dword offset 0_23 */
117 
118 /* Clock Control */
119 #define CLOCK_CNTL		0x0090	/* Dword offset 0_24 */
120 #define CLOCK_SEL_CNTL		0x0090	/* Dword offset 0_24 */
121 
122 /* Configuration */
123 #define CONFIG_STAT1		0x0094	/* Dword offset 0_25 */
124 #define CONFIG_STAT2		0x0098	/* Dword offset 0_26 */
125 
126 /* Bus Control */
127 #define BUS_CNTL		0x00A0	/* Dword offset 0_28 */
128 
129 #define LCD_INDEX		0x00A4	/* Dword offset 0_29 */
130 #define LCD_DATA		0x00A8	/* Dword offset 0_2A */
131 
132 /* Memory Control */
133 #define EXT_MEM_CNTL		0x00AC	/* Dword offset 0_2B */
134 #define MEM_CNTL		0x00B0	/* Dword offset 0_2C */
135 #define MEM_VGA_WP_SEL		0x00B4	/* Dword offset 0_2D */
136 #define MEM_VGA_RP_SEL		0x00B8	/* Dword offset 0_2E */
137 
138 #define I2C_CNTL_1		0x00BC	/* Dword offset 0_2F */
139 
140 /* DAC Control */
141 #define DAC_REGS		0x00C0	/* Dword offset 0_30 */
142 #define DAC_W_INDEX		0x00C0	/* Dword offset 0_30 */
143 #define DAC_DATA		0x00C1	/* Dword offset 0_30 */
144 #define DAC_MASK		0x00C2	/* Dword offset 0_30 */
145 #define DAC_R_INDEX		0x00C3	/* Dword offset 0_30 */
146 #define DAC_CNTL		0x00C4	/* Dword offset 0_31 */
147 
148 #define EXT_DAC_REGS		0x00C8	/* Dword offset 0_32 */
149 
150 /* Test and Debug */
151 #define GEN_TEST_CNTL		0x00D0	/* Dword offset 0_34 */
152 
153 /* Custom Macros */
154 #define CUSTOM_MACRO_CNTL	0x00D4	/* Dword offset 0_35 */
155 
156 #define LCD_GEN_CNTL_LG		0x00D4	/* Dword offset 0_35 */
157 
158 #define POWER_MANAGEMENT_LG	0x00D8	/* Dword offset 0_36 (LG) */
159 
160 /* Configuration */
161 #define CONFIG_CNTL		0x00DC	/* Dword offset 0_37 (CT, ET, VT) */
162 #define CONFIG_CHIP_ID		0x00E0	/* Dword offset 0_38 */
163 #define CONFIG_STAT0		0x00E4	/* Dword offset 0_39 */
164 
165 /* Test and Debug */
166 #define CRC_SIG			0x00E8	/* Dword offset 0_3A */
167 #define CRC2_SIG		0x00E8	/* Dword offset 0_3A */
168 
169 
170 /* GUI MEMORY MAPPED Registers */
171 
172 /* Draw Engine Destination Trajectory */
173 #define DST_OFF_PITCH		0x0100	/* Dword offset 0_40 */
174 #define DST_X			0x0104	/* Dword offset 0_41 */
175 #define DST_Y			0x0108	/* Dword offset 0_42 */
176 #define DST_Y_X			0x010C	/* Dword offset 0_43 */
177 #define DST_WIDTH		0x0110	/* Dword offset 0_44 */
178 #define DST_HEIGHT		0x0114	/* Dword offset 0_45 */
179 #define DST_HEIGHT_WIDTH	0x0118	/* Dword offset 0_46 */
180 #define DST_X_WIDTH		0x011C	/* Dword offset 0_47 */
181 #define DST_BRES_LNTH		0x0120	/* Dword offset 0_48 */
182 #define DST_BRES_ERR		0x0124	/* Dword offset 0_49 */
183 #define DST_BRES_INC		0x0128	/* Dword offset 0_4A */
184 #define DST_BRES_DEC		0x012C	/* Dword offset 0_4B */
185 #define DST_CNTL		0x0130	/* Dword offset 0_4C */
186 #define DST_Y_X__ALIAS__	0x0134	/* Dword offset 0_4D */
187 #define TRAIL_BRES_ERR		0x0138	/* Dword offset 0_4E */
188 #define TRAIL_BRES_INC		0x013C	/* Dword offset 0_4F */
189 #define TRAIL_BRES_DEC		0x0140	/* Dword offset 0_50 */
190 #define LEAD_BRES_LNTH		0x0144	/* Dword offset 0_51 */
191 #define Z_OFF_PITCH		0x0148	/* Dword offset 0_52 */
192 #define Z_CNTL			0x014C	/* Dword offset 0_53 */
193 #define ALPHA_TST_CNTL		0x0150	/* Dword offset 0_54 */
194 #define SECONDARY_STW_EXP	0x0158	/* Dword offset 0_56 */
195 #define SECONDARY_S_X_INC	0x015C	/* Dword offset 0_57 */
196 #define SECONDARY_S_Y_INC	0x0160	/* Dword offset 0_58 */
197 #define SECONDARY_S_START	0x0164	/* Dword offset 0_59 */
198 #define SECONDARY_W_X_INC	0x0168	/* Dword offset 0_5A */
199 #define SECONDARY_W_Y_INC	0x016C	/* Dword offset 0_5B */
200 #define SECONDARY_W_START	0x0170	/* Dword offset 0_5C */
201 #define SECONDARY_T_X_INC	0x0174	/* Dword offset 0_5D */
202 #define SECONDARY_T_Y_INC	0x0178	/* Dword offset 0_5E */
203 #define SECONDARY_T_START	0x017C	/* Dword offset 0_5F */
204 
205 /* Draw Engine Source Trajectory */
206 #define SRC_OFF_PITCH		0x0180	/* Dword offset 0_60 */
207 #define SRC_X			0x0184	/* Dword offset 0_61 */
208 #define SRC_Y			0x0188	/* Dword offset 0_62 */
209 #define SRC_Y_X			0x018C	/* Dword offset 0_63 */
210 #define SRC_WIDTH1		0x0190	/* Dword offset 0_64 */
211 #define SRC_HEIGHT1		0x0194	/* Dword offset 0_65 */
212 #define SRC_HEIGHT1_WIDTH1	0x0198	/* Dword offset 0_66 */
213 #define SRC_X_START		0x019C	/* Dword offset 0_67 */
214 #define SRC_Y_START		0x01A0	/* Dword offset 0_68 */
215 #define SRC_Y_X_START		0x01A4	/* Dword offset 0_69 */
216 #define SRC_WIDTH2		0x01A8	/* Dword offset 0_6A */
217 #define SRC_HEIGHT2		0x01AC	/* Dword offset 0_6B */
218 #define SRC_HEIGHT2_WIDTH2	0x01B0	/* Dword offset 0_6C */
219 #define SRC_CNTL		0x01B4	/* Dword offset 0_6D */
220 
221 #define SCALE_OFF		0x01C0	/* Dword offset 0_70 */
222 #define SECONDARY_SCALE_OFF	0x01C4	/* Dword offset 0_71 */
223 
224 #define TEX_0_OFF		0x01C0	/* Dword offset 0_70 */
225 #define TEX_1_OFF		0x01C4	/* Dword offset 0_71 */
226 #define TEX_2_OFF		0x01C8	/* Dword offset 0_72 */
227 #define TEX_3_OFF		0x01CC	/* Dword offset 0_73 */
228 #define TEX_4_OFF		0x01D0	/* Dword offset 0_74 */
229 #define TEX_5_OFF		0x01D4	/* Dword offset 0_75 */
230 #define TEX_6_OFF		0x01D8	/* Dword offset 0_76 */
231 #define TEX_7_OFF		0x01DC	/* Dword offset 0_77 */
232 
233 #define SCALE_WIDTH		0x01DC	/* Dword offset 0_77 */
234 #define SCALE_HEIGHT		0x01E0	/* Dword offset 0_78 */
235 
236 #define TEX_8_OFF		0x01E0	/* Dword offset 0_78 */
237 #define TEX_9_OFF		0x01E4	/* Dword offset 0_79 */
238 #define TEX_10_OFF		0x01E8	/* Dword offset 0_7A */
239 #define S_Y_INC			0x01EC	/* Dword offset 0_7B */
240 
241 #define SCALE_PITCH		0x01EC	/* Dword offset 0_7B */
242 #define SCALE_X_INC		0x01F0	/* Dword offset 0_7C */
243 
244 #define RED_X_INC		0x01F0	/* Dword offset 0_7C */
245 #define GREEN_X_INC		0x01F4	/* Dword offset 0_7D */
246 
247 #define SCALE_Y_INC		0x01F4	/* Dword offset 0_7D */
248 #define SCALE_VACC		0x01F8	/* Dword offset 0_7E */
249 #define SCALE_3D_CNTL		0x01FC	/* Dword offset 0_7F */
250 
251 /* Host Data */
252 #define HOST_DATA0		0x0200	/* Dword offset 0_80 */
253 #define HOST_DATA1		0x0204	/* Dword offset 0_81 */
254 #define HOST_DATA2		0x0208	/* Dword offset 0_82 */
255 #define HOST_DATA3		0x020C	/* Dword offset 0_83 */
256 #define HOST_DATA4		0x0210	/* Dword offset 0_84 */
257 #define HOST_DATA5		0x0214	/* Dword offset 0_85 */
258 #define HOST_DATA6		0x0218	/* Dword offset 0_86 */
259 #define HOST_DATA7		0x021C	/* Dword offset 0_87 */
260 #define HOST_DATA8		0x0220	/* Dword offset 0_88 */
261 #define HOST_DATA9		0x0224	/* Dword offset 0_89 */
262 #define HOST_DATAA		0x0228	/* Dword offset 0_8A */
263 #define HOST_DATAB		0x022C	/* Dword offset 0_8B */
264 #define HOST_DATAC		0x0230	/* Dword offset 0_8C */
265 #define HOST_DATAD		0x0234	/* Dword offset 0_8D */
266 #define HOST_DATAE		0x0238	/* Dword offset 0_8E */
267 #define HOST_DATAF		0x023C	/* Dword offset 0_8F */
268 #define HOST_CNTL		0x0240	/* Dword offset 0_90 */
269 
270 /* GUI Bus Mastering */
271 #define BM_HOSTDATA		0x0244	/* Dword offset 0_91 */
272 #define BM_ADDR			0x0248	/* Dword offset 0_92 */
273 #define BM_DATA			0x0248	/* Dword offset 0_92 */
274 #define BM_GUI_TABLE_CMD	0x024C	/* Dword offset 0_93 */
275 
276 /* Pattern */
277 #define PAT_REG0		0x0280	/* Dword offset 0_A0 */
278 #define PAT_REG1		0x0284	/* Dword offset 0_A1 */
279 #define PAT_CNTL		0x0288	/* Dword offset 0_A2 */
280 
281 /* Scissors */
282 #define SC_LEFT			0x02A0	/* Dword offset 0_A8 */
283 #define SC_RIGHT		0x02A4	/* Dword offset 0_A9 */
284 #define SC_LEFT_RIGHT		0x02A8	/* Dword offset 0_AA */
285 #define SC_TOP			0x02AC	/* Dword offset 0_AB */
286 #define SC_BOTTOM		0x02B0	/* Dword offset 0_AC */
287 #define SC_TOP_BOTTOM		0x02B4	/* Dword offset 0_AD */
288 
289 /* Data Path */
290 #define USR1_DST_OFF_PITCH	0x02B8	/* Dword offset 0_AE */
291 #define USR2_DST_OFF_PITCH	0x02BC	/* Dword offset 0_AF */
292 #define DP_BKGD_CLR		0x02C0	/* Dword offset 0_B0 */
293 #define DP_FOG_CLR		0x02C4	/* Dword offset 0_B1 */
294 #define DP_FRGD_CLR		0x02C4	/* Dword offset 0_B1 */
295 #define DP_WRITE_MASK		0x02C8	/* Dword offset 0_B2 */
296 #define DP_CHAIN_MASK		0x02CC	/* Dword offset 0_B3 */
297 #define DP_PIX_WIDTH		0x02D0	/* Dword offset 0_B4 */
298 #define DP_MIX			0x02D4	/* Dword offset 0_B5 */
299 #define DP_SRC			0x02D8	/* Dword offset 0_B6 */
300 #define DP_FRGD_CLR_MIX		0x02DC	/* Dword offset 0_B7 */
301 #define DP_FRGD_BKGD_CLR	0x02E0	/* Dword offset 0_B8 */
302 
303 /* Draw Engine Destination Trajectory */
304 #define DST_X_Y			0x02E8	/* Dword offset 0_BA */
305 #define DST_WIDTH_HEIGHT	0x02EC	/* Dword offset 0_BB */
306 
307 /* Data Path */
308 #define USR_DST_PICTH		0x02F0	/* Dword offset 0_BC */
309 #define DP_SET_GUI_ENGINE2	0x02F8	/* Dword offset 0_BE */
310 #define DP_SET_GUI_ENGINE	0x02FC	/* Dword offset 0_BF */
311 
312 /* Color Compare */
313 #define CLR_CMP_CLR		0x0300	/* Dword offset 0_C0 */
314 #define CLR_CMP_MASK		0x0304	/* Dword offset 0_C1 */
315 #define CLR_CMP_CNTL		0x0308	/* Dword offset 0_C2 */
316 
317 /* Command FIFO */
318 #define FIFO_STAT		0x0310	/* Dword offset 0_C4 */
319 
320 #define CONTEXT_MASK		0x0320	/* Dword offset 0_C8 */
321 #define CONTEXT_LOAD_CNTL	0x032C	/* Dword offset 0_CB */
322 
323 /* Engine Control */
324 #define GUI_TRAJ_CNTL		0x0330	/* Dword offset 0_CC */
325 
326 /* Engine Status/FIFO */
327 #define GUI_STAT		0x0338	/* Dword offset 0_CE */
328 
329 #define TEX_PALETTE_INDEX	0x0340	/* Dword offset 0_D0 */
330 #define STW_EXP			0x0344	/* Dword offset 0_D1 */
331 #define LOG_MAX_INC		0x0348	/* Dword offset 0_D2 */
332 #define S_X_INC			0x034C	/* Dword offset 0_D3 */
333 #define S_Y_INC__ALIAS__	0x0350	/* Dword offset 0_D4 */
334 
335 #define SCALE_PITCH__ALIAS__	0x0350	/* Dword offset 0_D4 */
336 
337 #define S_START			0x0354	/* Dword offset 0_D5 */
338 #define W_X_INC			0x0358	/* Dword offset 0_D6 */
339 #define W_Y_INC			0x035C	/* Dword offset 0_D7 */
340 #define W_START			0x0360	/* Dword offset 0_D8 */
341 #define T_X_INC			0x0364	/* Dword offset 0_D9 */
342 #define T_Y_INC			0x0368	/* Dword offset 0_DA */
343 
344 #define SECONDARY_SCALE_PITCH	0x0368	/* Dword offset 0_DA */
345 
346 #define T_START			0x036C	/* Dword offset 0_DB */
347 #define TEX_SIZE_PITCH		0x0370	/* Dword offset 0_DC */
348 #define TEX_CNTL		0x0374	/* Dword offset 0_DD */
349 #define SECONDARY_TEX_OFFSET	0x0378	/* Dword offset 0_DE */
350 #define TEX_PALETTE		0x037C	/* Dword offset 0_DF */
351 
352 #define SCALE_PITCH_BOTH	0x0380	/* Dword offset 0_E0 */
353 #define SECONDARY_SCALE_OFF_ACC	0x0384	/* Dword offset 0_E1 */
354 #define SCALE_OFF_ACC		0x0388	/* Dword offset 0_E2 */
355 #define SCALE_DST_Y_X		0x038C	/* Dword offset 0_E3 */
356 
357 /* Draw Engine Destination Trajectory */
358 #define COMPOSITE_SHADOW_ID	0x0398	/* Dword offset 0_E6 */
359 
360 #define SECONDARY_SCALE_X_INC	0x039C	/* Dword offset 0_E7 */
361 
362 #define SPECULAR_RED_X_INC	0x039C	/* Dword offset 0_E7 */
363 #define SPECULAR_RED_Y_INC	0x03A0	/* Dword offset 0_E8 */
364 #define SPECULAR_RED_START	0x03A4	/* Dword offset 0_E9 */
365 
366 #define SECONDARY_SCALE_HACC	0x03A4	/* Dword offset 0_E9 */
367 
368 #define SPECULAR_GREEN_X_INC	0x03A8	/* Dword offset 0_EA */
369 #define SPECULAR_GREEN_Y_INC	0x03AC	/* Dword offset 0_EB */
370 #define SPECULAR_GREEN_START	0x03B0	/* Dword offset 0_EC */
371 #define SPECULAR_BLUE_X_INC	0x03B4	/* Dword offset 0_ED */
372 #define SPECULAR_BLUE_Y_INC	0x03B8	/* Dword offset 0_EE */
373 #define SPECULAR_BLUE_START	0x03BC	/* Dword offset 0_EF */
374 
375 #define SCALE_X_INC__ALIAS__	0x03C0	/* Dword offset 0_F0 */
376 
377 #define RED_X_INC__ALIAS__	0x03C0	/* Dword offset 0_F0 */
378 #define RED_Y_INC		0x03C4	/* Dword offset 0_F1 */
379 #define RED_START		0x03C8	/* Dword offset 0_F2 */
380 
381 #define SCALE_HACC		0x03C8	/* Dword offset 0_F2 */
382 #define SCALE_Y_INC__ALIAS__	0x03CC	/* Dword offset 0_F3 */
383 
384 #define GREEN_X_INC__ALIAS__	0x03CC	/* Dword offset 0_F3 */
385 #define GREEN_Y_INC		0x03D0	/* Dword offset 0_F4 */
386 
387 #define SECONDARY_SCALE_Y_INC	0x03D0	/* Dword offset 0_F4 */
388 #define SECONDARY_SCALE_VACC	0x03D4	/* Dword offset 0_F5 */
389 
390 #define GREEN_START		0x03D4	/* Dword offset 0_F5 */
391 #define BLUE_X_INC		0x03D8	/* Dword offset 0_F6 */
392 #define BLUE_Y_INC		0x03DC	/* Dword offset 0_F7 */
393 #define BLUE_START		0x03E0	/* Dword offset 0_F8 */
394 #define Z_X_INC			0x03E4	/* Dword offset 0_F9 */
395 #define Z_Y_INC			0x03E8	/* Dword offset 0_FA */
396 #define Z_START			0x03EC	/* Dword offset 0_FB */
397 #define ALPHA_X_INC		0x03F0	/* Dword offset 0_FC */
398 #define FOG_X_INC		0x03F0	/* Dword offset 0_FC */
399 #define ALPHA_Y_INC		0x03F4	/* Dword offset 0_FD */
400 #define FOG_Y_INC		0x03F4	/* Dword offset 0_FD */
401 #define ALPHA_START		0x03F8	/* Dword offset 0_FE */
402 #define FOG_START		0x03F8	/* Dword offset 0_FE */
403 
404 #define OVERLAY_Y_X_START		0x0400	/* Dword offset 1_00 */
405 #define OVERLAY_Y_X_END			0x0404	/* Dword offset 1_01 */
406 #define OVERLAY_VIDEO_KEY_CLR		0x0408	/* Dword offset 1_02 */
407 #define OVERLAY_VIDEO_KEY_MSK		0x040C	/* Dword offset 1_03 */
408 #define OVERLAY_GRAPHICS_KEY_CLR	0x0410	/* Dword offset 1_04 */
409 #define OVERLAY_GRAPHICS_KEY_MSK	0x0414	/* Dword offset 1_05 */
410 #define OVERLAY_KEY_CNTL		0x0418	/* Dword offset 1_06 */
411 
412 #define OVERLAY_SCALE_INC	0x0420	/* Dword offset 1_08 */
413 #define OVERLAY_SCALE_CNTL	0x0424	/* Dword offset 1_09 */
414 #define SCALER_HEIGHT_WIDTH	0x0428	/* Dword offset 1_0A */
415 #define SCALER_TEST		0x042C	/* Dword offset 1_0B */
416 #define SCALER_BUF0_OFFSET	0x0434	/* Dword offset 1_0D */
417 #define SCALER_BUF1_OFFSET	0x0438	/* Dword offset 1_0E */
418 #define SCALE_BUF_PITCH		0x043C	/* Dword offset 1_0F */
419 
420 #define CAPTURE_START_END	0x0440	/* Dword offset 1_10 */
421 #define CAPTURE_X_WIDTH		0x0444	/* Dword offset 1_11 */
422 #define VIDEO_FORMAT		0x0448	/* Dword offset 1_12 */
423 #define VBI_START_END		0x044C	/* Dword offset 1_13 */
424 #define CAPTURE_CONFIG		0x0450	/* Dword offset 1_14 */
425 #define TRIG_CNTL		0x0454	/* Dword offset 1_15 */
426 
427 #define OVERLAY_EXCLUSIVE_HORZ	0x0458	/* Dword offset 1_16 */
428 #define OVERLAY_EXCLUSIVE_VERT	0x045C	/* Dword offset 1_17 */
429 
430 #define VAL_WIDTH		0x0460	/* Dword offset 1_18 */
431 #define CAPTURE_DEBUG		0x0464	/* Dword offset 1_19 */
432 #define VIDEO_SYNC_TEST		0x0468	/* Dword offset 1_1A */
433 
434 /* GenLocking */
435 #define SNAPSHOT_VH_COUNTS	0x0470	/* Dword offset 1_1C */
436 #define SNAPSHOT_F_COUNT	0x0474	/* Dword offset 1_1D */
437 #define N_VIF_COUNT		0x0478	/* Dword offset 1_1E */
438 #define SNAPSHOT_VIF_COUNT	0x047C	/* Dword offset 1_1F */
439 
440 #define CAPTURE_BUF0_OFFSET	0x0480	/* Dword offset 1_20 */
441 #define CAPTURE_BUF1_OFFSET	0x0484	/* Dword offset 1_21 */
442 #define CAPTURE_BUF_PITCH	0x0488	/* Dword offset 1_22 */
443 
444 /* GenLocking */
445 #define SNAPSHOT2_VH_COUNTS	0x04B0	/* Dword offset 1_2C */
446 #define SNAPSHOT2_F_COUNT	0x04B4	/* Dword offset 1_2D */
447 #define N_VIF2_COUNT		0x04B8	/* Dword offset 1_2E */
448 #define SNAPSHOT2_VIF_COUNT	0x04BC	/* Dword offset 1_2F */
449 
450 #define MPP_CONFIG		0x04C0	/* Dword offset 1_30 */
451 #define MPP_STROBE_SEQ		0x04C4	/* Dword offset 1_31 */
452 #define MPP_ADDR		0x04C8	/* Dword offset 1_32 */
453 #define MPP_DATA		0x04CC	/* Dword offset 1_33 */
454 #define TVO_CNTL		0x0500	/* Dword offset 1_40 */
455 
456 /* Test and Debug */
457 #define CRT_HORZ_VERT_LOAD	0x0544	/* Dword offset 1_51 */
458 
459 /* AGP */
460 #define AGP_BASE		0x0548	/* Dword offset 1_52 */
461 #define AGP_CNTL		0x054C	/* Dword offset 1_53 */
462 
463 #define SCALER_COLOUR_CNTL	0x0550	/* Dword offset 1_54 */
464 #define SCALER_H_COEFF0		0x0554	/* Dword offset 1_55 */
465 #define SCALER_H_COEFF1		0x0558	/* Dword offset 1_56 */
466 #define SCALER_H_COEFF2		0x055C	/* Dword offset 1_57 */
467 #define SCALER_H_COEFF3		0x0560	/* Dword offset 1_58 */
468 #define SCALER_H_COEFF4		0x0564	/* Dword offset 1_59 */
469 
470 /* Command FIFO */
471 #define GUI_CMDFIFO_DEBUG	0x0570	/* Dword offset 1_5C */
472 #define GUI_CMDFIFO_DATA	0x0574	/* Dword offset 1_5D */
473 #define GUI_CNTL		0x0578	/* Dword offset 1_5E */
474 
475 /* Bus Mastering */
476 #define BM_FRAME_BUF_OFFSET	0x0580	/* Dword offset 1_60 */
477 #define BM_SYSTEM_MEM_ADDR	0x0584	/* Dword offset 1_61 */
478 #define BM_COMMAND		0x0588	/* Dword offset 1_62 */
479 #define BM_STATUS		0x058C	/* Dword offset 1_63 */
480 #define BM_GUI_TABLE		0x05B8	/* Dword offset 1_6E */
481 #define BM_SYSTEM_TABLE		0x05BC	/* Dword offset 1_6F */
482 
483 #define SCALER_BUF0_OFFSET_U	0x05D4	/* Dword offset 1_75 */
484 #define SCALER_BUF0_OFFSET_V	0x05D8	/* Dword offset 1_76 */
485 #define SCALER_BUF1_OFFSET_U	0x05DC	/* Dword offset 1_77 */
486 #define SCALER_BUF1_OFFSET_V	0x05E0	/* Dword offset 1_78 */
487 
488 /* Setup Engine */
489 #define VERTEX_1_S		0x0640	/* Dword offset 1_90 */
490 #define VERTEX_1_T		0x0644	/* Dword offset 1_91 */
491 #define VERTEX_1_W		0x0648	/* Dword offset 1_92 */
492 #define VERTEX_1_SPEC_ARGB	0x064C	/* Dword offset 1_93 */
493 #define VERTEX_1_Z		0x0650	/* Dword offset 1_94 */
494 #define VERTEX_1_ARGB		0x0654	/* Dword offset 1_95 */
495 #define VERTEX_1_X_Y		0x0658	/* Dword offset 1_96 */
496 #define ONE_OVER_AREA		0x065C	/* Dword offset 1_97 */
497 #define VERTEX_2_S		0x0660	/* Dword offset 1_98 */
498 #define VERTEX_2_T		0x0664	/* Dword offset 1_99 */
499 #define VERTEX_2_W		0x0668	/* Dword offset 1_9A */
500 #define VERTEX_2_SPEC_ARGB	0x066C	/* Dword offset 1_9B */
501 #define VERTEX_2_Z		0x0670	/* Dword offset 1_9C */
502 #define VERTEX_2_ARGB		0x0674	/* Dword offset 1_9D */
503 #define VERTEX_2_X_Y		0x0678	/* Dword offset 1_9E */
504 #define ONE_OVER_AREA		0x065C	/* Dword offset 1_9F */
505 #define VERTEX_3_S		0x0680	/* Dword offset 1_A0 */
506 #define VERTEX_3_T		0x0684	/* Dword offset 1_A1 */
507 #define VERTEX_3_W		0x0688	/* Dword offset 1_A2 */
508 #define VERTEX_3_SPEC_ARGB	0x068C	/* Dword offset 1_A3 */
509 #define VERTEX_3_Z		0x0690	/* Dword offset 1_A4 */
510 #define VERTEX_3_ARGB		0x0694	/* Dword offset 1_A5 */
511 #define VERTEX_3_X_Y		0x0698	/* Dword offset 1_A6 */
512 #define ONE_OVER_AREA		0x065C	/* Dword offset 1_A7 */
513 #define VERTEX_1_S		0x0640	/* Dword offset 1_AB */
514 #define VERTEX_1_T		0x0644	/* Dword offset 1_AC */
515 #define VERTEX_1_W		0x0648	/* Dword offset 1_AD */
516 #define VERTEX_2_S		0x0660	/* Dword offset 1_AE */
517 #define VERTEX_2_T		0x0664	/* Dword offset 1_AF */
518 #define VERTEX_2_W		0x0668	/* Dword offset 1_B0 */
519 #define VERTEX_3_SECONDARY_S	0x06C0	/* Dword offset 1_B0 */
520 #define VERTEX_3_S		0x0680	/* Dword offset 1_B1 */
521 #define VERTEX_3_SECONDARY_T	0x06C4	/* Dword offset 1_B1 */
522 #define VERTEX_3_T		0x0684	/* Dword offset 1_B2 */
523 #define VERTEX_3_SECONDARY_W	0x06C8	/* Dword offset 1_B2 */
524 #define VERTEX_3_W		0x0688	/* Dword offset 1_B3 */
525 #define VERTEX_1_SPEC_ARGB	0x064C	/* Dword offset 1_B4 */
526 #define VERTEX_2_SPEC_ARGB	0x066C	/* Dword offset 1_B5 */
527 #define VERTEX_3_SPEC_ARGB	0x068C	/* Dword offset 1_B6 */
528 #define VERTEX_1_Z		0x0650	/* Dword offset 1_B7 */
529 #define VERTEX_2_Z		0x0670	/* Dword offset 1_B8 */
530 #define VERTEX_3_Z		0x0690	/* Dword offset 1_B9 */
531 #define VERTEX_1_ARGB		0x0654	/* Dword offset 1_BA */
532 #define VERTEX_2_ARGB		0x0674	/* Dword offset 1_BB */
533 #define VERTEX_3_ARGB		0x0694	/* Dword offset 1_BC */
534 #define VERTEX_1_X_Y		0x0658	/* Dword offset 1_BD */
535 #define VERTEX_2_X_Y		0x0678	/* Dword offset 1_BE */
536 #define VERTEX_3_X_Y		0x0698	/* Dword offset 1_BF */
537 #define ONE_OVER_AREA_UC	0x0700	/* Dword offset 1_C0 */
538 #define SETUP_CNTL		0x0704	/* Dword offset 1_C1 */
539 #define VERTEX_1_SECONDARY_S	0x0728	/* Dword offset 1_CA */
540 #define VERTEX_1_SECONDARY_T	0x072C	/* Dword offset 1_CB */
541 #define VERTEX_1_SECONDARY_W	0x0730	/* Dword offset 1_CC */
542 #define VERTEX_2_SECONDARY_S	0x0734	/* Dword offset 1_CD */
543 #define VERTEX_2_SECONDARY_T	0x0738	/* Dword offset 1_CE */
544 #define VERTEX_2_SECONDARY_W	0x073C	/* Dword offset 1_CF */
545 
546 
547 #define GTC_3D_RESET_DELAY	3	/* 3D engine reset delay in ms */
548 
549 /* CRTC control values (mostly CRTC_GEN_CNTL) */
550 
551 #define CRTC_H_SYNC_NEG		0x00200000
552 #define CRTC_V_SYNC_NEG		0x00200000
553 
554 #define CRTC_DBL_SCAN_EN	0x00000001
555 #define CRTC_INTERLACE_EN	0x00000002
556 #define CRTC_HSYNC_DIS		0x00000004
557 #define CRTC_VSYNC_DIS		0x00000008
558 #define CRTC_CSYNC_EN		0x00000010
559 #define CRTC_PIX_BY_2_EN	0x00000020	/* unused on RAGE */
560 #define CRTC_DISPLAY_DIS	0x00000040
561 #define CRTC_VGA_XOVERSCAN	0x00000040
562 
563 #define CRTC_PIX_WIDTH_MASK	0x00000700
564 #define CRTC_PIX_WIDTH_4BPP	0x00000100
565 #define CRTC_PIX_WIDTH_8BPP	0x00000200
566 #define CRTC_PIX_WIDTH_15BPP	0x00000300
567 #define CRTC_PIX_WIDTH_16BPP	0x00000400
568 #define CRTC_PIX_WIDTH_24BPP	0x00000500
569 #define CRTC_PIX_WIDTH_32BPP	0x00000600
570 
571 #define CRTC_BYTE_PIX_ORDER	0x00000800
572 #define CRTC_PIX_ORDER_MSN_LSN	0x00000000
573 #define CRTC_PIX_ORDER_LSN_MSN	0x00000800
574 
575 #define CRTC_FIFO_LWM		0x000f0000
576 
577 #define VGA_128KAP_PAGING	0x00100000
578 #define VFC_SYNC_TRISTATE	0x00200000
579 #define CRTC_LOCK_REGS		0x00400000
580 #define CRTC_SYNC_TRISTATE	0x00800000
581 
582 #define CRTC_EXT_DISP_EN	0x01000000
583 #define CRTC_ENABLE		0x02000000
584 #define CRTC_DISP_REQ_ENB	0x04000000
585 #define VGA_ATI_LINEAR		0x08000000
586 #define CRTC_VSYNC_FALL_EDGE	0x10000000
587 #define VGA_TEXT_132		0x20000000
588 #define VGA_XCRT_CNT_EN		0x40000000
589 #define VGA_CUR_B_TEST		0x80000000
590 
591 #define CRTC_CRNT_VLINE		0x07f00000
592 #define CRTC_VBLANK		0x00000001
593 
594 
595 /* DAC control values */
596 
597 #define DAC_EXT_SEL_RS2		0x01
598 #define DAC_EXT_SEL_RS3		0x02
599 #define DAC_8BIT_EN		0x00000100
600 #define DAC_PIX_DLY_MASK	0x00000600
601 #define DAC_PIX_DLY_0NS		0x00000000
602 #define DAC_PIX_DLY_2NS		0x00000200
603 #define DAC_PIX_DLY_4NS		0x00000400
604 #define DAC_BLANK_ADJ_MASK	0x00001800
605 #define DAC_BLANK_ADJ_0		0x00000000
606 #define DAC_BLANK_ADJ_1		0x00000800
607 #define DAC_BLANK_ADJ_2		0x00001000
608 
609 
610 /* Mix control values */
611 
612 #define MIX_NOT_DST		0x0000
613 #define MIX_0			0x0001
614 #define MIX_1			0x0002
615 #define MIX_DST			0x0003
616 #define MIX_NOT_SRC		0x0004
617 #define MIX_XOR			0x0005
618 #define MIX_XNOR		0x0006
619 #define MIX_SRC			0x0007
620 #define MIX_NAND		0x0008
621 #define MIX_NOT_SRC_OR_DST	0x0009
622 #define MIX_SRC_OR_NOT_DST	0x000a
623 #define MIX_OR			0x000b
624 #define MIX_AND			0x000c
625 #define MIX_SRC_AND_NOT_DST	0x000d
626 #define MIX_NOT_SRC_AND_DST	0x000e
627 #define MIX_NOR			0x000f
628 
629 /* Maximum engine dimensions */
630 #define ENGINE_MIN_X		0
631 #define ENGINE_MIN_Y		0
632 #define ENGINE_MAX_X		4095
633 #define ENGINE_MAX_Y		16383
634 
635 /* Mach64 engine bit constants - these are typically ORed together */
636 
637 /* BUS_CNTL register constants */
638 #define BUS_FIFO_ERR_ACK	0x00200000
639 #define BUS_HOST_ERR_ACK	0x00800000
640 
641 /* GEN_TEST_CNTL register constants */
642 #define GEN_OVR_OUTPUT_EN	0x20
643 #define HWCURSOR_ENABLE		0x80
644 #define GUI_ENGINE_ENABLE	0x100
645 #define BLOCK_WRITE_ENABLE	0x200
646 
647 /* DSP_CONFIG register constants */
648 #define DSP_XCLKS_PER_QW	0x00003fff
649 #define DSP_LOOP_LATENCY	0x000f0000
650 #define DSP_PRECISION		0x00700000
651 
652 /* DSP_ON_OFF register constants */
653 #define DSP_OFF			0x000007ff
654 #define DSP_ON			0x07ff0000
655 
656 /* CLOCK_CNTL register constants */
657 #define CLOCK_SEL		0x0f
658 #define CLOCK_DIV		0x30
659 #define CLOCK_DIV1		0x00
660 #define CLOCK_DIV2		0x10
661 #define CLOCK_DIV4		0x20
662 #define CLOCK_STROBE		0x40
663 #define PLL_WR_EN		0x02
664 
665 /* PLL register indices */
666 #define MPLL_CNTL		0x00
667 #define VPLL_CNTL		0x01
668 #define PLL_REF_DIV		0x02
669 #define PLL_GEN_CNTL		0x03
670 #define MCLK_FB_DIV		0x04
671 #define PLL_VCLK_CNTL		0x05
672 #define VCLK_POST_DIV		0x06
673 #define VCLK0_FB_DIV		0x07
674 #define VCLK1_FB_DIV		0x08
675 #define VCLK2_FB_DIV		0x09
676 #define VCLK3_FB_DIV		0x0A
677 #define PLL_EXT_CNTL		0x0B
678 #define DLL_CNTL		0x0C
679 #define DLL1_CNTL		0x0C
680 #define VFC_CNTL		0x0D
681 #define PLL_TEST_CNTL		0x0E
682 #define PLL_TEST_COUNT		0x0F
683 #define LVDS_CNTL0		0x10
684 #define LVDS_CNTL1		0x11
685 #define AGP1_CNTL		0x12
686 #define AGP2_CNTL		0x13
687 #define DLL2_CNTL		0x14
688 #define SCLK_FB_DIV		0x15
689 #define SPLL_CNTL1		0x16
690 #define SPLL_CNTL2		0x17
691 #define APLL_STRAPS		0x18
692 #define EXT_VPLL_CNTL		0x19
693 #define EXT_VPLL_REF_DIV	0x1A
694 #define EXT_VPLL_FB_DIV		0x1B
695 #define EXT_VPLL_MSB		0x1C
696 #define HTOTAL_CNTL		0x1D
697 #define BYTE_CLK_CNTL		0x1E
698 #define TV_PLL_CNTL1		0x1F
699 #define TV_PLL_CNTL2		0x20
700 #define TV_PLL_CNTL		0x21
701 #define EXT_TV_PLL		0x22
702 #define V2PLL_CNTL		0x23
703 #define PLL_V2CLK_CNTL		0x24
704 #define EXT_V2PLL_REF_DIV	0x25
705 #define EXT_V2PLL_FB_DIV	0x26
706 #define EXT_V2PLL_MSB		0x27
707 #define HTOTAL2_CNTL		0x28
708 #define PLL_YCLK_CNTL		0x29
709 #define PM_DYN_CLK_CNTL		0x2A
710 
711 /* Fields in PLL registers */
712 #define PLL_PC_GAIN		0x07
713 #define PLL_VC_GAIN		0x18
714 #define PLL_DUTY_CYC		0xE0
715 #define PLL_OVERRIDE		0x01
716 #define PLL_MCLK_RST		0x02
717 #define OSC_EN			0x04
718 #define EXT_CLK_EN		0x08
719 #define MCLK_SRC_SEL		0x70
720 #define EXT_CLK_CNTL		0x80
721 #define VCLK_SRC_SEL		0x03
722 #define PLL_VCLK_RST		0x04
723 #define VCLK_INVERT		0x08
724 #define VCLK0_POST		0x03
725 #define VCLK1_POST		0x0C
726 #define VCLK2_POST		0x30
727 #define VCLK3_POST		0xC0
728 
729 #define EXT_VPLL_EN		0x04
730 #define EXT_VPLL_VGA_EN		0x08
731 #define EXT_VPLL_INSYNC		0x10
732 
733 /* CONFIG_CNTL register constants */
734 #define APERTURE_4M_ENABLE	1
735 #define APERTURE_8M_ENABLE	2
736 #define VGA_APERTURE_ENABLE	4
737 
738 /* CONFIG_STAT0 register constants (GX, CX) */
739 #define CFG_BUS_TYPE		0x00000007
740 #define CFG_MEM_TYPE		0x00000038
741 #define CFG_INIT_DAC_TYPE	0x00000e00
742 
743 /* CONFIG_STAT0 register constants (CT, ET, VT) */
744 #define CFG_MEM_TYPE_xT		0x00000007
745 
746 #define ISA			0
747 #define EISA			1
748 #define LOCAL_BUS		6
749 #define PCI			7
750 
751 /* Memory types for GX, CX */
752 #define DRAMx4			0
753 #define VRAMx16			1
754 #define VRAMx16ssr		2
755 #define DRAMx16			3
756 #define GraphicsDRAMx16		4
757 #define EnhancedVRAMx16		5
758 #define EnhancedVRAMx16ssr	6
759 
760 /* Memory types for CT, ET, VT, GT */
761 #define DRAM			1
762 #define EDO			2
763 #define PSEUDO_EDO		3
764 #define SDRAM			4
765 #define SGRAM			5
766 #define WRAM			6
767 
768 #define DAC_INTERNAL		0x00
769 #define DAC_IBMRGB514		0x01
770 #define DAC_ATI68875		0x02
771 #define DAC_TVP3026_A		0x72
772 #define DAC_BT476		0x03
773 #define DAC_BT481		0x04
774 #define DAC_ATT20C491		0x14
775 #define DAC_SC15026		0x24
776 #define DAC_MU9C1880		0x34
777 #define DAC_IMSG174		0x44
778 #define DAC_ATI68860_B		0x05
779 #define DAC_ATI68860_C		0x15
780 #define DAC_TVP3026_B		0x75
781 #define DAC_STG1700		0x06
782 #define DAC_ATT498		0x16
783 #define DAC_STG1702		0x07
784 #define DAC_SC15021		0x17
785 #define DAC_ATT21C498		0x27
786 #define DAC_STG1703		0x37
787 #define DAC_CH8398		0x47
788 #define DAC_ATT20C408		0x57
789 
790 #define CLK_ATI18818_0		0
791 #define CLK_ATI18818_1		1
792 #define CLK_STG1703		2
793 #define CLK_CH8398		3
794 #define CLK_INTERNAL		4
795 #define CLK_ATT20C408		5
796 #define CLK_IBMRGB514		6
797 
798 /* MEM_CNTL register constants */
799 #define MEM_SIZE_ALIAS		0x00000007
800 #define MEM_SIZE_512K		0x00000000
801 #define MEM_SIZE_1M		0x00000001
802 #define MEM_SIZE_2M		0x00000002
803 #define MEM_SIZE_4M		0x00000003
804 #define MEM_SIZE_6M		0x00000004
805 #define MEM_SIZE_8M		0x00000005
806 #define MEM_SIZE_ALIAS_GTB	0x0000000F
807 #define MEM_SIZE_2M_GTB		0x00000003
808 #define MEM_SIZE_4M_GTB		0x00000007
809 #define MEM_SIZE_6M_GTB		0x00000009
810 #define MEM_SIZE_8M_GTB		0x0000000B
811 #define MEM_BNDRY		0x00030000
812 #define MEM_BNDRY_0K		0x00000000
813 #define MEM_BNDRY_256K		0x00010000
814 #define MEM_BNDRY_512K		0x00020000
815 #define MEM_BNDRY_1M		0x00030000
816 #define MEM_BNDRY_EN		0x00040000
817 
818 /* ATI PCI constants */
819 #define PCI_ATI_VENDOR_ID	0x1002
820 
821 
822 /* CONFIG_CHIP_ID register constants */
823 #define CFG_CHIP_TYPE		0x0000FFFF
824 #define CFG_CHIP_CLASS		0x00FF0000
825 #define CFG_CHIP_REV		0xFF000000
826 #define CFG_CHIP_MAJOR		0x07000000
827 #define CFG_CHIP_FND_ID		0x38000000
828 #define CFG_CHIP_MINOR		0xC0000000
829 
830 
831 /* Chip IDs read from CONFIG_CHIP_ID */
832 
833 /* mach64GX family */
834 #define GX_CHIP_ID	0xD7	/* mach64GX (ATI888GX00) */
835 #define CX_CHIP_ID	0x57	/* mach64CX (ATI888CX00) */
836 
837 #define GX_PCI_ID	0x4758	/* mach64GX (ATI888GX00) */
838 #define CX_PCI_ID	0x4358	/* mach64CX (ATI888CX00) */
839 
840 /* mach64CT family */
841 #define CT_CHIP_ID	0x4354	/* mach64CT (ATI264CT) */
842 #define ET_CHIP_ID	0x4554	/* mach64ET (ATI264ET) */
843 
844 /* mach64CT family / mach64VT class */
845 #define VT_CHIP_ID	0x5654	/* mach64VT (ATI264VT) */
846 #define VU_CHIP_ID	0x5655	/* mach64VTB (ATI264VTB) */
847 #define VV_CHIP_ID	0x5656	/* mach64VT4 (ATI264VT4) */
848 
849 /* mach64CT family / mach64GT (3D RAGE) class */
850 #define LB_CHIP_ID	0x4c42	/* RAGE LT PRO, AGP */
851 #define LD_CHIP_ID	0x4c44	/* RAGE LT PRO */
852 #define LG_CHIP_ID	0x4c47	/* RAGE LT */
853 #define LI_CHIP_ID	0x4c49	/* RAGE LT PRO */
854 #define LP_CHIP_ID	0x4c50	/* RAGE LT PRO */
855 #define LT_CHIP_ID	0x4c54	/* RAGE LT */
856 #define XL_CHIP_ID	0x4752	/* RAGE (XL) */
857 #define GT_CHIP_ID	0x4754	/* RAGE (GT) */
858 #define GU_CHIP_ID	0x4755	/* RAGE II/II+ (GTB) */
859 #define GV_CHIP_ID	0x4756	/* RAGE IIC, PCI */
860 #define GW_CHIP_ID	0x4757	/* RAGE IIC, AGP */
861 #define GZ_CHIP_ID	0x475a	/* RAGE IIC, AGP */
862 #define GB_CHIP_ID	0x4742	/* RAGE PRO, BGA, AGP 1x and 2x */
863 #define GD_CHIP_ID	0x4744	/* RAGE PRO, BGA, AGP 1x only */
864 #define GI_CHIP_ID	0x4749	/* RAGE PRO, BGA, PCI33 only */
865 #define GP_CHIP_ID	0x4750	/* RAGE PRO, PQFP, PCI33, full 3D */
866 #define GQ_CHIP_ID	0x4751	/* RAGE PRO, PQFP, PCI33, limited 3D */
867 #define LM_CHIP_ID	0x4c4d	/* RAGE Mobility PCI */
868 #define LN_CHIP_ID	0x4c4e	/* RAGE Mobility AGP */
869 
870 
871 /* Mach64 major ASIC revisions */
872 #define MACH64_ASIC_NEC_VT_A3		0x08
873 #define MACH64_ASIC_NEC_VT_A4		0x48
874 #define MACH64_ASIC_SGS_VT_A4		0x40
875 #define MACH64_ASIC_SGS_VT_B1S1		0x01
876 #define MACH64_ASIC_SGS_GT_B1S1		0x01
877 #define MACH64_ASIC_SGS_GT_B1S2		0x41
878 #define MACH64_ASIC_UMC_GT_B2U1		0x1a
879 #define MACH64_ASIC_UMC_GT_B2U2		0x5a
880 #define MACH64_ASIC_UMC_VT_B2U3		0x9a
881 #define MACH64_ASIC_UMC_GT_B2U3		0x9a
882 #define MACH64_ASIC_UMC_R3B_D_P_A1	0x1b
883 #define MACH64_ASIC_UMC_R3B_D_P_A2	0x5b
884 #define MACH64_ASIC_UMC_R3B_D_P_A3	0x1c
885 #define MACH64_ASIC_UMC_R3B_D_P_A4	0x5c
886 
887 /* Mach64 foundries */
888 #define MACH64_FND_SGS		0
889 #define MACH64_FND_NEC		1
890 #define MACH64_FND_UMC		3
891 
892 /* Mach64 chip types */
893 #define MACH64_UNKNOWN		0
894 #define MACH64_GX		1
895 #define MACH64_CX		2
896 #define MACH64_CT		3
897 #define MACH64_ET		4
898 #define MACH64_VT		5
899 #define MACH64_GT		6
900 
901 /* DST_CNTL register constants */
902 #define DST_X_RIGHT_TO_LEFT	0
903 #define DST_X_LEFT_TO_RIGHT	1
904 #define DST_Y_BOTTOM_TO_TOP	0
905 #define DST_Y_TOP_TO_BOTTOM	2
906 #define DST_X_MAJOR		0
907 #define DST_Y_MAJOR		4
908 #define DST_X_TILE		8
909 #define DST_Y_TILE		0x10
910 #define DST_LAST_PEL		0x20
911 #define DST_POLYGON_ENABLE	0x40
912 #define DST_24_ROTATION_ENABLE	0x80
913 
914 /* SRC_CNTL register constants */
915 #define SRC_PATTERN_ENABLE		1
916 #define SRC_ROTATION_ENABLE		2
917 #define SRC_LINEAR_ENABLE		4
918 #define SRC_BYTE_ALIGN			8
919 #define SRC_LINE_X_RIGHT_TO_LEFT	0
920 #define SRC_LINE_X_LEFT_TO_RIGHT	0x10
921 
922 /* HOST_CNTL register constants */
923 #define HOST_BYTE_ALIGN		1
924 
925 /* GUI_TRAJ_CNTL register constants */
926 #define PAT_MONO_8x8_ENABLE	0x01000000
927 #define PAT_CLR_4x2_ENABLE	0x02000000
928 #define PAT_CLR_8x1_ENABLE	0x04000000
929 
930 /* DP_CHAIN_MASK register constants */
931 #define DP_CHAIN_4BPP		0x8888
932 #define DP_CHAIN_7BPP		0xD2D2
933 #define DP_CHAIN_8BPP		0x8080
934 #define DP_CHAIN_8BPP_RGB	0x9292
935 #define DP_CHAIN_15BPP		0x4210
936 #define DP_CHAIN_16BPP		0x8410
937 #define DP_CHAIN_24BPP		0x8080
938 #define DP_CHAIN_32BPP		0x8080
939 
940 /* DP_PIX_WIDTH register constants */
941 #define DST_1BPP		0
942 #define DST_4BPP		1
943 #define DST_8BPP		2
944 #define DST_15BPP		3
945 #define DST_16BPP		4
946 #define DST_32BPP		6
947 #define SRC_1BPP		0
948 #define SRC_4BPP		0x100
949 #define SRC_8BPP		0x200
950 #define SRC_15BPP		0x300
951 #define SRC_16BPP		0x400
952 #define SRC_32BPP		0x600
953 #define HOST_TRIPLE_EN          0x2000
954 #define HOST_1BPP		0
955 #define HOST_4BPP		0x10000
956 #define HOST_8BPP		0x20000
957 #define HOST_15BPP		0x30000
958 #define HOST_16BPP		0x40000
959 #define HOST_32BPP		0x60000
960 #define BYTE_ORDER_MSB_TO_LSB	0
961 #define BYTE_ORDER_LSB_TO_MSB	0x1000000
962 
963 /* DP_MIX register constants */
964 #define BKGD_MIX_NOT_D			0
965 #define BKGD_MIX_ZERO			1
966 #define BKGD_MIX_ONE			2
967 #define BKGD_MIX_D			3
968 #define BKGD_MIX_NOT_S			4
969 #define BKGD_MIX_D_XOR_S		5
970 #define BKGD_MIX_NOT_D_XOR_S		6
971 #define BKGD_MIX_S			7
972 #define BKGD_MIX_NOT_D_OR_NOT_S		8
973 #define BKGD_MIX_D_OR_NOT_S		9
974 #define BKGD_MIX_NOT_D_OR_S		10
975 #define BKGD_MIX_D_OR_S			11
976 #define BKGD_MIX_D_AND_S		12
977 #define BKGD_MIX_NOT_D_AND_S		13
978 #define BKGD_MIX_D_AND_NOT_S		14
979 #define BKGD_MIX_NOT_D_AND_NOT_S	15
980 #define BKGD_MIX_D_PLUS_S_DIV2		0x17
981 #define FRGD_MIX_NOT_D			0
982 #define FRGD_MIX_ZERO			0x10000
983 #define FRGD_MIX_ONE			0x20000
984 #define FRGD_MIX_D			0x30000
985 #define FRGD_MIX_NOT_S			0x40000
986 #define FRGD_MIX_D_XOR_S		0x50000
987 #define FRGD_MIX_NOT_D_XOR_S		0x60000
988 #define FRGD_MIX_S			0x70000
989 #define FRGD_MIX_NOT_D_OR_NOT_S		0x80000
990 #define FRGD_MIX_D_OR_NOT_S		0x90000
991 #define FRGD_MIX_NOT_D_OR_S		0xa0000
992 #define FRGD_MIX_D_OR_S			0xb0000
993 #define FRGD_MIX_D_AND_S		0xc0000
994 #define FRGD_MIX_NOT_D_AND_S		0xd0000
995 #define FRGD_MIX_D_AND_NOT_S		0xe0000
996 #define FRGD_MIX_NOT_D_AND_NOT_S	0xf0000
997 #define FRGD_MIX_D_PLUS_S_DIV2		0x170000
998 
999 /* DP_SRC register constants */
1000 #define BKGD_SRC_BKGD_CLR	0
1001 #define BKGD_SRC_FRGD_CLR	1
1002 #define BKGD_SRC_HOST		2
1003 #define BKGD_SRC_BLIT		3
1004 #define BKGD_SRC_PATTERN	4
1005 #define FRGD_SRC_BKGD_CLR	0
1006 #define FRGD_SRC_FRGD_CLR	0x100
1007 #define FRGD_SRC_HOST		0x200
1008 #define FRGD_SRC_BLIT		0x300
1009 #define FRGD_SRC_PATTERN	0x400
1010 #define MONO_SRC_ONE		0
1011 #define MONO_SRC_PATTERN	0x10000
1012 #define MONO_SRC_HOST		0x20000
1013 #define MONO_SRC_BLIT		0x30000
1014 
1015 /* CLR_CMP_CNTL register constants */
1016 #define COMPARE_FALSE		0
1017 #define COMPARE_TRUE		1
1018 #define COMPARE_NOT_EQUAL	4
1019 #define COMPARE_EQUAL		5
1020 #define COMPARE_DESTINATION	0
1021 #define COMPARE_SOURCE		0x1000000
1022 
1023 /* FIFO_STAT register constants */
1024 #define FIFO_ERR		0x80000000
1025 
1026 /* CONTEXT_LOAD_CNTL constants */
1027 #define CONTEXT_NO_LOAD			0
1028 #define CONTEXT_LOAD			0x10000
1029 #define CONTEXT_LOAD_AND_DO_FILL	0x20000
1030 #define CONTEXT_LOAD_AND_DO_LINE	0x30000
1031 #define CONTEXT_EXECUTE			0
1032 #define CONTEXT_CMD_DISABLE		0x80000000
1033 
1034 /* GUI_STAT register constants */
1035 #define ENGINE_IDLE		0
1036 #define ENGINE_BUSY		1
1037 #define SCISSOR_LEFT_FLAG	0x10
1038 #define SCISSOR_RIGHT_FLAG	0x20
1039 #define SCISSOR_TOP_FLAG	0x40
1040 #define SCISSOR_BOTTOM_FLAG	0x80
1041 
1042 /* ATI VGA Extended Regsiters */
1043 #define sioATIEXT		0x1ce
1044 #define bioATIEXT		0x3ce
1045 
1046 #define ATI2E			0xae
1047 #define ATI32			0xb2
1048 #define ATI36			0xb6
1049 
1050 /* VGA Graphics Controller Registers */
1051 #define VGAGRA			0x3ce
1052 #define GRA06			0x06
1053 
1054 /* VGA Seququencer Registers */
1055 #define VGASEQ			0x3c4
1056 #define SEQ02			0x02
1057 #define SEQ04			0x04
1058 
1059 #define MACH64_MAX_X		ENGINE_MAX_X
1060 #define MACH64_MAX_Y		ENGINE_MAX_Y
1061 
1062 #define INC_X			0x0020
1063 #define INC_Y			0x0080
1064 
1065 #define RGB16_555		0x0000
1066 #define RGB16_565		0x0040
1067 #define RGB16_655		0x0080
1068 #define RGB16_664		0x00c0
1069 
1070 #define POLY_TEXT_TYPE		0x0001
1071 #define IMAGE_TEXT_TYPE		0x0002
1072 #define TEXT_TYPE_8_BIT		0x0004
1073 #define TEXT_TYPE_16_BIT	0x0008
1074 #define POLY_TEXT_TYPE_8	(POLY_TEXT_TYPE | TEXT_TYPE_8_BIT)
1075 #define IMAGE_TEXT_TYPE_8	(IMAGE_TEXT_TYPE | TEXT_TYPE_8_BIT)
1076 #define POLY_TEXT_TYPE_16	(POLY_TEXT_TYPE | TEXT_TYPE_16_BIT)
1077 #define IMAGE_TEXT_TYPE_16	(IMAGE_TEXT_TYPE | TEXT_TYPE_16_BIT)
1078 
1079 #define MACH64_NUM_CLOCKS	16
1080 #define MACH64_NUM_FREQS	50
1081 
1082 /* Power Management register constants (LT & LT Pro) */
1083 #define PWR_MGT_ON		0x00000001
1084 #define PWR_MGT_MODE_MASK	0x00000006
1085 #define AUTO_PWR_UP		0x00000008
1086 #define USE_F32KHZ		0x00000400
1087 #define TRISTATE_MEM_EN		0x00000800
1088 #define SELF_REFRESH		0x00000080
1089 #define PWR_BLON		0x02000000
1090 #define STANDBY_NOW		0x10000000
1091 #define SUSPEND_NOW		0x20000000
1092 #define PWR_MGT_STATUS_MASK	0xC0000000
1093 #define PWR_MGT_STATUS_SUSPEND	0x80000000
1094 
1095 /* PM Mode constants  */
1096 #define PWR_MGT_MODE_PIN	0x00000000
1097 #define PWR_MGT_MODE_REG	0x00000002
1098 #define PWR_MGT_MODE_TIMER	0x00000004
1099 #define PWR_MGT_MODE_PCI	0x00000006
1100 
1101 /* LCD registers (LT Pro) */
1102 
1103 /* LCD Index register */
1104 #define LCD_INDEX_MASK		0x0000003F
1105 #define LCD_DISPLAY_DIS		0x00000100
1106 #define LCD_SRC_SEL		0x00000200
1107 #define CRTC2_DISPLAY_DIS	0x00000400
1108 
1109 /* LCD register indices */
1110 #define CONFIG_PANEL		0x00
1111 #define LCD_GEN_CTRL		0x01
1112 #define DSTN_CONTROL		0x02
1113 #define HFB_PITCH_ADDR		0x03
1114 #define HORZ_STRETCHING		0x04
1115 #define VERT_STRETCHING		0x05
1116 #define EXT_VERT_STRETCH	0x06
1117 #define LT_GIO			0x07
1118 #define POWER_MANAGEMENT	0x08
1119 #define ZVGPIO			0x09
1120 #define ICON_CLR0		0x0A
1121 #define ICON_CLR1		0x0B
1122 #define ICON_OFFSET		0x0C
1123 #define ICON_HORZ_VERT_POSN	0x0D
1124 #define ICON_HORZ_VERT_OFF	0x0E
1125 #define ICON2_CLR0		0x0F
1126 #define ICON2_CLR1		0x10
1127 #define ICON2_OFFSET		0x11
1128 #define ICON2_HORZ_VERT_POSN	0x12
1129 #define ICON2_HORZ_VERT_OFF	0x13
1130 #define LCD_MISC_CNTL		0x14
1131 #define APC_CNTL		0x1C
1132 #define POWER_MANAGEMENT_2	0x1D
1133 #define ALPHA_BLENDING		0x25
1134 #define PORTRAIT_GEN_CNTL	0x26
1135 #define APC_CTRL_IO		0x27
1136 #define TEST_IO			0x28
1137 #define TEST_OUTPUTS		0x29
1138 #define DP1_MEM_ACCESS		0x2A
1139 #define DP0_MEM_ACCESS		0x2B
1140 #define DP0_DEBUG_A		0x2C
1141 #define DP0_DEBUG_B		0x2D
1142 #define DP1_DEBUG_A		0x2E
1143 #define DP1_DEBUG_B		0x2F
1144 #define DPCTRL_DEBUG_A		0x30
1145 #define DPCTRL_DEBUG_B		0x31
1146 #define MEMBLK_DEBUG		0x32
1147 #define APC_LUT_AB		0x33
1148 #define APC_LUT_CD		0x34
1149 #define APC_LUT_EF		0x35
1150 #define APC_LUT_GH		0x36
1151 #define APC_LUT_IJ		0x37
1152 #define APC_LUT_KL		0x38
1153 #define APC_LUT_MN		0x39
1154 #define APC_LUT_OP		0x3A
1155 
1156 /* Values in CONFIG_PANEL */
1157 
1158 #define DONT_SHADOW_HEND                0x00004000ul
1159 
1160 /* Values in LCD_GEN_CTRL */
1161 #define CRT_ON                          0x00000001ul
1162 #define LCD_ON                          0x00000002ul
1163 #define HORZ_DIVBY2_EN                  0x00000004ul
1164 #define DONT_DS_ICON                    0x00000008ul
1165 #define LOCK_8DOT                       0x00000010ul
1166 #define ICON_ENABLE                     0x00000020ul
1167 #define DONT_SHADOW_VPAR                0x00000040ul
1168 #define V2CLK_PM_EN                     0x00000080ul
1169 #define RST_FM                          0x00000100ul
1170 #define DISABLE_PCLK_RESET              0x00000200ul    /* XC/XL */
1171 #define DIS_HOR_CRT_DIVBY2              0x00000400ul
1172 #define SCLK_SEL                        0x00000800ul
1173 #define SCLK_DELAY                      0x0000f000ul
1174 #define TVCLK_PM_EN                     0x00010000ul
1175 #define VCLK_DAC_PM_EN                  0x00020000ul
1176 #define VCLK_LCD_OFF                    0x00040000ul
1177 #define SELECT_WAIT_4MS                 0x00080000ul
1178 #define XTALIN_PM_EN                    0x00080000ul    /* XC/XL */
1179 #define V2CLK_DAC_PM_EN                 0x00100000ul
1180 #define LVDS_EN                         0x00200000ul
1181 #define LVDS_PLL_EN                     0x00400000ul
1182 #define LVDS_PLL_RESET                  0x00800000ul
1183 #define LVDS_RESERVED_BITS              0x07000000ul
1184 #define CRTC_RW_SELECT                  0x08000000ul    /* LTPro */
1185 #define USE_SHADOWED_VEND               0x10000000ul
1186 #define USE_SHADOWED_ROWCUR             0x20000000ul
1187 #define SHADOW_EN                       0x40000000ul
1188 #define SHADOW_RW_EN                    0x80000000ul
1189 
1190 /* Values in HORZ_STRETCHING */
1191 #define HORZ_STRETCH_BLEND              0x00000ffful
1192 #define HORZ_STRETCH_RATIO              0x0000fffful
1193 #define HORZ_STRETCH_LOOP               0x00070000ul
1194 #define HORZ_STRETCH_LOOP09                     0x00000000ul
1195 #define HORZ_STRETCH_LOOP11                     0x00010000ul
1196 #define HORZ_STRETCH_LOOP12                     0x00020000ul
1197 #define HORZ_STRETCH_LOOP14                     0x00030000ul
1198 #define HORZ_STRETCH_LOOP15                     0x00040000ul
1199 /*      ?                                       0x00050000ul */
1200 /*      ?                                       0x00060000ul */
1201 /*      ?                                       0x00070000ul */
1202 /*      ?                               0x00080000ul */
1203 #define HORZ_PANEL_SIZE                 0x0ff00000ul    /* XC/XL */
1204 /*      ?                               0x10000000ul */
1205 #define AUTO_HORZ_RATIO                 0x20000000ul    /* XC/XL */
1206 #define HORZ_STRETCH_MODE               0x40000000ul
1207 #define HORZ_STRETCH_EN                 0x80000000ul
1208 
1209 /* Values in VERT_STRETCHING */
1210 #define VERT_STRETCH_RATIO0             0x000003fful
1211 #define VERT_STRETCH_RATIO1             0x000ffc00ul
1212 #define VERT_STRETCH_RATIO2             0x3ff00000ul
1213 #define VERT_STRETCH_USE0               0x40000000ul
1214 #define VERT_STRETCH_EN                 0x80000000ul
1215 
1216 /* Values in EXT_VERT_STRETCH */
1217 #define AUTO_VERT_RATIO                 0x00400000ul
1218 #define VERT_STRETCH_MODE		0x00000400ul
1219 
1220 /* Values in LCD_MISC_CNTL */
1221 #define BIAS_MOD_LEVEL_MASK	0x0000ff00
1222 #define BIAS_MOD_LEVEL_SHIFT	8
1223 #define BLMOD_EN		0x00010000
1224 #define BIASMOD_EN		0x00020000
1225 
1226 #endif /* REGMACH64_H */
1227