Searched refs:PPLL_FB3_DIV_MASK (Results 1 – 4 of 4) sorted by relevance
268 #define PPLL_FB3_DIV_MASK 0x7FF macro
3336 (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) in radeon_write_pll_regs()3352 while ((INPLL(PPLL_DIV_3) & PPLL_FB3_DIV_MASK) != in radeon_write_pll_regs()3353 (mode->ppll_div_3 & PPLL_FB3_DIV_MASK)) { in radeon_write_pll_regs()3354 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK); in radeon_write_pll_regs()
879 #define PPLL_FB3_DIV_MASK 0x000007ff macro
1121 div3 &= ~PPLL_FB3_DIV_MASK; in aty128_set_pll()