Searched refs:PPLL_DIV_SEL_MASK (Results 1 – 2 of 2) sorted by relevance
875 #define PPLL_DIV_SEL_MASK 0x00000300 macro
3340 while ((INREG(CLOCK_CNTL_INDEX) & PPLL_DIV_SEL_MASK) != in radeon_write_pll_regs()3341 PPLL_DIV_SEL_MASK) { in radeon_write_pll_regs()3342 OUTREGP(CLOCK_CNTL_INDEX, PPLL_DIV_SEL_MASK, 0xffff); in radeon_write_pll_regs()