Searched refs:PPLL_DIV_3 (Results 1 – 4 of 4) sorted by relevance
247 #define PPLL_DIV_3 0x0007 macro
3335 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) & in radeon_write_pll_regs()3352 while ((INPLL(PPLL_DIV_3) & PPLL_FB3_DIV_MASK) != in radeon_write_pll_regs()3354 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK); in radeon_write_pll_regs()3357 while ((INPLL(PPLL_DIV_3) & PPLL_POST3_DIV_MASK) != in radeon_write_pll_regs()3359 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK); in radeon_write_pll_regs()
410 #define PPLL_DIV_3 0x0007 macro
1120 div3 = aty_ld_pll(PPLL_DIV_3); in aty128_set_pll()1128 aty_st_pll(PPLL_DIV_3, div3); in aty128_set_pll()