1 /* -*- linux-c -*- */ 2 #ifndef __REG9050_H 3 #define __REG9050_H 4 5 /******************************************************************************* 6 * Copyright (c) 2001 PLX Technology, Inc. 7 * 8 * PLX Technology Inc. licenses this software under specific terms and 9 * conditions. Use of any of the software or derviatives thereof in any 10 * product without a PLX Technology chip is strictly prohibited. 11 * 12 * PLX Technology, Inc. provides this software AS IS, WITHOUT ANY WARRANTY, 13 * EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY WARRANTY OF 14 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. PLX makes no guarantee 15 * or representations regarding the use of, or the results of the use of, 16 * the software and documentation in terms of correctness, accuracy, 17 * reliability, currentness, or otherwise; and you rely on the software, 18 * documentation and results solely at your own risk. 19 * 20 * IN NO EVENT SHALL PLX BE LIABLE FOR ANY LOSS OF USE, LOSS OF BUSINESS, 21 * LOSS OF PROFITS, INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES 22 * OF ANY KIND. IN NO EVENT SHALL PLX'S TOTAL LIABILITY EXCEED THE SUM 23 * PAID TO PLX FOR THE PRODUCT LICENSED HEREUNDER. 24 * 25 ******************************************************************************/ 26 27 /* Modifications and extensions 28 * Copyright (C) 2001 By Joachim Martillo, Telford Tools, Inc. 29 * 30 * This program is free software; you can redistribute it and/or 31 * modify it under the terms of the GNU General Public License 32 * as published by the Free Software Foundation; either version 33 * 2 of the License, or (at your option) any later version. 34 **/ 35 36 37 /****************************************************************************** 38 * 39 * File Name: 40 * 41 * Reg9050.h 42 * 43 * Description: 44 * 45 * This file defines all the PLX 9050 chip Registers. 46 * 47 * Revision: 48 * 49 * 01-30-01 : PCI SDK v3.20 50 * 51 ******************************************************************************/ 52 53 54 #include "PciRegs.h" 55 56 57 #ifdef __cplusplus 58 extern "C" { 59 #endif 60 61 62 /* PCI Configuration Registers */ 63 #define PCI9050_VENDOR_ID CFG_VENDOR_ID 64 #define PCI9050_COMMAND CFG_COMMAND 65 #define PCI9050_REV_ID CFG_REV_ID 66 #define PCI9050_CACHE_SIZE CFG_CACHE_SIZE 67 #define PCI9050_PCI_BASE_0 CFG_BAR0 68 #define PCI9050_PCI_BASE_1 CFG_BAR1 69 #define PCI9050_PCI_BASE_2 CFG_BAR2 70 #define PCI9050_PCI_BASE_3 CFG_BAR3 71 #define PCI9050_PCI_BASE_4 CFG_BAR4 72 #define PCI9050_PCI_BASE_5 CFG_BAR5 73 #define PCI9050_CIS_PTR CFG_CIS_PTR 74 #define PCI9050_SUB_ID CFG_SUB_VENDOR_ID 75 #define PCI9050_PCI_BASE_EXP_ROM CFG_EXP_ROM_BASE 76 #define PCI9050_CAP_PTR CFG_CAP_PTR 77 #define PCI9050_PCI_RESERVED CFG_RESERVED2 78 #define PCI9050_INT_LINE CFG_INT_LINE 79 80 81 #if 0 /* from PLX header file */ 82 /* Local Configuration Registers */ 83 #define PCI9050_RANGE_SPACE0 0x000 84 #define PCI9050_RANGE_SPACE1 0x004 85 #define PCI9050_RANGE_SPACE2 0x008 86 #define PCI9050_RANGE_SPACE3 0x00C 87 #define PCI9050_RANGE_EXP_ROM 0x010 88 #define PCI9050_REMAP_SPACE0 0x014 89 #define PCI9050_REMAP_SPACE1 0x018 90 #define PCI9050_REMAP_SPACE2 0x01C 91 #define PCI9050_REMAP_SPACE3 0x020 92 #define PCI9050_REMAP_EXP_ROM 0x024 93 #define PCI9050_DESC_SPACE0 0x028 94 #define PCI9050_DESC_SPACE1 0x02C 95 #define PCI9050_DESC_SPACE2 0x030 96 #define PCI9050_DESC_SPACE3 0x034 97 #define PCI9050_DESC_EXP_ROM 0x038 98 #define PCI9050_BASE_CS0 0x03C 99 #define PCI9050_BASE_CS1 0x040 100 #define PCI9050_BASE_CS2 0x044 101 #define PCI9050_BASE_CS3 0x048 102 #define PCI9050_INT_CTRL_STAT 0x04C 103 #define PCI9050_EEPROM_CTRL 0x050 104 105 #endif 106 107 108 /* Additional register defintions */ 109 #define MAX_PCI9050_REG_OFFSET 0x054 110 111 #define PCI9050_EEPROM_SIZE 0x064 112 113 /* 114 * PLX 9050 registers: 115 */ 116 117 typedef struct plx9050_s 118 { 119 /* Local Address Space */ 120 unsigned int las0; /* 0x00 */ 121 unsigned int las1; /* 0x04 */ 122 unsigned int las2; /* 0x08 */ 123 unsigned int las3; /* 0x0c */ 124 /* Expansion ROM range */ 125 unsigned int e_rom; /* 0x10 */ 126 /* Local Base Adresses */ 127 unsigned int lba0; /* 0x14 */ 128 unsigned int lba1; /* 0x18 */ 129 unsigned int lba2; /* 0x1c */ 130 unsigned int lba3; /* 0x20 */ 131 unsigned int e_rom_lba; /* 0x24 */ 132 /* Bus region description */ 133 unsigned int brd0; /* 0x28 */ 134 unsigned int brd1; /* 0x2c */ 135 unsigned int brd2; /* 0x30 */ 136 unsigned int brd3; /* 0x34 */ 137 unsigned int e_rom_brd; /* 0x38 */ 138 /* Chip Select X Base address */ 139 unsigned int csba0; /* 0x3c */ 140 unsigned int csba1; /* 0x40 */ 141 unsigned int csba2; /* 0x44 */ 142 unsigned int csba3; /* 0x48 */ 143 /* Interupt Control/Status */ 144 unsigned int intr; /* 0x4c */ 145 /* Control */ 146 unsigned int ctrl; /* 0x50 */ 147 } plx9050_t, PLX9050; 148 149 #define PLX_REG_LAS0RR 0x0 150 #define PLX_REG_LAS1RR 0x4 151 #define PLX_REG_LAS2RR 0x8 152 #define PLX_REG_LAS3RR 0x0c 153 #define PLX_REG_EROMRR 0x10 154 #define PLX_REG_LAS0BA 0x14 155 #define PLX_REG_LAS1BA 0x18 156 #define PLX_REG_LAS2BA 0x1c 157 #define PLX_REG_LAS3BA 0x20 158 #define PLX_REG_EROMBA 0x24 159 #define PLX_REG_LAS0BRD 0x28 160 #define PLX_REG_LAS1BRD 0x2c 161 #define PLX_REG_LAS2BRD 0x30 162 #define PLX_REG_LAS3BRD 0x34 163 #define PLX_REG_EROMBRD 0x38 164 #define PLX_REG_CS0BASE 0x3c 165 #define PLX_REG_CS1BASE 0x40 166 #define PLX_REG_CS2BASE 0x44 167 #define PLX_REG_CS3BASE 0x48 168 #define PLX_REG_INTCSR 0x4c 169 #define PLX_REG_CTRL 0x50 170 171 /* 172 * Bits within those registers: 173 */ 174 /* LAS0 */ 175 #define PLX_LAS0_MEM_MASK 0x0ffffff0 176 177 /* INTCSR: */ 178 #define PLX_INT_INTR1ENA 0x00000001 /* Local interrupt 1 enable */ 179 #define PLX_INT_INTR1POL 0x00000002 /* Local interrupt 1 polarity */ 180 #define PLX_INT_INTR1STS 0x00000004 /* Local interrupt 1 status */ 181 #define PLX_INT_INTR2ENA 0x00000008 /* Local interrupt 2 enable */ 182 #define PLX_INT_INTR2POL 0x00000010 /* Local interrupt 2 polarity */ 183 #define PLX_INT_INTR2STS 0x00000020 /* Local interrupt 2 status */ 184 #define PLX_INT_PCIINTRENA 0x00000040 /* PCI interrupt enable */ 185 #define PLX_INT_SOFTINTR 0x00000080 /* Software interrupt */ 186 #if 0 187 #define PLX_INT_ON (PLX_INT_INTR1ENA | PLX_INT_PCIINTRENA | PLX_INT_INTR2POL) 188 #define PLX_INT_OFF PLX_INT_INTR2POL 189 #elif 0 190 #define PLX_INT_ON PLX_INT_PCIINTRENA 191 #define PLX_INT_OFF 0 192 #else 193 #define PLX_INT_ON (PLX_INT_INTR1ENA | PLX_INT_PCIINTRENA) 194 #define PLX_INT_OFF 0x0000 195 #endif 196 197 /* BRD */ 198 #define PLX_BRD_BIGEND 0x01000000 199 #define PLX_BRD_BIGEND_LANE 0x02000000 200 201 202 /* CTRL: */ /* 87654321 */ 203 #define PLX_CTRL_RESET 0x40000000 204 #define PLX_CTRL_USERIO3DIR 0x00000400 205 #define PLX_CTRL_USERIO3DATA 0x00000800 206 #define PLX_CTRL_SEPCLK 0x01000000 207 #define PLX_CTRL_SEPCS 0x02000000 208 #define PLX_CTRL_SEPWD 0x04000000 209 #define PLX_CTRL_SEPRD 0x08000000 210 211 /* Definition for the EPROM */ 212 /* # of addressing bits for NM93CS06, NM93CS46 */ 213 #define NM93_ADDRBITS 6 214 #define NM93_WENCMD ((u8) 0x00) 215 #define NM93_WRITECMD ((u8) 0x01) 216 #define NM93_READCMD ((u8) 0x02) 217 #define NM93_WRALLCMD ((u8) 0x00) /* same as WEN */ 218 #define NM93_WDSCMD ((u8) 0x00) /* ditto */ 219 220 #define NM93_WDSADDR ((u8) 0x00) 221 #define NM93_WRALLADDR ((u8) 0x10) 222 #define NM93_WENADDR ((u8) 0x30) 223 224 #define NM93_BITS_PER_BYTE 8 225 #define NM93_BITS_PER_WORD 16 226 227 #define EPROMPREFETCHOFFSET 9 228 #define PREFETCHBIT 0x0008 229 230 #define EPROM9050_SIZE 0x40 /* for loading the 9050 */ 231 232 #define AURORA_MULTI_EPROM_SIZE 0x40 /* serial EPROM size */ 233 /* serial EPROM offsets */ 234 #define AURORA_MULTI_EPROM_CLKLSW 0x36 /* clock speed LSW */ 235 #define AURORA_MULTI_EPROM_CLKMSW 0x37 /* clock speed MSW */ 236 #define AURORA_MULTI_EPROM_REV 0x38 /* revision begins here */ 237 #define AURORA_MULTI_EPROM_REVLEN 0x0f /* length (in bytes) */ 238 #define AURORA_MULTI_EPROM_SPDGRD 0x3f /* speed grade is here */ 239 240 #ifdef __cplusplus 241 } 242 #endif 243 244 #endif 245