1 #ifndef _PARISC_PDC_H 2 #define _PARISC_PDC_H 3 4 /* 5 * PDC return values ... 6 * All PDC calls return a subset of these errors. 7 */ 8 9 #define PDC_WARN 3 /* Call completed with a warning */ 10 #define PDC_REQ_ERR_1 2 /* See above */ 11 #define PDC_REQ_ERR_0 1 /* Call would generate a requestor error */ 12 #define PDC_OK 0 /* Call completed successfully */ 13 #define PDC_BAD_PROC -1 /* Called non-existent procedure*/ 14 #define PDC_BAD_OPTION -2 /* Called with non-existent option */ 15 #define PDC_ERROR -3 /* Call could not complete without an error */ 16 #define PDC_NE_MOD -5 /* Module not found */ 17 #define PDC_NE_CELL_MOD -7 /* Cell module not found */ 18 #define PDC_INVALID_ARG -10 /* Called with an invalid argument */ 19 #define PDC_BUS_POW_WARN -12 /* Call could not complete in allowed power budget */ 20 #define PDC_NOT_NARROW -17 /* Narrow mode not supported */ 21 22 23 /* 24 * PDC entry points... 25 */ 26 27 #define PDC_POW_FAIL 1 /* perform a power-fail */ 28 #define PDC_POW_FAIL_PREPARE 0 /* prepare for powerfail */ 29 30 #define PDC_CHASSIS 2 /* PDC-chassis functions */ 31 #define PDC_CHASSIS_DISP 0 /* update chassis display */ 32 #define PDC_CHASSIS_WARN 1 /* return chassis warnings */ 33 #define PDC_CHASSIS_DISPWARN 2 /* update&return chassis status */ 34 #define PDC_RETURN_CHASSIS_INFO 128 /* HVERSION dependent: return chassis LED/LCD info */ 35 36 #define PDC_PIM 3 /* Get PIM data */ 37 #define PDC_PIM_HPMC 0 /* Transfer HPMC data */ 38 #define PDC_PIM_RETURN_SIZE 1 /* Get Max buffer needed for PIM*/ 39 #define PDC_PIM_LPMC 2 /* Transfer HPMC data */ 40 #define PDC_PIM_SOFT_BOOT 3 /* Transfer Soft Boot data */ 41 #define PDC_PIM_TOC 4 /* Transfer TOC data */ 42 43 #define PDC_MODEL 4 /* PDC model information call */ 44 #define PDC_MODEL_INFO 0 /* returns information */ 45 #define PDC_MODEL_BOOTID 1 /* set the BOOT_ID */ 46 #define PDC_MODEL_VERSIONS 2 /* returns cpu-internal versions*/ 47 #define PDC_MODEL_SYSMODEL 3 /* return system model info */ 48 #define PDC_MODEL_ENSPEC 4 /* enable specific option */ 49 #define PDC_MODEL_DISPEC 5 /* disable specific option */ 50 #define PDC_MODEL_CPU_ID 6 /* returns cpu-id (only newer machines!) */ 51 #define PDC_MODEL_CAPABILITIES 7 /* returns OS32/OS64-flags */ 52 #define PDC_MODEL_GET_BOOT__OP 8 /* returns boot test options */ 53 #define PDC_MODEL_SET_BOOT__OP 9 /* set boot test options */ 54 55 #define PA89_INSTRUCTION_SET 0x4 /* capatibilies returned */ 56 #define PA90_INSTRUCTION_SET 0x8 57 58 #define PDC_CACHE 5 /* return/set cache (& TLB) info*/ 59 #define PDC_CACHE_INFO 0 /* returns information */ 60 #define PDC_CACHE_SET_COH 1 /* set coherence state */ 61 #define PDC_CACHE_RET_SPID 2 /* returns space-ID bits */ 62 63 #define PDC_HPA 6 /* return HPA of processor */ 64 #define PDC_HPA_PROCESSOR 0 65 #define PDC_HPA_MODULES 1 66 67 #define PDC_COPROC 7 /* Co-Processor (usually FP unit(s)) */ 68 #define PDC_COPROC_CFG 0 /* Co-Processor Cfg (FP unit(s) enabled?) */ 69 70 #define PDC_IODC 8 /* talk to IODC */ 71 #define PDC_IODC_READ 0 /* read IODC entry point */ 72 /* PDC_IODC_RI_ * INDEX parameter of PDC_IODC_READ */ 73 #define PDC_IODC_RI_DATA_BYTES 0 /* IODC Data Bytes */ 74 /* 1, 2 obsolete - HVERSION dependent*/ 75 #define PDC_IODC_RI_INIT 3 /* Initialize module */ 76 #define PDC_IODC_RI_IO 4 /* Module input/output */ 77 #define PDC_IODC_RI_SPA 5 /* Module input/output */ 78 #define PDC_IODC_RI_CONFIG 6 /* Module input/output */ 79 /* 7 obsolete - HVERSION dependent */ 80 #define PDC_IODC_RI_TEST 8 /* Module input/output */ 81 #define PDC_IODC_RI_TLB 9 /* Module input/output */ 82 #define PDC_IODC_NINIT 2 /* non-destructive init */ 83 #define PDC_IODC_DINIT 3 /* destructive init */ 84 #define PDC_IODC_MEMERR 4 /* check for memory errors */ 85 #define PDC_IODC_INDEX_DATA 0 /* get first 16 bytes from mod IODC */ 86 #define PDC_IODC_BUS_ERROR -4 /* bus error return value */ 87 #define PDC_IODC_INVALID_INDEX -5 /* invalid index return value */ 88 #define PDC_IODC_COUNT -6 /* count is too small */ 89 90 #define PDC_TOD 9 /* time-of-day clock (TOD) */ 91 #define PDC_TOD_READ 0 /* read TOD */ 92 #define PDC_TOD_WRITE 1 /* write TOD */ 93 #define PDC_TOD_ITIMER 2 /* calibrate Interval Timer (CR16) */ 94 95 #define PDC_STABLE 10 /* stable storage (sprockets) */ 96 #define PDC_STABLE_READ 0 97 #define PDC_STABLE_WRITE 1 98 #define PDC_STABLE_RETURN_SIZE 2 99 #define PDC_STABLE_VERIFY_CONTENTS 3 100 #define PDC_STABLE_INITIALIZE 4 101 102 #define PDC_NVOLATILE 11 /* often not implemented */ 103 104 #define PDC_ADD_VALID 12 /* Memory validation PDC call */ 105 #define PDC_ADD_VALID_VERIFY 0 /* Make PDC_ADD_VALID verify region */ 106 107 #define PDC_INSTR 15 /* get instr to invoke PDCE_CHECK() */ 108 109 #define PDC_PROC 16 /* (sprockets) */ 110 111 #define PDC_CONFIG 16 /* (sprockets) */ 112 #define PDC_CONFIG_DECONFIG 0 113 #define PDC_CONFIG_DRECONFIG 1 114 #define PDC_CONFIG_DRETURN_CONFIG 2 115 116 #define PDC_BLOCK_TLB 18 /* manage hardware block-TLB */ 117 #define PDC_BTLB_INFO 0 /* returns parameter */ 118 #define PDC_BTLB_INSERT 1 /* insert BTLB entry */ 119 #define PDC_BTLB_PURGE 2 /* purge BTLB entries */ 120 #define PDC_BTLB_PURGE_ALL 3 /* purge all BTLB entries */ 121 122 #define PDC_TLB 19 /* manage hardware TLB miss handling */ 123 #define PDC_TLB_INFO 0 /* returns parameter */ 124 #define PDC_TLB_SETUP 1 /* set up miss handling */ 125 126 #define PDC_MEM 20 /* Manage memory */ 127 #define PDC_MEM_MEMINFO 0 128 #define PDC_MEM_ADD_PAGE 1 129 #define PDC_MEM_CLEAR_PDT 2 130 #define PDC_MEM_READ_PDT 3 131 #define PDC_MEM_RESET_CLEAR 4 132 #define PDC_MEM_GOODMEM 5 133 #define PDC_MEM_TABLE 128 /* Non contig mem map (sprockets) */ 134 #define PDC_MEM_RETURN_ADDRESS_TABLE PDC_MEM_TABLE 135 #define PDC_MEM_GET_MEMORY_SYSTEM_TABLES_SIZE 131 136 #define PDC_MEM_GET_MEMORY_SYSTEM_TABLES 132 137 #define PDC_MEM_GET_PHYSICAL_LOCATION_FROM_MEMORY_ADDRESS 133 138 139 #define PDC_MEM_RET_SBE_REPLACED 5 /* PDC_MEM return values */ 140 #define PDC_MEM_RET_DUPLICATE_ENTRY 4 141 #define PDC_MEM_RET_BUF_SIZE_SMALL 1 142 #define PDC_MEM_RET_PDT_FULL -11 143 #define PDC_MEM_RET_INVALID_PHYSICAL_LOCATION ~0ULL 144 145 #ifndef __ASSEMBLY__ 146 typedef struct { 147 unsigned long long baseAddr; 148 unsigned int pages; 149 unsigned int reserved; 150 } MemAddrTable_t; 151 #endif 152 153 154 #define PDC_PSW 21 /* Get/Set default System Mask */ 155 #define PDC_PSW_MASK 0 /* Return mask */ 156 #define PDC_PSW_GET_DEFAULTS 1 /* Return defaults */ 157 #define PDC_PSW_SET_DEFAULTS 2 /* Set default */ 158 #define PDC_PSW_ENDIAN_BIT 1 /* set for big endian */ 159 #define PDC_PSW_WIDE_BIT 2 /* set for wide mode */ 160 161 #define PDC_SYSTEM_MAP 22 /* find system modules */ 162 #define PDC_FIND_MODULE 0 163 #define PDC_FIND_ADDRESS 1 164 #define PDC_TRANSLATE_PATH 2 165 166 #define PDC_SOFT_POWER 23 /* soft power switch */ 167 #define PDC_SOFT_POWER_INFO 0 /* return info about the soft power switch */ 168 #define PDC_SOFT_POWER_ENABLE 1 /* enable/disable soft power switch */ 169 170 171 /* HVERSION dependent */ 172 173 /* The PDC_MEM_MAP calls */ 174 #define PDC_MEM_MAP 128 /* on s700: return page info */ 175 #define PDC_MEM_MAP_HPA 0 /* returns hpa of a module */ 176 177 #define PDC_EEPROM 129 /* EEPROM access */ 178 #define PDC_EEPROM_READ_WORD 0 179 #define PDC_EEPROM_WRITE_WORD 1 180 #define PDC_EEPROM_READ_BYTE 2 181 #define PDC_EEPROM_WRITE_BYTE 3 182 #define PDC_EEPROM_EEPROM_PASSWORD -1000 183 184 #define PDC_NVM 130 /* NVM (non-volatile memory) access */ 185 #define PDC_NVM_READ_WORD 0 186 #define PDC_NVM_WRITE_WORD 1 187 #define PDC_NVM_READ_BYTE 2 188 #define PDC_NVM_WRITE_BYTE 3 189 190 #define PDC_SEED_ERROR 132 /* (sprockets) */ 191 192 #define PDC_IO 135 /* log error info, reset IO system */ 193 #define PDC_IO_READ_AND_CLEAR_ERRORS 0 194 #define PDC_IO_READ_AND_LOG_ERRORS 1 195 #define PDC_IO_SUSPEND_USB 2 196 /* sets bits 6&7 (little endian) of the HcControl Register */ 197 #define PDC_IO_USB_SUSPEND 0xC000000000000000 198 #define PDC_IO_EEPROM_IO_ERR_TABLE_FULL -5 /* return value */ 199 #define PDC_IO_NO_SUSPEND -6 /* return value */ 200 201 #define PDC_BROADCAST_RESET 136 /* reset all processors */ 202 #define PDC_DO_RESET 0 /* option: perform a broadcast reset */ 203 #define PDC_DO_FIRM_TEST_RESET 1 /* Do broadcast reset with bitmap */ 204 #define PDC_BR_RECONFIGURATION 2 /* reset w/reconfiguration */ 205 #define PDC_FIRM_TEST_MAGIC 0xab9ec36fUL /* for this reboot only */ 206 207 #define PDC_LAN_STATION_ID 138 /* Hversion dependent mechanism for */ 208 #define PDC_LAN_STATION_ID_READ 0 /* getting the lan station address */ 209 210 #define PDC_LAN_STATION_ID_SIZE 6 211 212 #define PDC_CHECK_RANGES 139 /* (sprockets) */ 213 214 #define PDC_NV_SECTIONS 141 /* (sprockets) */ 215 216 #define PDC_PERFORMANCE 142 /* performance monitoring */ 217 218 #define PDC_SYSTEM_INFO 143 /* system information */ 219 #define PDC_SYSINFO_RETURN_INFO_SIZE 0 220 #define PDC_SYSINFO_RRETURN_SYS_INFO 1 221 #define PDC_SYSINFO_RRETURN_ERRORS 2 222 #define PDC_SYSINFO_RRETURN_WARNINGS 3 223 #define PDC_SYSINFO_RETURN_REVISIONS 4 224 #define PDC_SYSINFO_RRETURN_DIAGNOSE 5 225 #define PDC_SYSINFO_RRETURN_HV_DIAGNOSE 1005 226 227 #define PDC_RDR 144 /* (sprockets) */ 228 #define PDC_RDR_READ_BUFFER 0 229 #define PDC_RDR_READ_SINGLE 1 230 #define PDC_RDR_WRITE_SINGLE 2 231 232 #define PDC_INTRIGUE 145 /* (sprockets) */ 233 #define PDC_INTRIGUE_WRITE_BUFFER 0 234 #define PDC_INTRIGUE_GET_SCRATCH_BUFSIZE 1 235 #define PDC_INTRIGUE_START_CPU_COUNTERS 2 236 #define PDC_INTRIGUE_STOP_CPU_COUNTERS 3 237 238 #define PDC_STI 146 /* STI access */ 239 /* same as PDC_PCI_XXX values (see below) */ 240 241 /* Legacy PDC definitions for same stuff */ 242 #define PDC_PCI_INDEX 147 243 #define PDC_PCI_INTERFACE_INFO 0 244 #define PDC_PCI_SLOT_INFO 1 245 #define PDC_PCI_INFLIGHT_BYTES 2 246 #define PDC_PCI_READ_CONFIG 3 247 #define PDC_PCI_WRITE_CONFIG 4 248 #define PDC_PCI_READ_PCI_IO 5 249 #define PDC_PCI_WRITE_PCI_IO 6 250 #define PDC_PCI_READ_CONFIG_DELAY 7 251 #define PDC_PCI_UPDATE_CONFIG_DELAY 8 252 #define PDC_PCI_PCI_PATH_TO_PCI_HPA 9 253 #define PDC_PCI_PCI_HPA_TO_PCI_PATH 10 254 #define PDC_PCI_PCI_PATH_TO_PCI_BUS 11 255 #define PDC_PCI_PCI_RESERVED 12 256 #define PDC_PCI_PCI_INT_ROUTE_SIZE 13 257 #define PDC_PCI_GET_INT_TBL_SIZE PDC_PCI_PCI_INT_ROUTE_SIZE 258 #define PDC_PCI_PCI_INT_ROUTE 14 259 #define PDC_PCI_GET_INT_TBL PDC_PCI_PCI_INT_ROUTE 260 #define PDC_PCI_READ_MON_TYPE 15 261 #define PDC_PCI_WRITE_MON_TYPE 16 262 263 264 /* Get SCSI Interface Card info: SDTR, SCSI ID, mode (SE vs LVD) */ 265 #define PDC_INITIATOR 163 266 #define PDC_GET_INITIATOR 0 267 #define PDC_SET_INITIATOR 1 268 #define PDC_DELETE_INITIATOR 2 269 #define PDC_RETURN_TABLE_SIZE 3 270 #define PDC_RETURN_TABLE 4 271 272 #define PDC_LINK 165 /* (sprockets) */ 273 #define PDC_LINK_PCI_ENTRY_POINTS 0 /* list (Arg1) = 0 */ 274 #define PDC_LINK_USB_ENTRY_POINTS 1 /* list (Arg1) = 1 */ 275 276 277 /* constants for OS (NVM...) */ 278 #define OS_ID_NONE 0 /* Undefined OS ID */ 279 #define OS_ID_HPUX 1 /* HP-UX OS */ 280 #define OS_ID_LINUX OS_ID_HPUX /* just use the same value as hpux */ 281 #define OS_ID_MPEXL 2 /* MPE XL OS */ 282 #define OS_ID_OSF 3 /* OSF OS */ 283 #define OS_ID_HPRT 4 /* HP-RT OS */ 284 #define OS_ID_NOVEL 5 /* NOVELL OS */ 285 #define OS_ID_NT 6 /* NT OS */ 286 287 288 /* constants for PDC_CHASSIS */ 289 #define OSTAT_OFF 0 290 #define OSTAT_FLT 1 291 #define OSTAT_TEST 2 292 #define OSTAT_INIT 3 293 #define OSTAT_SHUT 4 294 #define OSTAT_WARN 5 295 #define OSTAT_RUN 6 296 #define OSTAT_ON 7 297 298 #ifdef __LP64__ 299 /* PDC PAT CELL */ 300 #define PDC_PAT_CELL 64L /* Interface for gaining and 301 * manipulating cell state within PD */ 302 #define PDC_PAT_CELL_GET_NUMBER 0L /* Return Cell number */ 303 #define PDC_PAT_CELL_GET_INFO 1L /* Returns info about Cell */ 304 #define PDC_PAT_CELL_MODULE 2L /* Returns info about Module */ 305 #define PDC_PAT_CELL_SET_ATTENTION 9L /* Set Cell Attention indicator */ 306 #define PDC_PAT_CELL_NUMBER_TO_LOC 10L /* Cell Number -> Location */ 307 #define PDC_PAT_CELL_WALK_FABRIC 11L /* Walk the Fabric */ 308 #define PDC_PAT_CELL_GET_RDT_SIZE 12L /* Return Route Distance Table Sizes */ 309 #define PDC_PAT_CELL_GET_RDT 13L /* Return Route Distance Tables */ 310 #define PDC_PAT_CELL_GET_LOCAL_PDH_SZ 14L /* Read Local PDH Buffer Size*/ 311 #define PDC_PAT_CELL_SET_LOCAL_PDH 15L /* Write Local PDH Buffer */ 312 #define PDC_PAT_CELL_GET_REMOTE_PDH_SZ 16L /* Return Remote PDH Buffer Size */ 313 #define PDC_PAT_CELL_GET_REMOTE_PDH 17L /* Read Remote PDH Buffer */ 314 #define PDC_PAT_CELL_GET_DBG_INFO 128L /* Return DBG Buffer Info */ 315 #define PDC_PAT_CELL_CHANGE_ALIAS 129L /* Change Non-Equivalent Alias Checking */ 316 317 /* 318 ** Arg to PDC_PAT_CELL_MODULE memaddr[4] 319 ** 320 ** Addresses on the Merced Bus != all Runway Bus addresses. 321 ** This is intended for programming SBA/LBA chips range registers. 322 */ 323 #define IO_VIEW 0UL 324 #define PA_VIEW 1UL 325 326 /* PDC_PAT_CELL_MODULE entity type values */ 327 #define PAT_ENTITY_CA 0 /* central agent */ 328 #define PAT_ENTITY_PROC 1 /* processor */ 329 #define PAT_ENTITY_MEM 2 /* memory controller */ 330 #define PAT_ENTITY_SBA 3 /* system bus adapter */ 331 #define PAT_ENTITY_LBA 4 /* local bus adapter */ 332 #define PAT_ENTITY_PBC 5 /* processor bus converter */ 333 #define PAT_ENTITY_XBC 6 /* crossbar fabric connect */ 334 #define PAT_ENTITY_RC 7 /* fabric interconnect */ 335 336 /* PDC_PAT_CELL_MODULE address range type values */ 337 #define PAT_PBNUM 0 /* PCI Bus Number */ 338 #define PAT_LMMIO 1 /* < 4G MMIO Space */ 339 #define PAT_GMMIO 2 /* > 4G MMIO Space */ 340 #define PAT_NPIOP 3 /* Non Postable I/O Port Space */ 341 #define PAT_PIOP 4 /* Postable I/O Port Space */ 342 #define PAT_AHPA 5 /* Additional HPA Space */ 343 #define PAT_UFO 6 /* HPA Space (UFO for Mariposa) */ 344 #define PAT_GNIP 7 /* GNI Reserved Space */ 345 346 347 /* PDC PAT CHASSIS LOG */ 348 #define PDC_PAT_CHASSIS_LOG 65L /* Platform logging & forward 349 ** progress functions */ 350 #define PDC_PAT_CHASSIS_WRITE_LOG 0L /* Write Log Entry */ 351 #define PDC_PAT_CHASSIS_READ_LOG 1L /* Read Log Entry */ 352 353 354 /* PDC PAT CPU */ 355 #define PDC_PAT_CPU 67L /* Interface to CPU configuration 356 * within the protection domain */ 357 #define PDC_PAT_CPU_INFO 0L /* Return CPU config info */ 358 #define PDC_PAT_CPU_DELETE 1L /* Delete CPU */ 359 #define PDC_PAT_CPU_ADD 2L /* Add CPU */ 360 #define PDC_PAT_CPU_GET_NUMBER 3L /* Return CPU Number */ 361 #define PDC_PAT_CPU_GET_HPA 4L /* Return CPU HPA */ 362 #define PDC_PAT_CPU_STOP 5L /* Stop CPU */ 363 #define PDC_PAT_CPU_RENDEZVOUS 6L /* Rendezvous CPU */ 364 #define PDC_PAT_CPU_GET_CLOCK_INFO 7L /* Return CPU Clock info */ 365 #define PDC_PAT_CPU_GET_RENDEZVOUS_STATE 8L /* Return Rendezvous State */ 366 #define PDC_PAT_CPU_PLUNGE_FABRIC 128L /* Plunge Fabric */ 367 #define PDC_PAT_CPU_UPDATE_CACHE_CLEANSING 129L /* Manipulate Cache 368 * Cleansing Mode */ 369 370 /* PDC PAT EVENT */ 371 #define PDC_PAT_EVENT 68L /* Interface to Platform Events */ 372 #define PDC_PAT_EVENT_GET_CAPS 0L /* Get Capabilities */ 373 #define PDC_PAT_EVENT_SET_MODE 1L /* Set Notification Mode */ 374 #define PDC_PAT_EVENT_SCAN 2L /* Scan Event */ 375 #define PDC_PAT_EVENT_HANDLE 3L /* Handle Event */ 376 #define PDC_PAT_EVENT_GET_NB_CALL 4L /* Get Non-Blocking call Args*/ 377 378 /* PDC PAT HPMC */ 379 #define PDC_PAT_HPMC 70L /* Cause processor to go into spin 380 ** loop, and wait for wake up from 381 ** Monarch Processor */ 382 #define PDC_PAT_HPMC_RENDEZ_CPU 0L /* go into spin loop */ 383 #define PDC_PAT_HPMC_SET_PARAMS 1L /* Allows OS to specify intr which PDC 384 * will use to interrupt OS during machine 385 * check rendezvous */ 386 387 /* parameters for PDC_PAT_HPMC_SET_PARAMS */ 388 #define HPMC_SET_PARAMS_INTR 1L /* Rendezvous Interrupt */ 389 #define HPMC_SET_PARAMS_WAKE 2L /* Wake up processor */ 390 391 /* PDC PAT IO */ 392 #define PDC_PAT_IO 71L /* On-line services for I/O modules */ 393 #define PDC_PAT_IO_GET_SLOT_STATUS 5L /* Get Slot Status Info */ 394 #define PDC_PAT_IO_GET_LOC_FROM_HARDWARE 6L /* Get Physical Location from */ 395 /* Hardware Path */ 396 #define PDC_PAT_IO_GET_HARDWARE_FROM_LOC 7L /* Get Hardware Path from 397 * Physical Location */ 398 #define PDC_PAT_IO_GET_PCI_CONFIG_FROM_HW 11L /* Get PCI Configuration 399 * Address from Hardware Path */ 400 #define PDC_PAT_IO_GET_HW_FROM_PCI_CONFIG 12L /* Get Hardware Path 401 * from PCI Configuration Address */ 402 #define PDC_PAT_IO_READ_HOST_BRIDGE_INFO 13L /* Read Host Bridge State Info */ 403 #define PDC_PAT_IO_CLEAR_HOST_BRIDGE_INFO 14L /* Clear Host Bridge State Info*/ 404 #define PDC_PAT_IO_GET_PCI_ROUTING_TABLE_SIZE 15L /* Get PCI INT Routing Table 405 * Size */ 406 #define PDC_PAT_IO_GET_PCI_ROUTING_TABLE 16L /* Get PCI INT Routing Table */ 407 #define PDC_PAT_IO_GET_HINT_TABLE_SIZE 17L /* Get Hint Table Size */ 408 #define PDC_PAT_IO_GET_HINT_TABLE 18L /* Get Hint Table */ 409 #define PDC_PAT_IO_PCI_CONFIG_READ 19L /* PCI Config Read */ 410 #define PDC_PAT_IO_PCI_CONFIG_WRITE 20L /* PCI Config Write */ 411 #define PDC_PAT_IO_GET_NUM_IO_SLOTS 21L /* Get Number of I/O Bay Slots in 412 * Cabinet */ 413 #define PDC_PAT_IO_GET_LOC_IO_SLOTS 22L /* Get Physical Location of I/O */ 414 /* Bay Slots in Cabinet */ 415 #define PDC_PAT_IO_BAY_STATUS_INFO 28L /* Get I/O Bay Slot Status Info */ 416 #define PDC_PAT_IO_GET_PROC_VIEW 29L /* Get Processor view of IO address */ 417 #define PDC_PAT_IO_PROG_SBA_DIR_RANGE 30L /* Program directed range */ 418 419 /* PDC PAT MEM */ 420 #define PDC_PAT_MEM 72L /* Manage memory page deallocation */ 421 #define PDC_PAT_MEM_PD_INFO 0L /* Return PDT info for PD */ 422 #define PDC_PAT_MEM_PD_CLEAR 1L /* Clear PDT for PD */ 423 #define PDC_PAT_MEM_PD_READ 2L /* Read PDT entries for PD */ 424 #define PDC_PAT_MEM_PD_RESET 3L /* Reset clear bit for PD */ 425 #define PDC_PAT_MEM_CELL_INFO 5L /* Return PDT info For Cell */ 426 #define PDC_PAT_MEM_CELL_CLEAR 6L /* Clear PDT For Cell */ 427 #define PDC_PAT_MEM_CELL_READ 7L /* Read PDT entries For Cell */ 428 #define PDC_PAT_MEM_CELL_RESET 8L /* Reset clear bit For Cell */ 429 #define PDC_PAT_MEM_SETGM 9L /* Set Golden Memory value */ 430 #define PDC_PAT_MEM_ADD_PAGE 10L /* ADDs a page to the cell */ 431 #define PDC_PAT_MEM_ADDRESS 11L /* Get Physical Location From*/ 432 /* Memory Address */ 433 #define PDC_PAT_MEM_GET_TXT_SIZE 12L /* Get Formatted Text Size */ 434 #define PDC_PAT_MEM_GET_PD_TXT 13L /* Get PD Formatted Text */ 435 #define PDC_PAT_MEM_GET_CELL_TXT 14L /* Get Cell Formatted Text */ 436 #define PDC_PAT_MEM_RD_STATE_INFO 15L /* Read Mem Module State Info*/ 437 #define PDC_PAT_MEM_CLR_STATE_INFO 16L /*Clear Mem Module State Info*/ 438 #define PDC_PAT_MEM_CLEAN_RANGE 128L /*Clean Mem in specific range*/ 439 #define PDC_PAT_MEM_GET_TBL_SIZE 131L /* Get Memory Table Size */ 440 #define PDC_PAT_MEM_GET_TBL 132L /* Get Memory Table */ 441 442 /* PDC PAT NVOLATILE */ 443 #define PDC_PAT_NVOLATILE 73L /* Access Non-Volatile Memory*/ 444 #define PDC_PAT_NVOLATILE_READ 0L /* Read Non-Volatile Memory */ 445 #define PDC_PAT_NVOLATILE_WRITE 1L /* Write Non-Volatile Memory */ 446 #define PDC_PAT_NVOLATILE_GET_SIZE 2L /* Return size of NVM */ 447 #define PDC_PAT_NVOLATILE_VERIFY 3L /* Verify contents of NVM */ 448 #define PDC_PAT_NVOLATILE_INIT 4L /* Initialize NVM */ 449 450 /* PDC PAT PD */ 451 #define PDC_PAT_PD 74L /* Protection Domain Info */ 452 #define PDC_PAT_PD_GET_ADDR_MAP 0L /* Get Address Map */ 453 454 /* PDC_PAT_PD_GET_ADDR_MAP entry types */ 455 #define PAT_MEMORY_DESCRIPTOR 1 456 457 /* PDC_PAT_PD_GET_ADDR_MAP memory types */ 458 #define PAT_MEMTYPE_MEMORY 0 459 #define PAT_MEMTYPE_FIRMWARE 4 460 461 /* PDC_PAT_PD_GET_ADDR_MAP memory usage */ 462 #define PAT_MEMUSE_GENERAL 0 463 #define PAT_MEMUSE_GI 128 464 #define PAT_MEMUSE_GNI 129 465 #endif /* __LP64__ */ 466 467 #ifndef __ASSEMBLY__ 468 469 #include <linux/types.h> 470 471 extern int pdc_type; 472 473 /* Values for pdc_type */ 474 #define PDC_TYPE_ILLEGAL -1 475 #define PDC_TYPE_PAT 0 /* 64-bit PAT-PDC */ 476 #define PDC_TYPE_SYSTEM_MAP 1 /* 32-bit, but supports PDC_SYSTEM_MAP */ 477 #define PDC_TYPE_SNAKE 2 /* Doesn't support SYSTEM_MAP */ 478 479 #define is_pdc_pat() (pdc_type == PDC_TYPE_PAT) 480 481 struct pdc_chassis_info { /* for PDC_CHASSIS_INFO */ 482 unsigned long actcnt; /* actual number of bytes returned */ 483 unsigned long maxcnt; /* maximum number of bytes that could be returned */ 484 }; 485 486 struct pdc_coproc_cfg { /* for PDC_COPROC_CFG */ 487 unsigned long ccr_functional; 488 unsigned long ccr_present; 489 unsigned long revision; 490 unsigned long model; 491 }; 492 493 struct pdc_model { /* for PDC_MODEL */ 494 unsigned long hversion; 495 unsigned long sversion; 496 unsigned long hw_id; 497 unsigned long boot_id; 498 unsigned long sw_id; 499 unsigned long sw_cap; 500 unsigned long arch_rev; 501 unsigned long pot_key; 502 unsigned long curr_key; 503 }; 504 505 /* Values for PDC_MODEL_CAPABILITES non-equivalent virtual aliasing support */ 506 507 #define PDC_MODEL_IOPDIR_FDC (1 << 2) /* see sba_iommu.c */ 508 #define PDC_MODEL_NVA_MASK (3 << 4) 509 #define PDC_MODEL_NVA_SUPPORTED (0 << 4) 510 #define PDC_MODEL_NVA_SLOW (1 << 4) 511 #define PDC_MODEL_NVA_UNSUPPORTED (3 << 4) 512 513 struct pdc_cache_cf { /* for PDC_CACHE (I/D-caches) */ 514 unsigned long 515 #ifdef __LP64__ 516 cc_padW:32, 517 #endif 518 cc_alias:4, /* alias boundaries for virtual addresses */ 519 cc_block: 4, /* to determine most efficient stride */ 520 cc_line : 3, /* maximum amount written back as a result of store (multiple of 16 bytes) */ 521 cc_pad0 : 2, /* reserved */ 522 cc_wt : 1, /* 0 = WT-Dcache, 1 = WB-Dcache */ 523 cc_sh : 2, /* 0 = separate I/D-cache, else shared I/D-cache */ 524 cc_cst : 3, /* 0 = incoherent D-cache, 1=coherent D-cache */ 525 cc_pad1 : 5, /* reserved */ 526 cc_assoc: 8; /* associativity of I/D-cache */ 527 }; 528 529 struct pdc_tlb_cf { /* for PDC_CACHE (I/D-TLB's) */ 530 unsigned long tc_pad0:12, /* reserved */ 531 #ifdef __LP64__ 532 tc_padW:32, 533 #endif 534 tc_sh : 2, /* 0 = separate I/D-TLB, else shared I/D-TLB */ 535 tc_hv : 1, /* HV */ 536 tc_page : 1, /* 0 = 2K page-size-machine, 1 = 4k page size */ 537 tc_cst : 3, /* 0 = incoherent operations, else coherent operations */ 538 tc_aid : 5, /* ITLB: width of access ids of processor (encoded!) */ 539 tc_pad1 : 8; /* ITLB: width of space-registers (encoded) */ 540 }; 541 542 struct pdc_cache_info { /* main-PDC_CACHE-structure (caches & TLB's) */ 543 /* I-cache */ 544 unsigned long ic_size; /* size in bytes */ 545 struct pdc_cache_cf ic_conf; /* configuration */ 546 unsigned long ic_base; /* base-addr */ 547 unsigned long ic_stride; 548 unsigned long ic_count; 549 unsigned long ic_loop; 550 /* D-cache */ 551 unsigned long dc_size; /* size in bytes */ 552 struct pdc_cache_cf dc_conf; /* configuration */ 553 unsigned long dc_base; /* base-addr */ 554 unsigned long dc_stride; 555 unsigned long dc_count; 556 unsigned long dc_loop; 557 /* Instruction-TLB */ 558 unsigned long it_size; /* number of entries in I-TLB */ 559 struct pdc_tlb_cf it_conf; /* I-TLB-configuration */ 560 unsigned long it_sp_base; 561 unsigned long it_sp_stride; 562 unsigned long it_sp_count; 563 unsigned long it_off_base; 564 unsigned long it_off_stride; 565 unsigned long it_off_count; 566 unsigned long it_loop; 567 /* data-TLB */ 568 unsigned long dt_size; /* number of entries in D-TLB */ 569 struct pdc_tlb_cf dt_conf; /* D-TLB-configuration */ 570 unsigned long dt_sp_base; 571 unsigned long dt_sp_stride; 572 unsigned long dt_sp_count; 573 unsigned long dt_off_base; 574 unsigned long dt_off_stride; 575 unsigned long dt_off_count; 576 unsigned long dt_loop; 577 }; 578 579 #if 0 580 /* If you start using the next struct, you'll have to adjust it to 581 * work with 64-bit firmware I think -PB 582 */ 583 struct pdc_iodc { /* PDC_IODC */ 584 unsigned char hversion_model; 585 unsigned char hversion; 586 unsigned char spa; 587 unsigned char type; 588 unsigned int sversion_rev:4; 589 unsigned int sversion_model:19; 590 unsigned int sversion_opt:8; 591 unsigned char rev; 592 unsigned char dep; 593 unsigned char features; 594 unsigned char pad1; 595 unsigned int checksum:16; 596 unsigned int length:16; 597 unsigned int pad[15]; 598 } __attribute__((aligned(8))) ; 599 #endif 600 601 #ifndef CONFIG_PA20 602 /* no BLTBs in pa2.0 processors */ 603 struct pdc_btlb_info_range { 604 __u8 res00; 605 __u8 num_i; 606 __u8 num_d; 607 __u8 num_comb; 608 }; 609 610 struct pdc_btlb_info { /* PDC_BLOCK_TLB, return of PDC_BTLB_INFO */ 611 unsigned int min_size; /* minimum size of BTLB in pages */ 612 unsigned int max_size; /* maximum size of BTLB in pages */ 613 struct pdc_btlb_info_range fixed_range_info; 614 struct pdc_btlb_info_range variable_range_info; 615 }; 616 617 #endif /* !CONFIG_PA20 */ 618 619 #ifdef __LP64__ 620 struct pdc_memory_table_raddr { /* PDC_MEM/PDC_MEM_TABLE (return info) */ 621 unsigned long entries_returned; 622 unsigned long entries_total; 623 }; 624 625 struct pdc_memory_table { /* PDC_MEM/PDC_MEM_TABLE (arguments) */ 626 unsigned long paddr; 627 unsigned int pages; 628 unsigned int reserved; 629 }; 630 #endif /* __LP64__ */ 631 632 struct pdc_system_map_mod_info { /* PDC_SYSTEM_MAP/FIND_MODULE */ 633 unsigned long mod_addr; 634 unsigned long mod_pgs; 635 unsigned long add_addrs; 636 }; 637 638 struct pdc_system_map_addr_info { /* PDC_SYSTEM_MAP/FIND_ADDRESS */ 639 unsigned long mod_addr; 640 unsigned long mod_pgs; 641 }; 642 643 struct hardware_path { 644 char flags; /* see bit definitions below */ 645 char bc[6]; /* Bus Converter routing info to a specific */ 646 /* I/O adaptor (< 0 means none, > 63 resvd) */ 647 char mod; /* fixed field of specified module */ 648 }; 649 650 /* 651 * Device path specifications used by PDC. 652 */ 653 struct pdc_module_path { 654 struct hardware_path path; 655 unsigned int layers[6]; /* device-specific info (ctlr #, unit # ...) */ 656 }; 657 658 #ifndef CONFIG_PA20 659 /* Only used on some pre-PA2.0 boxes */ 660 struct pdc_memory_map { /* PDC_MEMORY_MAP */ 661 unsigned long hpa; /* mod's register set address */ 662 unsigned long more_pgs; /* number of additional I/O pgs */ 663 }; 664 #endif 665 666 struct pdc_tod { 667 unsigned long tod_sec; 668 unsigned long tod_usec; 669 }; 670 671 #ifdef __LP64__ 672 struct pdc_pat_cell_num { 673 unsigned long cell_num; 674 unsigned long cell_loc; 675 }; 676 677 struct pdc_pat_cpu_num { 678 unsigned long cpu_num; 679 unsigned long cpu_loc; 680 }; 681 682 struct pdc_pat_pd_addr_map_entry { 683 unsigned char entry_type; /* 1 = Memory Descriptor Entry Type */ 684 unsigned char reserve1[5]; 685 unsigned char memory_type; 686 unsigned char memory_usage; 687 unsigned long paddr; 688 unsigned int pages; /* Length in 4K pages */ 689 unsigned int reserve2; 690 unsigned long cell_map; 691 }; 692 693 /* FIXME: mod[508] should really be a union of the various mod components */ 694 struct pdc_pat_cell_mod_maddr_block { /* PDC_PAT_CELL_MODULE */ 695 unsigned long cba; /* function 0 configuration space address */ 696 unsigned long mod_info; /* module information */ 697 unsigned long mod_location; /* physical location of the module */ 698 struct hardware_path mod_path; /* hardware path */ 699 unsigned long mod[508]; /* PAT cell module components */ 700 }; 701 702 typedef struct pdc_pat_cell_mod_maddr_block pdc_pat_cell_mod_maddr_block_t; 703 #endif /* __LP64__ */ 704 705 /* architected results from PDC_PIM/transfer hpmc on a PA1.1 machine */ 706 707 struct pdc_hpmc_pim_11 { /* PDC_PIM */ 708 __u32 gr[32]; 709 __u32 cr[32]; 710 __u32 sr[8]; 711 __u32 iasq_back; 712 __u32 iaoq_back; 713 __u32 check_type; 714 __u32 cpu_state; 715 __u32 rsvd1; 716 __u32 cache_check; 717 __u32 tlb_check; 718 __u32 bus_check; 719 __u32 assists_check; 720 __u32 rsvd2; 721 __u32 assist_state; 722 __u32 responder_addr; 723 __u32 requestor_addr; 724 __u32 path_info; 725 __u64 fr[32]; 726 }; 727 728 /* 729 * architected results from PDC_PIM/transfer hpmc on a PA2.0 machine 730 * 731 * Note that PDC_PIM doesn't care whether or not wide mode was enabled 732 * so the results are different on PA1.1 vs. PA2.0 when in narrow mode. 733 * 734 * Note also that there are unarchitected results available, which 735 * are hversion dependent. Do a "ser pim 0 hpmc" after rebooting, since 736 * the firmware is probably the best way of printing hversion dependent 737 * data. 738 */ 739 740 struct pdc_hpmc_pim_20 { /* PDC_PIM */ 741 __u64 gr[32]; 742 __u64 cr[32]; 743 __u64 sr[8]; 744 __u64 iasq_back; 745 __u64 iaoq_back; 746 __u32 check_type; 747 __u32 cpu_state; 748 __u32 cache_check; 749 __u32 tlb_check; 750 __u32 bus_check; 751 __u32 assists_check; 752 __u32 assist_state; 753 __u32 path_info; 754 __u64 responder_addr; 755 __u64 requestor_addr; 756 __u64 fr[32]; 757 }; 758 759 #endif /* __ASSEMBLY__ */ 760 761 /* flags of the device_path (see below) */ 762 #define PF_AUTOBOOT 0x80 763 #define PF_AUTOSEARCH 0x40 764 #define PF_TIMER 0x0F 765 766 #ifndef __ASSEMBLY__ 767 768 struct device_path { /* page 1-69 */ 769 unsigned char flags; /* flags see above! */ 770 unsigned char bc[6]; /* bus converter routing info */ 771 unsigned char mod; 772 unsigned int layers[6];/* device-specific layer-info */ 773 } __attribute__((aligned(8))) ; 774 775 struct pz_device { 776 struct device_path dp; /* see above */ 777 /* struct iomod *hpa; */ 778 unsigned int hpa; /* HPA base address */ 779 /* char *spa; */ 780 unsigned int spa; /* SPA base address */ 781 /* int (*iodc_io)(struct iomod*, ...); */ 782 unsigned int iodc_io; /* device entry point */ 783 short pad; /* reserved */ 784 unsigned short cl_class;/* see below */ 785 } __attribute__((aligned(8))) ; 786 787 #endif /* __ASSEMBLY__ */ 788 789 /* cl_class 790 * page 3-33 of IO-Firmware ARS 791 * IODC ENTRY_INIT(Search first) RET[1] 792 */ 793 #define CL_NULL 0 /* invalid */ 794 #define CL_RANDOM 1 /* random access (as disk) */ 795 #define CL_SEQU 2 /* sequential access (as tape) */ 796 #define CL_DUPLEX 7 /* full-duplex point-to-point (RS-232, Net) */ 797 #define CL_KEYBD 8 /* half-duplex console (HIL Keyboard) */ 798 #define CL_DISPL 9 /* half-duplex console (display) */ 799 #define CL_FC 10 /* FiberChannel access media */ 800 801 #if 0 802 /* FIXME: DEVCLASS_* duplicates CL_* (above). Delete DEVCLASS_*? */ 803 #define DEVCLASS_RANDOM 1 804 #define DEVCLASS_SEQU 2 805 #define DEVCLASS_DUPLEX 7 806 #define DEVCLASS_KEYBD 8 807 #define DEVCLASS_DISP 9 808 #endif 809 810 /* IODC ENTRY_INIT() */ 811 #define ENTRY_INIT_SRCH_FRST 2 812 #define ENTRY_INIT_SRCH_NEXT 3 813 #define ENTRY_INIT_MOD_DEV 4 814 #define ENTRY_INIT_DEV 5 815 #define ENTRY_INIT_MOD 6 816 #define ENTRY_INIT_MSG 9 817 818 /* IODC ENTRY_IO() */ 819 #define ENTRY_IO_BOOTIN 0 820 #define ENTRY_IO_BOOTOUT 1 821 #define ENTRY_IO_CIN 2 822 #define ENTRY_IO_COUT 3 823 #define ENTRY_IO_CLOSE 4 824 #define ENTRY_IO_GETMSG 9 825 #define ENTRY_IO_BBLOCK_IN 16 826 #define ENTRY_IO_BBLOCK_OUT 17 827 828 /* IODC ENTRY_SPA() */ 829 830 /* IODC ENTRY_CONFIG() */ 831 832 /* IODC ENTRY_TEST() */ 833 834 /* IODC ENTRY_TLB() */ 835 836 837 /* DEFINITION OF THE ZERO-PAGE (PAG0) */ 838 /* based on work by Jason Eckhardt (jason@equator.com) */ 839 840 #ifndef __ASSEMBLY__ 841 842 #define PAGE0 ((struct zeropage *)__PAGE_OFFSET) 843 844 struct zeropage { 845 /* [0x000] initialize vectors (VEC) */ 846 unsigned int vec_special; /* must be zero */ 847 /* int (*vec_pow_fail)(void);*/ 848 unsigned int vec_pow_fail; /* power failure handler */ 849 /* int (*vec_toc)(void); */ 850 unsigned int vec_toc; 851 unsigned int vec_toclen; 852 /* int (*vec_rendz)(void); */ 853 unsigned int vec_rendz; 854 int vec_pow_fail_flen; 855 int vec_pad[10]; 856 857 /* [0x040] reserved processor dependent */ 858 int pad0[112]; 859 860 /* [0x200] reserved */ 861 int pad1[84]; 862 863 /* [0x350] memory configuration (MC) */ 864 int memc_cont; /* contiguous mem size (bytes) */ 865 int memc_phsize; /* physical memory size */ 866 int memc_adsize; /* additional mem size, bytes of SPA space used by PDC */ 867 unsigned int mem_pdc_hi; /* used for 64-bit */ 868 869 /* [0x360] various parameters for the boot-CPU */ 870 /* unsigned int *mem_booterr[8]; */ 871 unsigned int mem_booterr[8]; /* ptr to boot errors */ 872 unsigned int mem_free; /* first location, where OS can be loaded */ 873 /* struct iomod *mem_hpa; */ 874 unsigned int mem_hpa; /* HPA of the boot-CPU */ 875 /* int (*mem_pdc)(int, ...); */ 876 unsigned int mem_pdc; /* PDC entry point */ 877 unsigned int mem_10msec; /* number of clock ticks in 10msec */ 878 879 /* [0x390] initial memory module (IMM) */ 880 /* struct iomod *imm_hpa; */ 881 unsigned int imm_hpa; /* HPA of the IMM */ 882 int imm_soft_boot; /* 0 = was hard boot, 1 = was soft boot */ 883 unsigned int imm_spa_size; /* SPA size of the IMM in bytes */ 884 unsigned int imm_max_mem; /* bytes of mem in IMM */ 885 886 /* [0x3A0] boot console, display device and keyboard */ 887 struct pz_device mem_cons; /* description of console device */ 888 struct pz_device mem_boot; /* description of boot device */ 889 struct pz_device mem_kbd; /* description of keyboard device */ 890 891 /* [0x430] reserved */ 892 int pad430[116]; 893 894 /* [0x600] processor dependent */ 895 __u32 pad600[1]; 896 __u32 proc_sti; /* pointer to STI ROM */ 897 __u32 pad608[126]; 898 }; 899 900 #endif /* __ASSEMBLY__ */ 901 902 /* Page Zero constant offsets used by the HPMC handler */ 903 904 #define BOOT_CONSOLE_HPA_OFFSET 0x3c0 905 #define BOOT_CONSOLE_SPA_OFFSET 0x3c4 906 #define BOOT_CONSOLE_PATH_OFFSET 0x3a8 907 908 #ifndef __ASSEMBLY__ 909 void pdc_console_init(void); /* in pdc_console.c */ 910 void pdc_console_restart(void); 911 912 void setup_pdc(void); /* in inventory.c */ 913 914 /* wrapper-functions from pdc.c */ 915 916 int pdc_add_valid(unsigned long address); 917 int pdc_chassis_info(struct pdc_chassis_info *chassis_info, void *led_info, unsigned long len); 918 int pdc_chassis_disp(unsigned long disp); 919 int pdc_coproc_cfg(struct pdc_coproc_cfg *pdc_coproc_info); 920 int pdc_iodc_read(unsigned long *actcnt, unsigned long hpa, unsigned int index, 921 void *iodc_data, unsigned int iodc_data_size); 922 int pdc_system_map_find_mods(struct pdc_system_map_mod_info *pdc_mod_info, 923 struct pdc_module_path *mod_path, long mod_index); 924 int pdc_system_map_find_addrs(struct pdc_system_map_addr_info *pdc_addr_info, 925 long mod_index, long addr_index); 926 int pdc_model_info(struct pdc_model *model); 927 int pdc_model_sysmodel(char *name); 928 int pdc_model_cpuid(unsigned long *cpu_id); 929 int pdc_model_versions(unsigned long *versions, int id); 930 int pdc_model_capabilities(unsigned long *capabilities); 931 int pdc_cache_info(struct pdc_cache_info *cache); 932 #ifndef CONFIG_PA20 933 int pdc_btlb_info(struct pdc_btlb_info *btlb); 934 int pdc_mem_map_hpa(struct pdc_memory_map *r_addr, struct pdc_module_path *mod_path); 935 #endif /* !CONFIG_PA20 */ 936 int pdc_lan_station_id(char *lan_addr, unsigned long net_hpa); 937 938 int pdc_pci_irt_size(unsigned long *num_entries, unsigned long hpa); 939 int pdc_pci_irt(unsigned long num_entries, unsigned long hpa, void *tbl); 940 941 int pdc_get_initiator(struct hardware_path *hwpath, unsigned char *scsi_id, unsigned long *period, char *width, char *mode); 942 int pdc_tod_read(struct pdc_tod *tod); 943 int pdc_tod_set(unsigned long sec, unsigned long usec); 944 945 #ifdef __LP64__ 946 int pdc_mem_mem_table(struct pdc_memory_table_raddr *r_addr, 947 struct pdc_memory_table *tbl, unsigned long entries); 948 #endif 949 950 int pdc_do_firm_test_reset(unsigned long ftc_bitmap); 951 int pdc_do_reset(void); 952 int pdc_soft_power_info(unsigned long *power_reg); 953 int pdc_soft_power_button(int sw_control); 954 void pdc_suspend_usb(void); 955 int pdc_iodc_getc(void); 956 void pdc_iodc_putc(unsigned char c); 957 void pdc_iodc_outc(unsigned char c); 958 959 void pdc_emergency_unlock(void); 960 int pdc_sti_call(unsigned long func, unsigned long flags, 961 unsigned long inptr, unsigned long outputr, 962 unsigned long glob_cfg); 963 964 #ifdef __LP64__ 965 int pdc_pat_chassis_send_log(unsigned long status, unsigned long data); 966 967 int pdc_pat_cell_get_number(struct pdc_pat_cell_num *cell_info); 968 int pdc_pat_cell_module(unsigned long *actcnt, unsigned long ploc, unsigned long mod, 969 unsigned long view_type, void *mem_addr); 970 int pdc_pat_cpu_get_number(struct pdc_pat_cpu_num *cpu_info, void *hpa); 971 int pdc_pat_get_irt_size(unsigned long *num_entries, unsigned long cell_num); 972 int pdc_pat_get_irt(void *r_addr, unsigned long cell_num); 973 int pdc_pat_pd_get_addr_map(unsigned long *actual_len, void *mem_addr, 974 unsigned long count, unsigned long offset); 975 976 /******************************************************************** 977 * PDC_PAT_CELL[Return Cell Module] memaddr[0] conf_base_addr 978 * ---------------------------------------------------------- 979 * Bit 0 to 51 - conf_base_addr 980 * Bit 52 to 62 - reserved 981 * Bit 63 - endianess bit 982 ********************************************************************/ 983 #define PAT_GET_CBA(value) ((value) & 0xfffffffffffff000UL) 984 985 /******************************************************************** 986 * PDC_PAT_CELL[Return Cell Module] memaddr[1] mod_info 987 * ---------------------------------------------------- 988 * Bit 0 to 7 - entity type 989 * 0 = central agent, 1 = processor, 990 * 2 = memory controller, 3 = system bus adapter, 991 * 4 = local bus adapter, 5 = processor bus converter, 992 * 6 = crossbar fabric connect, 7 = fabric interconnect, 993 * 8 to 254 reserved, 255 = unknown. 994 * Bit 8 to 15 - DVI 995 * Bit 16 to 23 - IOC functions 996 * Bit 24 to 39 - reserved 997 * Bit 40 to 63 - mod_pages 998 * number of 4K pages a module occupies starting at conf_base_addr 999 ********************************************************************/ 1000 #define PAT_GET_ENTITY(value) (((value) >> 56) & 0xffUL) 1001 #define PAT_GET_DVI(value) (((value) >> 48) & 0xffUL) 1002 #define PAT_GET_IOC(value) (((value) >> 40) & 0xffUL) 1003 #define PAT_GET_MOD_PAGES(value) ((value) & 0xffffffUL) 1004 1005 #else /* !__LP64__ */ 1006 /* No PAT support for 32-bit kernels...sorry */ 1007 #define pdc_pat_get_irt_size(num_entries, cell_numn) PDC_BAD_PROC 1008 #define pdc_pat_get_irt(r_addr, cell_num) PDC_BAD_PROC 1009 #endif /* !__LP64__ */ 1010 1011 extern void pdc_init(void); 1012 1013 #endif /* __ASSEMBLY__ */ 1014 1015 #endif /* _PARISC_PDC_H */ 1016