1 2 /* DO NOT EDIT!! - this file automatically generated 3 * from .s file by awk -f s2h.awk 4 */ 5 /*********************************************************************** 6 * Copyright ARM Limited 1998 - 2001. All rights reserved. 7 * ************************************************************************ 8 * 9 * Omaha address map 10 * 11 * NOTE: This is a multi-hosted header file for use with uHAL and 12 * supported debuggers. 13 * 14 * $Id: platform.h,v 1.12 2002/08/22 15:49:56 ahaigh Exp $ 15 * 16 * Everything is defined in terms of PLAT_* and then the key values 17 * are redefined as required for uHAL. 18 * 19 * NOTE: If things are defined in terms of a BASE and lots of OFFSETs, 20 * the code will be more portable and amenable to being used in 21 * different (physical vs virtual) memory maps - just change the 22 * base and the rest will work! 23 * 24 * ***********************************************************************/ 25 26 #ifndef __address_h 27 #define __address_h 1 28 29 #include "bits.h" 30 31 #define PLATFORM_ID 0x00000800 /* TBD */ 32 33 /* Common modules for uHAL can be included or excluded by changing these 34 * definitions. These can be over-ridden by the makefile/ARM project file 35 * provided the .h file is rebuilt. 36 */ 37 38 #ifndef USE_C_LIBRARY 39 #define USE_C_LIBRARY 0 40 #endif 41 #ifndef uHAL_HEAP 42 #define uHAL_HEAP 1 43 #endif 44 #ifndef uHAL_PCI 45 #define uHAL_PCI 0 46 #endif 47 48 49 /* ----------------------------------------------------------------------- 50 * 51 * uHAL always has RAM at 0 and, when a MMU is used, maps everything else 52 * 1-1 physical to virtual. 53 */ 54 55 /* ======================================================================= 56 * Omaha 57 * ======================================================================= 58 * ----------------------------------------------------------------------- 59 * Memory definitions 60 * ----------------------------------------------------------------------- 61 */ 62 63 /* New world memory.... 64 */ 65 66 /* We have eight banks of 32MB, covering the first 256Mb of address space 67 */ 68 69 /* Bank Function 70 * 0 Flash 71 * 1 TBD / ROM 72 * 2 TBD / ROM 73 * 3 FPGA / sub-chip-selects 74 * 4 TBD / ROM 75 * 5 TBD / ROM 76 * 6 SDRAM Bank 0 77 * 7 SDRAM Bank 1 78 */ 79 80 81 /* SDRAM : 64Mbytes. 82 * 83 * Two banks of 32-bit SDRAM, each 32Mbytes in size. 84 * Bank 0 is on nGCS6, bank 1 is on nGCS7 85 */ 86 87 /* Physical address 88 */ 89 #define PLAT_SDRAM_PHYS0 0x0C000000 /* @ 192Mb */ 90 #define PLAT_SDRAM_PHYS1 0x0E000000 /* @ 224Mb */ 91 92 /* Size of one SDRAM bank 93 */ 94 #define PLAT_SDRAM_BANKSIZE SZ_32M 95 96 /* Virtual address 97 */ 98 #define PLAT_SDRAM_BASE 0x00000000 99 #define PLAT_SDRAM_SIZE SZ_64M 100 101 /* Put page tables in top 1MB of memory; don't let the user access this area. 102 */ 103 #define PLAT_PAGETABLE_BASE 0x0FFF0000 104 #define PLAT_USER_SDRAM_SIZE PLAT_SDRAM_SIZE - SZ_1M 105 106 /* Flash : 0.5MBytes 107 * 108 * One bank of 8-bit Flash on nGCS0 (SST39VF040-90-4C-NH) 109 */ 110 111 /* Physical flash device base address 112 */ 113 #define PLAT_FLASH_PHYS 0x00000000 /* nCS0 */ 114 115 /* Logical address for flash 116 */ 117 #define PLAT_FLASH_BASE SZ_64M 118 #define PLAT_FLASH_UNCACHED SZ_128M 119 #define PLAT_FLASH_DEVICE_SIZE SZ_512K 120 #define PLAT_FLASH_SIZE SZ_512K 121 122 /* Notes 123 * We do not map physical devices at their physical 124 * addresses, because this would overlap the 64Mb of RAM 125 * at the bottom of memory. Instead, they are mostly mapped 126 * at 0x20000000 + Physical address instead 127 * (CPU internal registers live at 0x10000000 + something) 128 */ 129 130 /* FPGA space (all of nGCS 3) 131 */ 132 #define PLAT_FPGA_PHYS 0x06000000 133 #define PLAT_FPGA_BASE 0x26000000 134 #define PLAT_FPGA_SIZE SZ_32M 135 136 /* PLD live in PLD space in nGCS1 137 */ 138 #define PLAT_PLD_PHYS 0x02800000 139 #define PLAT_PLD_BASE 0x22800000 140 #define PLAT_PLD_SIZE SZ_8M 141 142 /* USB2 space 143 */ 144 #define PLAT_USB2_PHYS 0x04000000 145 #define PLAT_USB2_BASE 0x24000000 146 #define PLAT_USB2_SIZE 0x00200000 147 148 /* Ethernet space 149 */ 150 #define PLAT_ETHERNET_PHYS 0x02200000 151 #define PLAT_ETHERNET_BASE 0x22200000 152 #define PLAT_ETHERNET_SIZE 0x00200000 153 154 /* TAP Controller space 155 */ 156 #define PLAT_TAP_PHYS PLAT_FPGA_PHYS 157 #define PLAT_TAP_BASE PLAT_FPGA_BASE 158 #define PLAT_TAP_SIZE SZ_32M 159 160 /* CompactFlash address space (top half on nGCS1) 161 */ 162 163 /* Notes about the CompactFlash implementation (rev b): 164 * 165 * Since we only need CF ATA cards to work, we 166 * use TrueIDE mode for simplicity. 167 * 168 * However, we need 8-bit access to the Command 169 * Registers, and 16-bit access to the Data-Register. 170 * So we have to access the CF card in two chip select 171 * regions: nCS0 and nCS2. 172 * 173 * In the case of TrueIDE mode, we get the following 174 * (physical) address usage: 175 * 176 * 0x01C00000 - 0x01C00007 - Command Registers (8-bit r/w) 177 * 0x01E00006 - 0x01E00006 - Control Register (8-bit r/w) 178 * 0x05C00000 - 0x05C00001 - Data Register (16-bit r/w) 179 * 180 */ 181 182 /* CF 16-bit access in nCS2 183 */ 184 #define PLAT_PCMCIA_PHYS 0x05000000 185 #define PLAT_PCMCIA_BASE 0x25000000 186 #define PLAT_PCMCIA_SIZE 0x01000000 187 188 /* CF 8-bit access in nCS0 189 */ 190 #define PLAT_PCMCIA_8_PHYS 0x01000000 191 #define PLAT_PCMCIA_8_BASE 0x21000000 192 #define PLAT_PCMCIA_8_SIZE 0x01000000 193 194 /* Offsets into CF region (applies to both CS regions) 195 */ 196 #define PLAT_PCMCIA_ATTR 0x00800000 197 #define PLAT_PCMCIA_MEM 0x00A00000 198 #define PLAT_PCMCIA_IO 0x00C00000 /* CE1 in TrueIDE */ 199 #define PLAT_PCMCIA_IO_ALT 0x00E00000 /* CE2 in TrueIDE */ 200 201 /* Expansion Bus memory region (nGCS4 and nGCS5) 202 */ 203 #define PLAT_BUS_PHYS 0x08000000 204 #define PLAT_BUS_BASE 0x28000000 205 #define PLAT_BUS_SIZE 0x04000000 206 207 /* Location of high vectors used by operating system 208 * If we may this, then we can seamlessly debug 209 * from a uHAL program into an OS using high-vectors, 210 * since we are always going to need exception handlers, 211 * and they can only be in two places (0x0 and 0xFFFF0000)! 212 */ 213 #define PLAT_HIVECS_PHYS 0xFFFF0000 214 #define PLAT_HIVECS_BASE 0xFFFF0000 215 #define PLAT_HIVECS_SIZE SZ_1M 216 217 /* Remaining chip-select regions 218 * Leave these un-mapped for the moment 219 */ 220 221 222 /* ---------------------------------------------------------------------- 223 * S3C2400X01 CPU peripherals 224 * ----------------------------------------------------------------------- 225 */ 226 227 /* AHB peripherals appear in the lower 16Mb, APB in the upper 16Mb 228 */ 229 230 /* All peripherals are offsets from PLAT_PERIPHERAL_BASE 231 */ 232 233 #define PLAT_PERIPHERAL_BASE 0x14000000 234 #define PLAT_PERIPHERAL_SIZE SZ_32M 235 236 /* Memory Controller 237 */ 238 #define OMAHA_BWSCON 0x00 /* Bus width and wait state control */ 239 #define OMAHA_BANKCON0 0x04 /* Boot ROM control (Bank 0) */ 240 #define OMAHA_BANKCON1 0x08 /* Bank 1 control */ 241 #define OMAHA_BANKCON2 0x0C /* Bank 2 control */ 242 #define OMAHA_BANKCON3 0x10 /* Bank 3 control */ 243 #define OMAHA_BANKCON4 0x14 /* Bank 4 control */ 244 #define OMAHA_BANKCON5 0x18 /* Bank 5 control */ 245 #define OMAHA_BANKCON6 0x1C /* Bank 6 control */ 246 #define OMAHA_BANKCON7 0x20 /* Bank 7 control */ 247 248 #define OMAHA_REFRESH 0x24 /* SDRAM refresh control */ 249 #define OMAHA_BANKSIZE 0x28 /* Flexible bank size */ 250 #define OMAHA_MRSRB6 0x2C /* Mode register set for SDRAM Bank 0 (nGCS6) */ 251 #define OMAHA_MRSRB7 0x30 /* Mode register set for SDRAM Bank 1 (nGCS7) */ 252 253 /* Interrupt controller 254 */ 255 #define OMAHA_SRCPND 0x400000 /* Interrupt sources pending */ 256 #define OMAHA_INTMOD 0x400004 /* Interrupt mode control */ 257 #define OMAHA_INTMSK 0x400008 /* Interrupt mask control */ 258 #define OMAHA_PRIORITY 0x40000C /* Int. priority control */ 259 #define OMAHA_INTPND 0x400010 /* Interrupts pending */ 260 #define OMAHA_INTOFFSET 0x400014 /* IRQ source */ 261 262 /* Clock / Power management 263 */ 264 #define OMAHA_LOCKTIME 0x800000 /* PLL Lock time counter */ 265 #define OMAHA_MPLLCON 0x800004 /* MPLL Control */ 266 #define OMAHA_UPLLCON 0x800008 /* UPLL Control */ 267 #define OMAHA_CLKCON 0x80000C /* Clock control */ 268 #define OMAHA_CLKSLOW 0x800010 /* Slow clock control */ 269 #define OMAHA_CLKDIVN 0x800014 /* Clock divider control */ 270 271 /* LCD Control 272 */ 273 274 /* UARTs 275 */ 276 #define OMAHA_ULCON0 0x1000000 /* UART 0 Line control */ 277 #define OMAHA_ULCON1 0x1004000 /* UART 1 Line control */ 278 279 /* PWM Timers 280 */ 281 #define OMAHA_TCFG0 0x1100000 /* Timer 0 config */ 282 #define OMAHA_TCFG1 0x1100004 /* Timer 1 config */ 283 #define OMAHA_TCON 0x1100008 /* Timer control */ 284 #define OMAHA_TCNTB0 0x110000C /* Timer count buffer 0 */ 285 #define OMAHA_TCMPB0 0x1100010 /* Timer Compare buffer 0 */ 286 #define OMAHA_TCNTO0 0x1100014 /* Timer count observation 0 */ 287 #define OMAHA_TCNTB1 0x1100018 /* Timer count buffer 1 */ 288 #define OMAHA_TCMPB1 0x110001C /* Timer compare buffer 1 */ 289 #define OMAHA_TCNTO1 0x1100020 /* Timer count observation 1 */ 290 #define OMAHA_TCNTB2 0x1100024 /* Timer count buffer 2 */ 291 #define OMAHA_TCMPB2 0x1100028 /* Timer compare buffer 2 */ 292 #define OMAHA_TCNTO2 0x110002C /* Timer count observation 2 */ 293 #define OMAHA_TCNTB3 0x1100030 /* Timer count buffer 3 */ 294 #define OMAHA_TCMPB3 0x1100034 /* Timer compare buffer 3 */ 295 #define OMAHA_TCNTO3 0x1100038 /* Timer count observation 3 */ 296 #define OMAHA_TCNTB4 0x110003C /* Timer count buffer 2 */ 297 #define OMAHA_TCNTO4 0x1100040 /* Timer count observation 2 */ 298 299 /* DMA 300 */ 301 #define OMAHA_DMA_CON 0x12001C0 /* DMA Interface control */ 302 #define OMAHA_DMA_UNIT 0x12001C4 /* DMA Transfer unit counter */ 303 #define OMAHA_DMA_FIFO 0x12001C8 /* DMA Transfer FIFO counter */ 304 #define OMAHA_DMA_TX 0x12001CC /* DMA Total transfer counter */ 305 306 /* Watchdog 307 */ 308 #define OMAHA_WTCON 0x1300000 /* Watchdog control register */ 309 #define OMAHA_WTDAT 0x1300004 /* Watchdog data */ 310 #define OMAHA_WTCNT 0x1300008 /* Watchdog count */ 311 #define OMAHA_WT_DEF 0x0 /* Disable the watchdog */ 312 313 /* IIC 314 */ 315 #define OMAHA_IICCON 0x1400000 /* IIC Control */ 316 #define OMAHA_IICSTAT 0x1400004 /* IIC Status */ 317 #define OMAHA_IICADD 0x1400008 /* IIC address */ 318 #define OMAHA_IICDS 0x140000C /* IIC Data shift */ 319 320 /* IIS 321 */ 322 #define OMAHA_IISCON 0x1508000 /* IIS Control */ 323 #define OMAHA_IISMOD 0x1508004 /* IIS Mode */ 324 #define OMAHA_IISPSR 0x1508008 /* IIS Prescaler */ 325 #define OMAHA_IISFIFOCON 0x150800C /* IIS FIFO control */ 326 #define OMAHA_IISFIF 0x1508010 /* IIS Fifo entry */ 327 328 /* I/O Ports (GPIO's) 329 */ 330 #define OMAHA_PACON 0x1600000 /* Port A control */ 331 #define OMAHA_PADAT 0x1600004 /* Port A data */ 332 #define OMAHA_PBCON 0x1600008 /* Port B control */ 333 #define OMAHA_PBDAT 0x160000C /* Port B data */ 334 #define OMAHA_PBUP 0x1600010 /* Port B pull-up control */ 335 #define OMAHA_PCCON 0x1600014 /* Port C control */ 336 #define OMAHA_PCDAT 0x1600018 /* Port C data */ 337 #define OMAHA_PCUP 0x160001C /* Port C pull-up */ 338 #define OMAHA_PDCON 0x1600020 /* Port D control */ 339 #define OMAHA_PDDAT 0x1600024 /* Port D data */ 340 #define OMAHA_PDUP 0x1600028 /* Port D pull-up */ 341 #define OMAHA_PECON 0x160002C /* Port E control */ 342 #define OMAHA_PEDAT 0x1600030 /* Port E data */ 343 #define OMAHA_PEUP 0x1600034 /* Port E pull-up */ 344 #define OMAHA_PFCON 0x1600038 /* Port F control */ 345 #define OMAHA_PFDAT 0x160003C /* Port F data */ 346 #define OMAHA_PFUP 0x1600040 /* Port F pull-up */ 347 #define OMAHA_PGCON 0x1600044 /* Port G control */ 348 #define OMAHA_PGDAT 0x1600048 /* Port G data */ 349 #define OMAHA_PGUP 0x160004C /* Port G pull-up */ 350 #define OMAHA_OPENCR 0x1600050 /* Open Drain enable */ 351 #define OMAHA_MISCCR 0x1600054 /* Misc. control */ 352 #define OMAHA_EXTINT 0x1600058 /* External interrupt control */ 353 354 /* RTC 355 */ 356 #define OMAHA_RTCCON 0x1700040 /* RTC Control */ 357 #define OMAHA_TICINT 0x1700044 /* Tick time count */ 358 #define OMAHA_RTCALM 0x1700050 /* RTC Alarm control */ 359 #define OMAHA_ALMSEC 0x1700054 /* Alarm Second */ 360 #define OMAHA_ALMMIN 0x1700058 /* Alarm Minute */ 361 #define OMAHA_ALMHOUR 0x170005C /* Alarm Hour */ 362 #define OMAHA_ALMDAY 0x1700060 /* Alarm Day */ 363 #define OMAHA_ALMMON 0x1700064 /* Alarm Month */ 364 #define OMAHA_ALMYEAR 0x1700068 /* Alarm Year */ 365 #define OMAHA_RTCRST 0x170006C /* RTC Round Reset */ 366 #define OMAHA_BCDSEC 0x1700070 /* BCD Second */ 367 #define OMAHA_BCDMIN 0x1700074 /* BCD Minute */ 368 #define OMAHA_BCDHOUR 0x1700078 /* BCD Hour */ 369 #define OMAHA_BCDDAY 0x170007C /* BCD Day */ 370 #define OMAHA_BCDDATE 0x1700080 /* BCD Date */ 371 #define OMAHA_BCDMON 0x1700084 /* BCD Month */ 372 #define OMAHA_BCDYEAR 0x1700088 /* BCD Year */ 373 374 /* ADC 375 */ 376 #define OMAHA_ADCCON 0x1800000 /* ADC control */ 377 #define OMAHA_ADCDAT 0x1800004 /* ADC data */ 378 379 /* SPI 380 */ 381 #define OMAHA_SPCON 0x1900000 /* SPI Control */ 382 #define OMAHA_SPSTA 0x1900004 /* SPI status */ 383 #define OMAHA_SPPIN 0x1900008 /* SPI pin control */ 384 #define OMAHA_SPPRE 0x190000C /* Baud rate prescaler */ 385 #define OMAHA_SPTDAT 0x1900010 /* SPI Tx data */ 386 #define OMAHA_SPRDAT 0x1900014 /* SPI Rx data */ 387 388 /* MMC 389 */ 390 391 /* Memory timings 392 */ 393 394 /* nGCS0: 8-bit r/o, no-wait. boot flash 395 * nGCS1: 32-bit, r/w, no-wait. PLD (inc. ethernet) 396 * nGCS2: 16-bit, r/w, wait. CompactFlash+USB2 397 * nGCS3: 32-bit, r/w, no-wait. FPGA 398 * nGCS4: 32-bit, r/w, no-wait. Expansion Bus 399 * nGCS5: 32-bit, r/w, no-wait. Expansion Bus 400 * nGCS6: 32-bit, r/w, no-wait. SDRAM bank 0 401 * nGCS7: 32-bit, r/w, no-wait. SDRAM bank 1 402 */ 403 404 #define OMAHA_BWSCON_DEF 0x222221A0 /* All 32-bit, r/w, no-wait */ 405 406 /* Functions: 407 * CS0 - Flash bank 0 408 * CS1 - PLD 409 * CS2 - FPGA 410 * CS3 - FPGA 411 * CS4 - PCMCIA0 (Unused) 412 * CS5 - PCMCIA1 (Unused) 413 */ 414 415 /* CS0 Intel flash devices: 416 */ 417 #define OMAHA_BANKCON0_DEF 0x00007FFC /* Maximum clocks/function */ 418 #define OMAHA_BANKCON1_DEF 0x00007FFC /* Maximum clocks/function */ 419 #define OMAHA_BANKCON2_DEF 0x00007FFC /* Maximum clocks/function */ 420 #define OMAHA_BANKCON3_DEF 0x00002400 /* tacs=1, tacc = 6clks */ 421 #define OMAHA_BANKCON4_DEF 0x00007FFC /* Maximum clocks/function */ 422 #define OMAHA_BANKCON5_DEF 0x00007FFC /* Maximum clocks/function */ 423 424 /* CS6 SDRAM0 425 */ 426 #define OMAHA_BANKCON6_DEF 0x00018001 /* 9-bit, 2clks */ 427 428 /* CS7 SDRAM1 429 */ 430 #define OMAHA_BANKCON7_DEF 0x00018001 /* 9-bit, 2clks */ 431 432 /* refresh (Assumes HCLK = 66MHz) 433 * refresh period = 64msecs (from datasheet) for 8K cycles (8usecs each) 434 * @66MHz busclock, this is 533 cycles... 435 */ 436 #define OMAHA_REFRESH_DEF 0x00A405EC /* Refresh enabled, max clk. */ 437 438 #define OMAHA_BANKSIZE_DEF 0x00000000 /* 32Mb/32Mb */ 439 440 /* mode register (CL = 3) 441 */ 442 #define OMAHA_MRSRB6_DEF 0x00000030 443 #define OMAHA_MRSRB7_DEF 0x00000030 444 445 /* ----------------------------------------------------------------------- 446 * CPU Clocking 447 * ----------------------------------------------------------------------- 448 */ 449 450 /* There are three important clock domains 451 * FCLK - CPU clock 452 * HCLK - AHB clock 453 * PCLK - APB clock 454 */ 455 456 /* All clocks are derived from a 12MHz Xtal fed through 457 * PLL's and dividers. 458 * 459 * Note: 460 * HCLK = FCLK / 2 461 * PCLK = HCLK / 2 462 * 463 * Eg. for FCLK = 133MHz, HCLK = 66MHz, PCLK = 33MHz 464 */ 465 466 #define OMAHA_LOCKTIME_DEF 0xFFFFFF /* PLL synchronization time */ 467 468 /* Nearest values (Samsung recommended from 12MHz xtal) 469 */ 470 #define OMAHA_CLK_33M 0x25003 /* ; 33.75 MHz */ 471 #define OMAHA_CLK_66M 0x25002 /* 67.50 MHz */ 472 #define OMAHA_CLK_100M 0x2B011 /* 102.00 MHz */ 473 #define OMAHA_CLK_133M 0x51021 /* 133.50 MHz */ 474 475 /* Full speed ahead! 476 */ 477 #define OMAHA_CLK_DEFAULT OMAHA_CLK_133M 478 479 /* Don't trust the PLL, use SLOW mode (HCLK = 12MHz direct) 480 * OMAHA_SLOW EQU 1 481 */ 482 483 /* ----------------------------------------------------------------------- 484 * From PrimeCell UART (PL010) Block Specification (ARM-DDI-0139B) 485 * ----------------------------------------------------------------------- 486 * UART Base register absolute address 487 */ 488 #define OMAHA_UART0_BASE 0x15000000 /* Uart 0 base */ 489 #define OMAHA_UART1_BASE 0x15004000 /* Uart 1 base */ 490 491 /* Offsets into registers of each UART controller 492 */ 493 #define OMAHA_ULCON 0x00 /* Line control */ 494 #define OMAHA_UCON 0x04 /* Control */ 495 #define OMAHA_UFCON 0x08 /* FIFO control */ 496 #define OMAHA_UMCON 0x0C /* Modem control */ 497 #define OMAHA_UTRSTAT 0x10 /* Rx/Tx status */ 498 #define OMAHA_UERSTAT 0x14 /* Rx Error Status */ 499 #define OMAHA_UFSTAT 0x18 /* FIFO status */ 500 #define OMAHA_UMSTAT 0x1C /* Modem status */ 501 #define OMAHA_UTXH 0x20 /* Transmission Hold (byte wide) */ 502 #define OMAHA_URXH 0x24 /* Receive buffer (byte wide) */ 503 #define OMAHA_UBRDIV 0x28 /* Baud rate divisor */ 504 505 /* UART status flags in OMAHA_UTRSTAT 506 */ 507 #define OMAHA_URX_FULL 0x1 /* Receive buffer has valid data */ 508 #define OMAHA_UTX_EMPTY 0x2 /* Transmitter has finished */ 509 510 /* Baud rates supported on the uart. */ 511 512 #define ARM_BAUD_460800 460800 513 #define ARM_BAUD_230400 230400 514 #define ARM_BAUD_115200 115200 515 #define ARM_BAUD_57600 57600 516 #define ARM_BAUD_38400 38400 517 #define ARM_BAUD_19200 19200 518 #define ARM_BAUD_9600 9600 519 520 /* LEDs 521 * These are connected to GPIO Port C 522 */ 523 #define PLAT_DBG_LEDS (PLAT_PERIPHERAL_BASE + OMAHA_PCDAT) 524 525 /* ----------------------------------------------------------------------- 526 * Interrupts 527 * ----------------------------------------------------------------------- 528 */ 529 530 /* Interrupt numbers 531 */ 532 #define OMAHA_INT_EINT0 0 /* FPGA */ 533 #define OMAHA_INT_EINT1 1 /* PLD */ 534 #define OMAHA_INT_EINT2 2 /* Expansion Bus */ 535 #define OMAHA_INT_EINT3 3 /* Ethernet */ 536 #define OMAHA_INT_EINT4 4 /* USB2 */ 537 #define OMAHA_INT_EINT5 5 /* Fan */ 538 #define OMAHA_INT_EINT6 6 /* unused */ 539 #define OMAHA_INT_EINT7 7 /* unused */ 540 #define OMAHA_INT_TICK 8 541 #define OMAHA_INT_WDT 9 542 #define OMAHA_INT_TIMER0 10 543 #define OMAHA_INT_TIMER1 11 544 #define OMAHA_INT_TIMER2 12 545 #define OMAHA_INT_TIMER3 13 546 #define OMAHA_INT_TIMER4 14 547 #define OMAHA_INT_UERR 15 548 /* 16 Unused 549 */ 550 #define OMAHA_INT_DMA0 17 551 #define OMAHA_INT_DMA1 18 552 #define OMAHA_INT_DMA2 19 553 #define OMAHA_INT_DMA3 20 554 #define OMAHA_INT_MMC 21 555 #define OMAHA_INT_SPI 22 556 #define OMAHA_INT_URXD0 23 557 #define OMAHA_INT_URXD1 24 558 #define OMAHA_INT_USBD 25 559 #define OMAHA_INT_USBH 26 560 #define OMAHA_INT_IIC 27 561 #define OMAHA_INT_UTXD0 28 562 #define OMAHA_INT_UTXD1 29 563 #define OMAHA_INT_RTC 30 564 #define OMAHA_INT_ADC 31 565 566 /* ----------------------------------------------------------------------- 567 * PLD Control registers (offset from PLAT_PLD_BASE) 568 * ----------------------------------------------------------------------- 569 */ 570 571 /* register offsets from PLAT_PLD_BASE 572 */ 573 #define PLD_FPGA_ID 0x00 /* 8-bit FPGA ID number (ro) */ 574 #define PLD_INT_CTRL 0x04 /* Interrupt control */ 575 #define PLD_INT_STATUS 0x08 /* Interrupt status */ 576 #define PLD_WAIT_STATUS 0x0C /* IO device wait status */ 577 #define PLD_ID 0x10 /* PCB revision number */ 578 #define PLD_BUS 0x14 /* Expansion bus control register */ 579 #define PLD_TEST 0x18 /* 8-bit test register (rw) */ 580 #define PLD_CF 0x1C /* CompactFlash control */ 581 #define PLD_DMA_CTRL 0x20 /* DMA Control register */ 582 583 /* PLD Register bitdefs 584 */ 585 586 /* PLD_FPGA_ID ; contains FPGA Iden 587 */ 588 589 /* INT_CTRL bit-defs 590 */ 591 #define PLD_INT_CTRL_USB BIT0 /* USB */ 592 #define PLD_INT_CTRL_LAN BIT1 /* Ethernet */ 593 594 /* INT_STATUS bit-defs 595 */ 596 #define PLD_INT_STATUS_CF_IDE BIT0 /* CF True-IDE mode (r/w) */ 597 #define PLD_INT_STATUS_nDATACS BIT1 /* SMC91C111 nDATACS control (r/w) */ 598 #define PLD_INT_STATUS_CF_RDY BIT2 /* CompactFlash ready (r/o) */ 599 #define PLD_INT_STATUS_nWP BIT3 /* Flash write protect (r/w) */ 600 601 /* WAIT_STATUS bit-defs 602 */ 603 #define PLD_WAIT_STATUS_USB BIT0 /* USB wait signal active */ 604 #define PLD_WAIT_STATUS_LAN BIT1 /* Ethernet wait signal active */ 605 #define PLD_WAIT_STATUS_CF BIT2 /* CompactFlash wait status */ 606 607 /* ID ; Contains PLD Id 608 */ 609 610 /* BOARD_ADDR 611 */ 612 613 #define PLD_BUS_ADDR 0x0F /* 4-bit expansion bus address */ 614 #define PLD_BUS_nACK BIT4 /* BUS nACK */ 615 #define PLD_BUS_nCLR BIT5 /* BUS nCLR */ 616 #define PLD_BUS_nSTR BIT6 /* BUS nSTR */ 617 #define PLD_BUS_DONE BIT7 /* BUS Done */ 618 619 /* TEST ; 8-bit r/w any value. 620 */ 621 622 /* CF status bitdefs 623 */ 624 #define PLD_CF_WP BIT0 /* r/w */ 625 #define PLD_CF_RDY BIT1 /* CF_RDY r/o */ 626 #define PLD_CF_VS1 BIT2 /* Voltage Sense 1. r/o */ 627 #define PLD_CF_VS2 BIT3 /* Voltage Sense 2. r/o */ 628 #define PLD_CF_RESET BIT4 /* Reset. r/w (TrueIDE active low/else high) */ 629 #define PLD_CF_CD BIT5 /* Card Detect (1 AND 2). r/o */ 630 #define PLD_CF_BVD BIT6 /* Batt. Voltage Detect (1 AND 2). r/o */ 631 #define PLD_CF_nINPACK BIT7 /* Input Acknowlegde. r/o */ 632 633 /* DMA_CTRL 634 */ 635 #define PLD_DMA_BUS BIT4 /* Bus DMA request. r/w */ 636 #define PLD_DMA_USB BIT5 /* USB DMA request. r/w */ 637 #define PLD_DMA_FPGA BIT6 /* FPGA DMA request. r/w */ 638 639 /* ======================================================================= 640 * Start of uHAL definitions 641 * ======================================================================= 642 */ 643 644 #define MAXIRQNUM 31 645 646 #define NR_IRQS (MAXIRQNUM + 1) 647 648 /* ----------------------------------------------------------------------- 649 * LEDs - One available 650 * ----------------------------------------------------------------------- 651 * 652 */ 653 #define uHAL_LED_ON 1 654 #define uHAL_LED_OFF 0 655 #define uHAL_NUM_OF_LEDS 4 656 657 /* Colours may not match reality... 658 */ 659 #define GREEN_LED BIT8 660 #define YELLOW_LED BIT9 661 #define RED_LED BIT10 662 #define RED_LED_1 BIT11 663 #define ALL_LEDS (RED_LED | RED_LED_1 | YELLOW_LED | GREEN_LED) 664 665 #define LED_BANK PLAT_DBG_LEDS 666 667 /* LED definitions. 668 * The bit patterns & base addresses of the individual LEDs 669 */ 670 #define uHAL_LED_MASKS {0, GREEN_LED, YELLOW_LED, RED_LED, RED_LED_1} 671 #define uHAL_LED_OFFSETS {0, (void *)LED_BANK, (void *)LED_BANK, (void *)LED_BANK} 672 673 674 /* ----------------------------------------------------------------------- 675 * Memory definitions - run uHAL out of SDRAM. Reserve top 64K for MMU. 676 */ 677 #define uHAL_MEMORY_SIZE PLAT_USER_SDRAM_SIZE 678 679 680 /* Application Flash 681 */ 682 #define FLASH_BASE PLAT_FLASH_BASE 683 #define WFLASH_BASE PLAT_FLASH_UNCACHED 684 #define FLASH_SIZE PLAT_FLASH_SIZE 685 #define FLASH_END (FLASH_BASE + FLASH_SIZE - 1) 686 #define FLASH_BLOCK_SIZE SZ_4K 687 688 /* Reserve the first sector of flash for the boot switcher. 689 * Note: Changes to PLAT_BOOT_ROM_HI will have to be reflected in 690 * FlashLibrary/Boards/P920/flashMap.h 691 */ 692 #define PLAT_BOOT_ROM_HI FLASH_BASE 693 #define PLAT_BOOT_ROM_SIZE (FLASH_BLOCK_SIZE*0) 694 695 /* Boot Flash 696 */ 697 #define EPROM_BASE PLAT_BOOT_ROM_HI 698 #define EPROM_SIZE PLAT_BOOT_ROM_SIZE 699 #define EPROM_END (EPROM_BASE + EPROM_SIZE - 1) 700 701 702 /* Clean base - an area of memory (usually fast access) which can be read 703 * to ensure the data caches are flushed. 704 */ 705 #define CLEAN_BASE EPROM_BASE 706 707 /* ----------------------------------------------------------------------- 708 * UART definitions 709 */ 710 711 /* Which com port can the OS use? 712 * 713 */ 714 /* Default port to talk to host (via debugger) */ 715 #define HOST_COMPORT OMAHA_UART0_BASE 716 #define HOST_IRQBIT_NUMBER OMAHA_INT_URXD0 717 #define HOST_IRQBIT (1 << HOST_IRQBIT_NUMBER) 718 719 /* Default port for use by Operating System or program */ 720 #define OS_COMPORT OMAHA_UART0_BASE 721 #define OS_IRQBIT_NUMBER OMAHA_INT_URXD0 722 #define OS_IRQBIT (1 << OS_IRQBIT_NUMBER) 723 724 #define DEBUG_COMPORT OS_COMPORT 725 #define DEBUG_IRQBIT OS_IRQBIT 726 727 /* Values to set given baud rates */ 728 #define DEFAULT_HOST_BAUD ARM_BAUD_9600 729 #define DEFAULT_OS_BAUD ARM_BAUD_38400 730 731 /* 'C' macros to access comports */ 732 #define GET_STATUS(p) (IO_READ((p) + OMAHA_UTRSTAT)) 733 #define GET_CHAR(p) ((IO_READ((p) + OMAHA_URXH)) & 0xFF) 734 #define PUT_CHAR(p, c) (IO_WRITE(((p) + OMAHA_UTXH), (c))) 735 #define IO_READ(p) (*(volatile unsigned int *)(p)) 736 #define IO_WRITE(p, c) (*(unsigned int *)(p) = (c)) 737 #define IO_MASK_WRITE(p, m, c) IO_WRITE(p, (IO_READ(p) & ~(m)) | (c)) 738 #define IO_SET(p, c) IO_WRITE(p, (IO_READ(p) | (c))) 739 #define IO_CLEAR(p, c) IO_WRITE(p, (IO_READ(p) & ~(c))) 740 #define RX_DATA(s) (((s) & OMAHA_URX_FULL)) 741 #define TX_READY(s) (((s) & OMAHA_UTX_EMPTY)) 742 #define TX_EMPTY(p) ((GET_STATUS(p) & OMAHA_UTX_EMPTY) != 0) 743 744 745 /* ----------------------------------------------------------------------- 746 * Timer definitions 747 * 748 * There are 5 16-bit countdown timers on-chip. 749 * These are all driven by PCLK, running at whatever Mhz. 750 * For now we shall clock all the timers at 1MHz (arranged by uHAL) 751 */ 752 753 #define PLAT_TIMER1_BASE (PLAT_PERIPHERAL_BASE + OMAHA_TCNTB0) 754 #define PLAT_TIMER2_BASE (PLAT_PERIPHERAL_BASE + OMAHA_TCNTB1) 755 #define PLAT_TIMER3_BASE (PLAT_PERIPHERAL_BASE + OMAHA_TCNTB2) 756 #define PLAT_TIMER4_BASE (PLAT_PERIPHERAL_BASE + OMAHA_TCNTB3) 757 #define PLAT_TIMER5_BASE (PLAT_PERIPHERAL_BASE + OMAHA_TCNTB4) 758 759 760 #define MAX_TIMER 5 761 /* Maximum time interval we can handle (in microseconds) 762 * = max_ticks / ticks_per_us ( = 65535 / 0.2) 763 */ 764 765 /* Maximum period in uSecs 766 */ 767 #define MAX_PERIOD 131072 768 769 #define PLAT_uS_TO_TICK(t) (t*1) 770 771 /* These are useconds NOT ticks. 772 */ 773 #define mSEC_1 1000 774 #define mSEC_5 (mSEC_1 * 5) 775 #define mSEC_10 (mSEC_1 * 10) 776 #define mSEC_25 (mSEC_1 * 25) 777 #define SEC_1 (mSEC_1 * 1000) 778 779 /* SEMIHOSTED Debugger doesn't use a timer by default. If it requires a 780 * timer (eg for profiling), set HOST_TIMER to MAX_TIMER 781 */ 782 #define HOST_TIMER 0 783 #define OS_TIMER 1 784 #define OS_TIMERINT OMAHA_INT_TIMER1 785 786 787 /* Timer definitions. 788 * The irq numbers & base addresses of the individual timers 789 */ 790 #define TIMER_VECTORS {0, OMAHA_INT_TIMER0, OMAHA_INT_TIMER1, OMAHA_INT_TIMER2, OMAHA_INT_TIMER3, OMAHA_INT_TIMER4} 791 #define TIMER_BASES {0, (void *)PLAT_TIMER1_BASE, (void *)PLAT_TIMER2_BASE, (void *)PLAT_TIMER3_BASE, (void *)PLAT_TIMER4_BASE, (void *)PLAT_TIMER5_BASE} 792 793 794 /* ----------------------------------------------------------------------- 795 * Number of Level2 table entries in uHAL_AddressTable 796 * Each entry contains 256 32-bit descriptors 797 */ 798 #define L2_TABLE_ENTRIES 0 799 800 801 /* macros to map from PCI memory/IO addresses to local bus addresses 802 */ 803 #define _MapAddress(a) (a) 804 #define _MapIOAddress(a) (a) 805 #define _MapMemAddress(a) (a) 806 807 808 #define ALLBITS 0xffffffff 809 810 811 #ifdef uHAL_HEAP 812 #if USE_C_LIBRARY != 0 813 #define uHAL_HEAP_BASE (PLAT_SDRAM_BASE + SZ_1M) 814 #define uHAL_HEAP_SIZE (SZ_16M - SZ_1M - SZ_1M - 4) 815 #define uHAL_STACK_BASE SZ_16M 816 #define uHAL_STACK_SIZE SZ_1M 817 #else 818 #define uHAL_HEAP_BASE (PLAT_SDRAM_BASE + PLAT_SDRAM_SIZE - SZ_64K) 819 #define uHAL_HEAP_SIZE SZ_16K 820 #define uHAL_STACK_SIZE SZ_16K 821 #define uHAL_STACK_BASE (uHAL_HEAP_BASE + SZ32K) 822 #endif 823 #endif 824 825 826 #endif 827 828 /* END */ 829 830