1 /* 2 * PowerPC memory management structures 3 */ 4 5 #ifdef __KERNEL__ 6 #ifndef _PPC_MMU_H_ 7 #define _PPC_MMU_H_ 8 9 #include <linux/config.h> 10 11 #ifndef __ASSEMBLY__ 12 13 /* 14 * Define physical address type. Machines using split size 15 * virtual/physical addressing like 32-bit virtual / 36-bit 16 * physical need a larger than native word size type. -Matt 17 */ 18 #ifdef CONFIG_PTE_64BIT 19 typedef unsigned long long phys_addr_t; 20 extern phys_addr_t fixup_bigphys_addr(phys_addr_t, phys_addr_t); 21 #else 22 typedef unsigned long phys_addr_t; 23 #endif 24 25 /* Default "unsigned long" context */ 26 typedef unsigned long mm_context_t; 27 28 /* Hardware Page Table Entry */ 29 typedef struct _PTE { 30 #ifdef CONFIG_PPC64BRIDGE 31 unsigned long long vsid:52; 32 unsigned long api:5; 33 unsigned long :5; 34 unsigned long h:1; 35 unsigned long v:1; 36 unsigned long long rpn:52; 37 #else /* CONFIG_PPC64BRIDGE */ 38 unsigned long v:1; /* Entry is valid */ 39 unsigned long vsid:24; /* Virtual segment identifier */ 40 unsigned long h:1; /* Hash algorithm indicator */ 41 unsigned long api:6; /* Abbreviated page index */ 42 unsigned long rpn:20; /* Real (physical) page number */ 43 #endif /* CONFIG_PPC64BRIDGE */ 44 unsigned long :3; /* Unused */ 45 unsigned long r:1; /* Referenced */ 46 unsigned long c:1; /* Changed */ 47 unsigned long w:1; /* Write-thru cache mode */ 48 unsigned long i:1; /* Cache inhibited */ 49 unsigned long m:1; /* Memory coherence */ 50 unsigned long g:1; /* Guarded */ 51 unsigned long :1; /* Unused */ 52 unsigned long pp:2; /* Page protection */ 53 } PTE; 54 55 extern PTE *Hash, *Hash_end; 56 extern unsigned long Hash_size, Hash_mask; 57 58 /* Values for PP (assumes Ks=0, Kp=1) */ 59 #define PP_RWXX 0 /* Supervisor read/write, User none */ 60 #define PP_RWRX 1 /* Supervisor read/write, User read */ 61 #define PP_RWRW 2 /* Supervisor read/write, User read/write */ 62 #define PP_RXRX 3 /* Supervisor read, User read */ 63 64 /* Segment Register */ 65 typedef struct _SEGREG { 66 unsigned long t:1; /* Normal or I/O type */ 67 unsigned long ks:1; /* Supervisor 'key' (normally 0) */ 68 unsigned long kp:1; /* User 'key' (normally 1) */ 69 unsigned long n:1; /* No-execute */ 70 unsigned long :4; /* Unused */ 71 unsigned long vsid:24; /* Virtual Segment Identifier */ 72 } SEGREG; 73 74 /* Block Address Translation (BAT) Registers */ 75 typedef struct _P601_BATU { /* Upper part of BAT for 601 processor */ 76 unsigned long bepi:15; /* Effective page index (virtual address) */ 77 unsigned long :8; /* unused */ 78 unsigned long w:1; 79 unsigned long i:1; /* Cache inhibit */ 80 unsigned long m:1; /* Memory coherence */ 81 unsigned long ks:1; /* Supervisor key (normally 0) */ 82 unsigned long kp:1; /* User key (normally 1) */ 83 unsigned long pp:2; /* Page access protections */ 84 } P601_BATU; 85 86 typedef struct _BATU { /* Upper part of BAT (all except 601) */ 87 #ifdef CONFIG_PPC64BRIDGE 88 unsigned long long bepi:47; 89 #else /* CONFIG_PPC64BRIDGE */ 90 unsigned long bepi:15; /* Effective page index (virtual address) */ 91 #endif /* CONFIG_PPC64BRIDGE */ 92 unsigned long :4; /* Unused */ 93 unsigned long bl:11; /* Block size mask */ 94 unsigned long vs:1; /* Supervisor valid */ 95 unsigned long vp:1; /* User valid */ 96 } BATU; 97 98 typedef struct _P601_BATL { /* Lower part of BAT for 601 processor */ 99 unsigned long brpn:15; /* Real page index (physical address) */ 100 unsigned long :10; /* Unused */ 101 unsigned long v:1; /* Valid bit */ 102 unsigned long bl:6; /* Block size mask */ 103 } P601_BATL; 104 105 typedef struct _BATL { /* Lower part of BAT (all except 601) */ 106 #ifdef CONFIG_PPC64BRIDGE 107 unsigned long long brpn:47; 108 #else /* CONFIG_PPC64BRIDGE */ 109 unsigned long brpn:15; /* Real page index (physical address) */ 110 #endif /* CONFIG_PPC64BRIDGE */ 111 unsigned long :10; /* Unused */ 112 unsigned long w:1; /* Write-thru cache */ 113 unsigned long i:1; /* Cache inhibit */ 114 unsigned long m:1; /* Memory coherence */ 115 unsigned long g:1; /* Guarded (MBZ in IBAT) */ 116 unsigned long :1; /* Unused */ 117 unsigned long pp:2; /* Page access protections */ 118 } BATL; 119 120 typedef struct _BAT { 121 BATU batu; /* Upper register */ 122 BATL batl; /* Lower register */ 123 } BAT; 124 125 typedef struct _P601_BAT { 126 P601_BATU batu; /* Upper register */ 127 P601_BATL batl; /* Lower register */ 128 } P601_BAT; 129 130 extern void _tlbie(unsigned long va); /* invalidate a TLB entry */ 131 extern void _tlbia(void); /* invalidate all TLB entries */ 132 133 #endif /* __ASSEMBLY__ */ 134 135 /* Block size masks */ 136 #define BL_128K 0x000 137 #define BL_256K 0x001 138 #define BL_512K 0x003 139 #define BL_1M 0x007 140 #define BL_2M 0x00F 141 #define BL_4M 0x01F 142 #define BL_8M 0x03F 143 #define BL_16M 0x07F 144 #define BL_32M 0x0FF 145 #define BL_64M 0x1FF 146 #define BL_128M 0x3FF 147 #define BL_256M 0x7FF 148 149 /* BAT Access Protection */ 150 #define BPP_XX 0x00 /* No access */ 151 #define BPP_RX 0x01 /* Read only */ 152 #define BPP_RW 0x02 /* Read/write */ 153 154 /* Control/status registers for the MPC8xx. 155 * A write operation to these registers causes serialized access. 156 * During software tablewalk, the registers used perform mask/shift-add 157 * operations when written/read. A TLB entry is created when the Mx_RPN 158 * is written, and the contents of several registers are used to 159 * create the entry. 160 */ 161 #define MI_CTR 784 /* Instruction TLB control register */ 162 #define MI_GPM 0x80000000 /* Set domain manager mode */ 163 #define MI_PPM 0x40000000 /* Set subpage protection */ 164 #define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ 165 #define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */ 166 #define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ 167 #define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */ 168 #define MI_RESETVAL 0x00000000 /* Value of register at reset */ 169 170 /* These are the Ks and Kp from the PowerPC books. For proper operation, 171 * Ks = 0, Kp = 1. 172 */ 173 #define MI_AP 786 174 #define MI_Ks 0x80000000 /* Should not be set */ 175 #define MI_Kp 0x40000000 /* Should always be set */ 176 177 /* The effective page number register. When read, contains the information 178 * about the last instruction TLB miss. When MI_RPN is written, bits in 179 * this register are used to create the TLB entry. 180 */ 181 #define MI_EPN 787 182 #define MI_EPNMASK 0xfffff000 /* Effective page number for entry */ 183 #define MI_EVALID 0x00000200 /* Entry is valid */ 184 #define MI_ASIDMASK 0x0000000f /* ASID match value */ 185 /* Reset value is undefined */ 186 187 /* A "level 1" or "segment" or whatever you want to call it register. 188 * For the instruction TLB, it contains bits that get loaded into the 189 * TLB entry when the MI_RPN is written. 190 */ 191 #define MI_TWC 789 192 #define MI_APG 0x000001e0 /* Access protection group (0) */ 193 #define MI_GUARDED 0x00000010 /* Guarded storage */ 194 #define MI_PSMASK 0x0000000c /* Mask of page size bits */ 195 #define MI_PS8MEG 0x0000000c /* 8M page size */ 196 #define MI_PS512K 0x00000004 /* 512K page size */ 197 #define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */ 198 #define MI_SVALID 0x00000001 /* Segment entry is valid */ 199 /* Reset value is undefined */ 200 201 /* Real page number. Defined by the pte. Writing this register 202 * causes a TLB entry to be created for the instruction TLB, using 203 * additional information from the MI_EPN, and MI_TWC registers. 204 */ 205 #define MI_RPN 790 206 207 /* Define an RPN value for mapping kernel memory to large virtual 208 * pages for boot initialization. This has real page number of 0, 209 * large page size, shared page, cache enabled, and valid. 210 * Also mark all subpages valid and write access. 211 */ 212 #define MI_BOOTINIT 0x000001fd 213 214 #define MD_CTR 792 /* Data TLB control register */ 215 #define MD_GPM 0x80000000 /* Set domain manager mode */ 216 #define MD_PPM 0x40000000 /* Set subpage protection */ 217 #define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ 218 #define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */ 219 #define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */ 220 #define MD_TWAM 0x04000000 /* Use 4K page hardware assist */ 221 #define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ 222 #define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */ 223 #define MD_RESETVAL 0x04000000 /* Value of register at reset */ 224 225 #define M_CASID 793 /* Address space ID (context) to match */ 226 #define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */ 227 228 229 /* These are the Ks and Kp from the PowerPC books. For proper operation, 230 * Ks = 0, Kp = 1. 231 */ 232 #define MD_AP 794 233 #define MD_Ks 0x80000000 /* Should not be set */ 234 #define MD_Kp 0x40000000 /* Should always be set */ 235 236 /* The effective page number register. When read, contains the information 237 * about the last instruction TLB miss. When MD_RPN is written, bits in 238 * this register are used to create the TLB entry. 239 */ 240 #define MD_EPN 795 241 #define MD_EPNMASK 0xfffff000 /* Effective page number for entry */ 242 #define MD_EVALID 0x00000200 /* Entry is valid */ 243 #define MD_ASIDMASK 0x0000000f /* ASID match value */ 244 /* Reset value is undefined */ 245 246 /* The pointer to the base address of the first level page table. 247 * During a software tablewalk, reading this register provides the address 248 * of the entry associated with MD_EPN. 249 */ 250 #define M_TWB 796 251 #define M_L1TB 0xfffff000 /* Level 1 table base address */ 252 #define M_L1INDX 0x00000ffc /* Level 1 index, when read */ 253 /* Reset value is undefined */ 254 255 /* A "level 1" or "segment" or whatever you want to call it register. 256 * For the data TLB, it contains bits that get loaded into the TLB entry 257 * when the MD_RPN is written. It is also provides the hardware assist 258 * for finding the PTE address during software tablewalk. 259 */ 260 #define MD_TWC 797 261 #define MD_L2TB 0xfffff000 /* Level 2 table base address */ 262 #define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */ 263 #define MD_APG 0x000001e0 /* Access protection group (0) */ 264 #define MD_GUARDED 0x00000010 /* Guarded storage */ 265 #define MD_PSMASK 0x0000000c /* Mask of page size bits */ 266 #define MD_PS8MEG 0x0000000c /* 8M page size */ 267 #define MD_PS512K 0x00000004 /* 512K page size */ 268 #define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */ 269 #define MD_WT 0x00000002 /* Use writethrough page attribute */ 270 #define MD_SVALID 0x00000001 /* Segment entry is valid */ 271 /* Reset value is undefined */ 272 273 274 /* Real page number. Defined by the pte. Writing this register 275 * causes a TLB entry to be created for the data TLB, using 276 * additional information from the MD_EPN, and MD_TWC registers. 277 */ 278 #define MD_RPN 798 279 280 /* This is a temporary storage register that could be used to save 281 * a processor working register during a tablewalk. 282 */ 283 #define M_TW 799 284 285 /* 286 * At present, all PowerPC 400-class processors share a similar TLB 287 * architecture. The instruction and data sides share a unified, 288 * 64-entry, fully-associative TLB which is maintained totally under 289 * software control. In addition, the instruction side has a 290 * hardware-managed, 4-entry, fully- associative TLB which serves as a 291 * first level to the shared TLB. These two TLBs are known as the UTLB 292 * and ITLB, respectively. 293 */ 294 295 #define PPC4XX_TLB_SIZE 64 296 297 /* 298 * TLB entries are defined by a "high" tag portion and a "low" data 299 * portion. On all architectures, the data portion is 32-bits. 300 * 301 * TLB entries are managed entirely under software control by reading, 302 * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx 303 * instructions. 304 */ 305 306 #define TLB_LO 1 307 #define TLB_HI 0 308 309 #define TLB_DATA TLB_LO 310 #define TLB_TAG TLB_HI 311 312 /* Tag portion */ 313 314 #define TLB_EPN_MASK 0xFFFFFC00 /* Effective Page Number */ 315 #define TLB_PAGESZ_MASK 0x00000380 316 #define TLB_PAGESZ(x) (((x) & 0x7) << 7) 317 #define PAGESZ_1K 0 318 #define PAGESZ_4K 1 319 #define PAGESZ_16K 2 320 #define PAGESZ_64K 3 321 #define PAGESZ_256K 4 322 #define PAGESZ_1M 5 323 #define PAGESZ_4M 6 324 #define PAGESZ_16M 7 325 #define TLB_VALID 0x00000040 /* Entry is valid */ 326 327 /* Data portion */ 328 329 #define TLB_RPN_MASK 0xFFFFFC00 /* Real Page Number */ 330 #define TLB_PERM_MASK 0x00000300 331 #define TLB_EX 0x00000200 /* Instruction execution allowed */ 332 #define TLB_WR 0x00000100 /* Writes permitted */ 333 #define TLB_ZSEL_MASK 0x000000F0 334 #define TLB_ZSEL(x) (((x) & 0xF) << 4) 335 #define TLB_ATTR_MASK 0x0000000F 336 #define TLB_W 0x00000008 /* Caching is write-through */ 337 #define TLB_I 0x00000004 /* Caching is inhibited */ 338 #define TLB_M 0x00000002 /* Memory is coherent */ 339 #define TLB_G 0x00000001 /* Memory is guarded from prefetch */ 340 341 /* 342 * PPC44x support 343 */ 344 #define PPC44x_MMUCR_TID 0x000000ff 345 #define PPC44x_MMUCR_STS 0x00010000 346 347 #define PPC44x_TLB_PAGEID 0 348 #define PPC44x_TLB_XLAT 1 349 #define PPC44x_TLB_ATTRIB 2 350 351 /* Page identification fields */ 352 #define PPC44x_TLB_EPN_MASK 0xfffffc00 /* Effective Page Number */ 353 #define PPC44x_TLB_VALID 0x00000200 /* Valid flag */ 354 #define PPC44x_TLB_TS 0x00000100 /* Translation address space */ 355 #define PPC44x_TLB_PAGESZ_MASK 0x000000f0 356 #define PPC44x_TLB_PAGESZ(x) (x << 4) 357 #define PPC44x_PAGESZ_1K 0 358 #define PPC44x_PAGESZ_4K 1 359 #define PPC44x_PAGESZ_16K 2 360 #define PPC44x_PAGESZ_64K 3 361 #define PPC44x_PAGESZ_256K 4 362 #define PPC44x_PAGESZ_1M 5 363 #define PPC44x_PAGESZ_16M 7 364 #define PPC44x_PAGESZ_256M 9 365 366 /* Translation fields */ 367 #define PPC44x_TLB_RPN_MASK 0xfffffc00 /* Real Page Number */ 368 #define PPC44x_TLB_ERPN_MASK 0x0000000f 369 370 /* Storage attribute and access control fields */ 371 #define PPC44x_TLB_ATTR_MASK 0x0000ff80 372 #define PPC44x_TLB_U0 0x00008000 /* User 0 */ 373 #define PPC44x_TLB_U1 0x00004000 /* User 1 */ 374 #define PPC44x_TLB_U2 0x00002000 /* User 2 */ 375 #define PPC44x_TLB_U3 0x00001000 /* User 3 */ 376 #define PPC44x_TLB_W 0x00000800 /* Caching is write-through */ 377 #define PPC44x_TLB_I 0x00000400 /* Caching is inhibited */ 378 #define PPC44x_TLB_M 0x00000200 /* Memory is coherent */ 379 #define PPC44x_TLB_G 0x00000100 /* Memory is guarded */ 380 #define PPC44x_TLB_E 0x00000080 /* Memory is guarded */ 381 382 #define PPC44x_TLB_PERM_MASK 0x0000003f 383 #define PPC44x_TLB_UX 0x00000020 /* User execution */ 384 #define PPC44x_TLB_UW 0x00000010 /* User write */ 385 #define PPC44x_TLB_UR 0x00000008 /* User read */ 386 #define PPC44x_TLB_SX 0x00000004 /* Super execution */ 387 #define PPC44x_TLB_SW 0x00000002 /* Super write */ 388 #define PPC44x_TLB_SR 0x00000001 /* Super read */ 389 390 #endif /* _PPC_MMU_H_ */ 391 #endif /* __KERNEL__ */ 392